summaryrefslogtreecommitdiffstats
path: root/src/cpu/samsung/exynos5250/dmc_common.c
diff options
context:
space:
mode:
authorRonald G. Minnich <rminnich@gmail.com>2013-01-29 14:35:35 -0800
committerDavid Hendricks <dhendrix@chromium.org>2013-01-30 21:39:22 +0100
commitb7e05358621344e0d777853c34960944d680f804 (patch)
tree1735417d681ed532639120626598d63e902c00c0 /src/cpu/samsung/exynos5250/dmc_common.c
parent21d0fc0d3701d1c359fb4d4267383aeaa5886a7e (diff)
downloadcoreboot-staging-b7e05358621344e0d777853c34960944d680f804.zip
coreboot-staging-b7e05358621344e0d777853c34960944d680f804.tar.gz
Exynos5250: Get DDR3 working by changing what is compiled and add a function
This is a minor set of changes to get DDR3 going. Move compilation of DDR3 startup to the romstage. Fix a prototype that was missing a void. Remove a function that is overly flexible, and even though it is overly flexible only actually can handle one type of RAM. Mainboards only support one type of DRAM, so create a function to explicitly initialize the type of DDR we have -- DDR3. With these changes, and the previous changes, google snow is ready to run the ramstage. Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/cpu/samsung/exynos5250/dmc_common.c')
-rw-r--r--src/cpu/samsung/exynos5250/dmc_common.c21
1 files changed, 2 insertions, 19 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c
index 35a13ac..f91cbb3 100644
--- a/src/cpu/samsung/exynos5250/dmc_common.c
+++ b/src/cpu/samsung/exynos5250/dmc_common.c
@@ -26,6 +26,8 @@
#include <common.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/setup.h>
+#include <cpu/samsung/exynos5250/dmc.h>
+#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5-common/spl.h>
#include <system.h>
@@ -179,22 +181,3 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
}
-void mem_ctrl_init()
-{
- struct spl_machine_param *param = spl_get_machine_params();
- struct mem_timings *mem;
- int ret;
-
- mem = clock_get_mem_timings();
-
- /* If there are any other memory variant, add their init call below */
- if (param->mem_type == DDR_MODE_DDR3) {
- ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
- if (ret) {
- printk(BIOS_ERR, "Memory controller init failed, err: %u", ret);
- BUG();
- }
- } else {
- die("Unknown memory type");
- }
-}
OpenPOWER on IntegriCloud