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author | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
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committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
commit | fcd5ace00b333ce31b11b02a2243dfbf39307f10 (patch) | |
tree | d686d752ccea9b185b0008c70d8523749b26e2dd /src/cpu/amd/model_fxx/apic_timer.c | |
parent | 98e619b1cefcb9871185f4cc3db85fa430dcdbce (diff) | |
download | coreboot-staging-fcd5ace00b333ce31b11b02a2243dfbf39307f10.zip coreboot-staging-fcd5ace00b333ce31b11b02a2243dfbf39307f10.tar.gz |
- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_fxx/apic_timer.c')
-rw-r--r-- | src/cpu/amd/model_fxx/apic_timer.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c new file mode 100644 index 0000000..5a81f91 --- /dev/null +++ b/src/cpu/amd/model_fxx/apic_timer.c @@ -0,0 +1,26 @@ +#include <stdint.h> +#include <delay.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); +} + +void udelay(unsigned usecs) +{ + uint32_t start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); + +} |