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| author | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:20:07 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:20:07 +0000 |
| commit | 8127dc41d1fde1118cdbe3bf6b592312b5b85c02 (patch) | |
| tree | 08827883b0bff5c400452aba8fc3b2a93df4cdb2 /src/cpu/amd/model_10xxx/init_cpus.c | |
| parent | c74e3627233558c62e93beb37efa271f0f353f8d (diff) | |
| download | coreboot-staging-8127dc41d1fde1118cdbe3bf6b592312b5b85c02.zip coreboot-staging-8127dc41d1fde1118cdbe3bf6b592312b5b85c02.tar.gz | |
Update the FAM10 microcode to current versions.
In addition, AP microcode is now updated in early initialization to support errata settings that require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_10xxx/init_cpus.c')
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 5c17a9a..16b5a3d 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -53,6 +53,7 @@ static inline void print_initcpu(const char *strval, u32 val) } +void update_microcode(u32 cpu_deviceid); static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); @@ -391,6 +392,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) * This happens after HTinit. * The BSP runs this code in it's own path. */ + update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); |
