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author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:23:54 -0600 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:59 +0200 |
commit | 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch) | |
tree | 6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/amd/geode_gx2/cpureginit.c | |
parent | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff) | |
download | coreboot-staging-4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c.zip coreboot-staging-4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c.tar.gz |
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/geode_gx2/cpureginit.c')
-rw-r--r-- | src/cpu/amd/geode_gx2/cpureginit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c index 0fc852d..e0ecd62 100644 --- a/src/cpu/amd/geode_gx2/cpureginit.c +++ b/src/cpu/amd/geode_gx2/cpureginit.c @@ -15,7 +15,7 @@ void cpuRegInit (void) /* Set up GLCP to grab BTM data. */ msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ + msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ @@ -119,7 +119,7 @@ void cpuRegInit (void) wrmsr(msrnum, msr); } -/* FPU impercise exceptions bit */ +/* FPU imprecise exceptions bit */ { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); |