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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-13 09:39:15 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-13 21:04:56 +0200 |
commit | 6cb3a59fd5e754c3627b79db21c5bcc284bfd721 (patch) | |
tree | e83db5b11ee4a29d496dcf2798d024b6b8455ab7 /src/arch/x86/pci_ops_mmconf.c | |
parent | 9693885ad88d21ead7bd9ebc32f3e4901841b18b (diff) | |
download | coreboot-staging-6cb3a59fd5e754c3627b79db21c5bcc284bfd721.zip coreboot-staging-6cb3a59fd5e754c3627b79db21c5bcc284bfd721.tar.gz |
It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.
This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.
Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86/pci_ops_mmconf.c')
-rw-r--r-- | src/arch/x86/pci_ops_mmconf.c | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/src/arch/x86/pci_ops_mmconf.c b/src/arch/x86/pci_ops_mmconf.c new file mode 100644 index 0000000..e4fa128 --- /dev/null +++ b/src/arch/x86/pci_ops_mmconf.c @@ -0,0 +1,61 @@ +#include <console/console.h> +#include <arch/io.h> +#include <arch/pciconf.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +/* + * Functions for accessing PCI configuration space with mmconf accesses + */ + +#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \ + ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\ + (((SEGBUS) & 0xFFF) << 20) |\ + (((DEVFN) & 0xFF) << 12) |\ + ((WHERE) & 0xFFF)) & ~MASK)) + +static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, + int where) +{ + return read8(PCI_MMIO_ADDR(bus, devfn, where, 0)); +} + +static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, + int where) +{ + return read16(PCI_MMIO_ADDR(bus, devfn, where, 1)); +} + +static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, + int where) +{ + return read32(PCI_MMIO_ADDR(bus, devfn, where, 3)); +} + +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, + int where, uint8_t value) +{ + write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value); +} + +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, + int where, uint16_t value) +{ + write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value); +} + +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, + int where, uint32_t value) +{ + write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value); +} + +const struct pci_bus_operations pci_ops_mmconf = { + .read8 = pci_mmconf_read_config8, + .read16 = pci_mmconf_read_config16, + .read32 = pci_mmconf_read_config32, + .write8 = pci_mmconf_write_config8, + .write16 = pci_mmconf_write_config16, + .write32 = pci_mmconf_write_config32, +}; |