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| author | Martin Roth <gaumless@gmail.com> | 2015-06-19 23:17:15 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-23 09:42:44 +0200 |
| commit | 026e4dc3ffb909c2cbf98dffb8156929e4b1e7a3 (patch) | |
| tree | e7c776ab0b789890206d07923e8a0d1d16a3faf1 /src/Kconfig | |
| parent | 633886719e2853744d932bd15324dd21634b0bbb (diff) | |
| download | coreboot-staging-026e4dc3ffb909c2cbf98dffb8156929e4b1e7a3.zip coreboot-staging-026e4dc3ffb909c2cbf98dffb8156929e4b1e7a3.tar.gz | |
Kconfig: Move CBFS_SIZE into Mainboard menu
The CBFS size is really mainboard specific, since it really depends on
size of the chip on the mainboard, so it makes sense to have it in
the mainboard menu along with the ROM-chip size.
- Move the CBFS_SIZE definition up in src/kconfig
- Move the Mainboard Menu markers out of src/mainboard/kconfig into
src/Kconfig so CBFS_SIZE can live in the mainboard menu.
- Add a long list setting default values to do what the chipset
directories were previously defaulting the values to. This will
be trimmed down in a following patch that creates a common set of
IFD routines. (Who knew that kconfig supported line wrapping?)
- Update the help text.
Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10610
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/src/Kconfig b/src/Kconfig index c282d21..91a3b29 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -332,8 +332,31 @@ endmenu source "src/acpi/Kconfig" +menu "Mainboard" + source "src/mainboard/Kconfig" +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ + NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ + NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \ + NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ + SOC_INTEL_BROADWELL + default 0x200000 if SOC_INTEL_FSP_BAYTRAIL + default ROM_SIZE + help + This is the part of the ROM actually managed by CBFS, located at the + end of the ROM (passed through cbfstool -o) on x86 and at at the start + of the ROM (passed through cbfstool -s) everywhere else. It defaults + to span the whole ROM on all but Intel systems that use an Intel Firmware + Descriptor. It can be overridden to make coreboot live alongside other + components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE + binaries. + +endmenu + config SYSTEM_TYPE_LAPTOP default n bool @@ -482,16 +505,6 @@ config IOAPIC bool default n -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default ROM_SIZE - help - This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start - of the ROM (passed through cbfstool -s) everywhere else. Defaults to - span the whole ROM but can be overwritten to make coreboot live - alongside other components (like ChromeOS's vboot/FMAP). - config CACHE_ROM_SIZE_OVERRIDE hex default 0 |
