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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-08-06 19:22:53 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-21 02:04:21 +0100 |
| commit | f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d (patch) | |
| tree | 353035a4ba6a24cf8bef75adb77ecb28f84ae0bf | |
| parent | fb5647a60bbe56b654a9ce9d8e9f307b1d9fd10d (diff) | |
| download | coreboot-staging-f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d.zip coreboot-staging-f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d.tar.gz | |
imgtec/pistachio: increase CBFS cache
Increase CBFS cache size to allow for a bigger payload.
Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index ce0063f..edf9c41 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -26,8 +26,8 @@ SECTIONS DRAM_START(0x00000000) /* DMA coherent area: accessed via KSEG1. */ DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 192K) - RAMSTAGE(0x00230000, 128K) + POSTRAM_CBFS_CACHE(0x00200000, 512K) + RAMSTAGE(0x00280000, 128K) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock |
