diff options
author | Myles Watson <mylesgw@gmail.com> | 2010-03-11 21:34:27 +0000 |
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committer | Myles Watson <mylesgw@gmail.com> | 2010-03-11 21:34:27 +0000 |
commit | ed15220b87d298088a074747b24e212c23333e33 (patch) | |
tree | 08baf8485e130591af1edd889333f3cef998c01c | |
parent | bc259d09d342f09987c65290422009615a8287a7 (diff) | |
download | coreboot-staging-ed15220b87d298088a074747b24e212c23333e33.zip coreboot-staging-ed15220b87d298088a074747b24e212c23333e33.tar.gz |
Replace clear_memory with memset.
Replace set_init_ram_access with the call to set_var_mtrr.
Remove unused #include statments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r-- | src/cpu/amd/car/clear_init_ram.c | 23 | ||||
-rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 12 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 3 | ||||
-rw-r--r-- | src/include/cpu/x86/mem.h | 16 | ||||
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/e7520/raminit.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/e7525/raminit.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/i3100/raminit.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/i945/raminit.c | 1 |
19 files changed, 11 insertions, 60 deletions
diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c deleted file mode 100644 index 624e0fe..0000000 --- a/src/cpu/amd/car/clear_init_ram.c +++ /dev/null @@ -1,23 +0,0 @@ -/* by yhlu 6.2005 */ -/* be warned, this file will be used core 0/node 0 only */ - -static void __attribute__((noinline)) clear_init_ram(void) -{ - // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram - // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already - // so noline clear_init_ram - -#if CONFIG_HAVE_ACPI_RESUME == 1 - /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); -#else - clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); -#endif -} - -/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ -static void set_init_ram_access(void) -{ - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); -} - diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 5c085cd..10194b9 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -3,8 +3,6 @@ */ #include "cpu/amd/car/disable_cache_as_ram.c" -#include "cpu/amd/car/clear_init_ram.c" - static inline void print_debug_pcar(const char *strval, uint32_t val) { printk_debug("%s%08x\r\n", strval, val); @@ -64,7 +62,8 @@ static void post_cache_as_ram(void) #error "You need to set CONFIG_RAMTOP greater than 1M" #endif - set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */ + /* So we can access RAM from [1M, CONFIG_RAMTOP) */ + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); @@ -94,7 +93,12 @@ static void post_cache_as_ram(void) disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP)) +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ + memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0); +#else + memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0); +#endif print_debug("Done\r\n"); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 822e362..c43887f 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -421,7 +421,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) */ //wait_till_sysinfo_in_ram(); - set_init_ram_access(); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid); diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index daf3ece..6ef1f42 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -34,7 +34,6 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/mem.h> #include <cpu/amd/quadcore.h> #include <cpu/amd/model_10xxx_msr.h> diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 483399c..510c803 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -317,7 +317,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid); } lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu - set_init_ram_access(); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned) STOP_CAR_AND_CPU); diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 2d72618..b4a981b 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -24,7 +24,6 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/mem.h> #include <cpu/amd/dualcore.h> @@ -238,7 +237,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta /* clear memory 2M (limitk - basek) */ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10)); - clear_memory(addr, size); + memset(addr, size, 0); } static void init_ecc_memory(unsigned node_id) diff --git a/src/include/cpu/x86/mem.h b/src/include/cpu/x86/mem.h deleted file mode 100644 index 530c653..0000000 --- a/src/include/cpu/x86/mem.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef CPU_X86_MEM_H -#define CPU_X86_MEM_H - -/* Optimized generic x86 assembly for clearing memory */ -static inline void clear_memory(void *addr, unsigned long size) -{ - asm volatile( - "cld \n\t" - "rep; stosl\n\t" - : /* No outputs */ - : "a" (0), "D" (addr), "c" (size>>2) - ); - -} - -#endif /* CPU_X86_MEM_H */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 82a404b..0546a6d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -130,7 +130,6 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdht/ht_wrapper.c" -#include "include/cpu/x86/mem.h" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index f19147f..60a1e14 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdht/ht_wrapper.c" -#include "include/cpu/x86/mem.h" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 4ebc47f..9d870f0 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdht/ht_wrapper.c" -#include "include/cpu/x86/mem.h" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 749527f..1a19a14 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdht/ht_wrapper.c" -#include "include/cpu/x86/mem.h" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 45d0d94..337750b 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdht/ht_wrapper.c" -#include "include/cpu/x86/mem.h" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 22b672f..0e27a16 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -4,7 +4,6 @@ 2005.02 yhlu add E0 memory hole support */ -#include <cpu/x86/mem.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <stdlib.h> diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index aaf60a8..601c035 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -20,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/mem.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 27ed477..bb4ebbd 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -18,7 +18,6 @@ * */ -#include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <stdlib.h> diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 313dc0f..4aaa264 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -18,7 +18,6 @@ * */ -#include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 5aa4d9d..76475ce 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -19,7 +19,6 @@ * */ -#include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5e51361..9ad778b 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -19,7 +19,6 @@ * */ -#include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include "raminit_ep80579.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f65ccfa..3f73549 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <spd.h> |