updated to new svn repo

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 781 insertions, 33 deletions

diff --git a/src/cpu/amd/sc520/mmcr.h b/src/cpu/amd/sc520/mmcr.h
new file mode 100644
index 0000000..09690cb
--- /dev/null
+++ b/src/cpu/amd/sc520/mmcr.h
@@ -0,0 +1,284 @@
+struct memregs {
+	/* make these shorts, we are lsb and the hardware seems to like it 
+	 * better
+	 */
+	unsigned short drcctl;
+	unsigned short drctmctl;
+	unsigned short drccfg;
+	unsigned char pad1[2];
+	unsigned char drcbendadr[4];
+	unsigned char pad2[4];
+	unsigned char eccctl;
+	unsigned char eccsta;
+	unsigned char eccckbpos;
+	unsigned char ecccktest;
+	unsigned long eccsbadd;
+	unsigned long eccmbadd;
+	unsigned char pad3[18];
+};
+struct dbctl {
+	unsigned char dbctl;
+	unsigned char pad4[15];
+};
+	
+struct romregs {
+	unsigned char bootcs;
+	unsigned char pad5[3];
+	unsigned char romcs1;
+	unsigned char pad6[1];
+	unsigned char romcs2;
+	unsigned char pad7[6];
+};
+	
+
+struct hostbridge {
+	unsigned short hbctl;
+	unsigned short hbtgtirqctl;
+	unsigned short hbtgtirqsta;
+	unsigned short hbmstirqctl;
+	unsigned short hbmstirqsta;
+	unsigned char pad8[2];
+	unsigned long mstintadd;
+};
+
+struct sysarb {
+	unsigned char sysarbctl;
+	unsigned char pciarbsta;
+	unsigned char sysarbmenb;
+	unsigned long arbprictl;
+	unsigned char pad9[8];
+};
+
+struct sysmap {
+	unsigned char adddecctl;
+	unsigned char pada[1];
+	unsigned short wpvsta;
+	unsigned char padb[4];
+	unsigned long par[16];
+	unsigned char padc[0xb38];
+};
+
+struct gpctl {
+	unsigned char gpecho;
+	unsigned char gpcsdw;
+	unsigned char gpcsqual;
+	unsigned char padd[5];
+	unsigned char gpcsrt;
+	unsigned char gpcspw;
+	unsigned char gpcsoff;
+	unsigned char gprdw;
+	unsigned char gprdoff;
+	unsigned char gpwrw;
+	unsigned char gpwroff;
+	unsigned char gpalew;
+	unsigned char gpaleoff;
+	unsigned char pade[15];
+};
+
+struct pio {
+	unsigned short piopfs15_0;
+	unsigned short piopfs31_16;
+	unsigned char cspfs;
+	unsigned char padf[1];
+	unsigned char clksel;
+	unsigned char padg[1];
+	unsigned short dsctl;
+	unsigned short piodir15_0;
+	unsigned short piodir31_16;
+	unsigned short padh;
+	unsigned short piodata15_0;
+	unsigned short piodata31_16;
+	unsigned short pioset15_0;
+	unsigned short pioset31_16;
+	unsigned short pioclr15_0;
+	unsigned short pioclr31_16;
+	unsigned char padi[0x24];
+};
+
+struct swtmr {
+	unsigned short swtmrmilli;
+	unsigned short swtmrmicro;
+	unsigned char swtmrcfg;
+	unsigned char padj[0xb];
+};
+
+struct gptmr {
+	unsigned short ctl;
+	unsigned short cnt;
+	unsigned short maxcmpa, maxcmpb;
+};
+
+struct gptimers {
+	unsigned char status;
+	unsigned char pad;
+	struct gptmr timer[2];
+	/* yes, they REALLY DID make timer 2 different. */
+	/* yikes */
+	unsigned short ctl2;
+	unsigned short cnt2;
+	unsigned char paddumb[8];
+	unsigned short maxcmpa2;
+
+	unsigned char pada[0x20];
+};
+
+struct watchdog {
+	unsigned short ctl;
+	unsigned short cntll;
+        unsigned short cntlh;
+	unsigned char pad[10];
+};
+
+struct uart {
+	unsigned char ctl, sta, fcrshad, pad;
+};
+
+struct uarts {
+	struct uart uart[2];
+	unsigned char pad[8];
+};
+
+struct ssi {
+	unsigned char ctl, xmit, cmd, sta, rcv;
+	unsigned char pad[0x2b];
+};
+
+	
+/* interrupt control registers */
+/* defined this way for portability. Shame we can't just use plan 9 c. */
+struct pic {
+	unsigned char pcicr;
+	unsigned char pad1;
+	unsigned char mpicmode;
+	unsigned char sl1picmode;
+	unsigned char sl2picmode;
+	unsigned char pad2[3];
+	unsigned char swint16_1;
+	unsigned char pad3;
+	unsigned char swint22_17;
+	unsigned char pad4[5];
+	unsigned short intpinpol;
+	unsigned char pad5[2];
+	unsigned char pichostmap;
+	unsigned char pad6[3];
+	unsigned char eccmap;
+	unsigned char pad7[1];
+	unsigned char gptmr0map;
+	unsigned char gptmr1map;
+	unsigned char gptmr2map;
+	unsigned char pad8[3];
+	unsigned char pit0map;
+	unsigned char pit1map;
+	unsigned char pit2map;
+	unsigned char pad9[5];
+	unsigned char uart1map;
+	unsigned char uart2map;
+	unsigned char pad99[6];
+	unsigned char pciintamap;
+	unsigned char pciintbmap;
+	unsigned char pciintcmap;
+	unsigned char pciintdmap;
+	unsigned char pad10[12];
+	unsigned char dmabcintmap;
+	unsigned char ssimap;
+	unsigned char wdtmap;
+	unsigned char rtcmap;
+	unsigned char wpvmap;
+	unsigned char icemap;
+	unsigned char ferrmap;
+	unsigned char pad11[9];
+	unsigned char gp0imap;
+	unsigned char gp1imap;
+	unsigned char gp2imap;
+	unsigned char gp3imap;
+	unsigned char gp4imap;
+	unsigned char gp5imap;
+	unsigned char gp6imap;
+	unsigned char gp7imap;
+	unsigned char gp8imap;
+	unsigned char gp9imap;
+	unsigned char gp10imap;
+	unsigned char padend[0x14];
+}; 
+
+struct reset {
+	unsigned char sysinfo;
+	unsigned char pad1;
+	unsigned char rescfg;
+	unsigned char pad2;
+	unsigned char ressta;
+	unsigned char pad3[0xb];
+};
+
+struct dmacontrol {
+	unsigned char ctl;
+	unsigned char mmio;
+	unsigned short extchanmapa;
+	unsigned short extchanmapb;
+	unsigned char extpg0;
+	unsigned char extpg1;
+	unsigned char extpg2;
+	unsigned char extpg3;
+	unsigned char extpg5;
+	unsigned char extpg6;
+	unsigned char extpg7;
+	unsigned char pad[3];
+	unsigned char exttc3;
+	unsigned char exttc5;
+	unsigned char exttc6;
+	unsigned char exttc7;
+	unsigned char pad1[4];
+	unsigned char bcctl;
+	unsigned char bcsta;
+	unsigned char bsintenb;
+	unsigned char bcval;
+	unsigned char pad2[4];
+	unsigned short nxtaddl3;
+	unsigned short nxtaddh3;
+	unsigned short nxtaddl5;
+	unsigned short nxtaddh5;
+	unsigned short nxtaddl6;
+	unsigned short nxtaddh6;
+	unsigned short nxtaddl7;
+	unsigned short nxtaddh7;
+	unsigned short nxtttcl3;
+	unsigned char nxtttch3;
+	unsigned char pad3;
+	unsigned short nxtttcl5;
+	unsigned char nxtttch5;
+	unsigned char pad5;
+	unsigned short nxtttcl6;
+	unsigned char nxtttch6;
+	unsigned char pad6;
+	unsigned short nxtttcl7;
+	unsigned char nxtttch7;
+	unsigned char pad7;
+};
+
+
+	
+
+struct mmcr {
+	unsigned short revid;
+	unsigned char cpucontrol;
+	unsigned char pad1[11];
+	struct memregs memregs;
+	struct dbctl dbctl;
+	struct romregs romregs;
+	struct hostbridge hostbridge;
+	struct sysarb sysarb;
+	struct sysmap sysmap;
+	struct gpctl gpctl;
+	struct pio pio;
+	struct swtmr swtmr;
+	struct gptimers gptimers;
+	struct watchdog watchdog;
+	struct uarts uarts;
+	struct ssi ssi;
+	struct pic pic;
+	struct reset reset;
+	struct dmacontrol dmacontrol;
+	unsigned char padend[0x23d];
+}
+
+
diff --git a/src/cpu/amd/sc520/mmcrtest.c b/src/cpu/amd/sc520/mmcrtest.c
new file mode 100644
index 0000000..9ba0715
--- /dev/null
+++ b/src/cpu/amd/sc520/mmcrtest.c
@@ -0,0 +1,231 @@
+#include <stdio.h>
+#include "mmcr.h"
+
+#define offsetof(s,m) (size_t)(unsigned long)&(((s *)0)->m)
+
+main(){
+printf("offset of revid is 0x%x\n\n", offsetof(struct mmcr, revid));
+printf("offset of cpucontrol is 0x%x\n\n", offsetof(struct mmcr, cpucontrol));
+printf("offset of hostbridge is 0x%x\n\n", offsetof(struct mmcr, hostbridge));
+printf("offset of sysarb is 0x%x\n\n", offsetof(struct mmcr, sysarb));
+printf("offset of sysmap is 0x%x\n\n", offsetof(struct mmcr, sysmap));
+printf("offset of gpctl is 0x%x\n\n", offsetof(struct mmcr, gpctl));
+printf("offset of pio is 0x%x\n\n", offsetof(struct mmcr, pio));
+printf("offset of swtmr is 0x%x\n\n", offsetof(struct mmcr, swtmr));
+printf("offset of gptimers is 0x%x\n\n", offsetof(struct mmcr, gptimers));
+printf("offset of watchdog is 0x%x\n\n", offsetof(struct mmcr, watchdog));
+printf("offset of uarts is 0x%x\n\n", offsetof(struct mmcr, uarts));
+printf("offset of ssi is 0x%x\n\n", offsetof(struct mmcr, ssi));
+printf("offset of pic is 0x%x\n\n", offsetof(struct mmcr, pic));
+printf("offset of reset is 0x%x\n\n", offsetof(struct mmcr, reset));
+printf("offset of dmacontrol is 0x%x\n\n", offsetof(struct mmcr, dmacontrol));
+
+printf("\n");
+printf("offset of memregs is 0x%x\n\n", offsetof(struct mmcr, memregs));
+printf("offset of drcctl is 0x%x\n", offsetof(struct mmcr, memregs.drcctl));
+printf("offset of drctmctl is 0x%x\n", offsetof(struct mmcr, memregs.drctmctl));
+printf("offset of drccfg is 0x%x\n", offsetof(struct mmcr, memregs.drccfg));
+printf("offset of bendaddr is 0x%x\n", offsetof(struct mmcr, memregs.drcbendadr));
+printf("offset of eccctl is 0x%x\n", offsetof(struct mmcr, memregs.eccctl));
+printf("offset of eccsta is 0x%x\n", offsetof(struct mmcr, memregs.eccsta));
+printf("offset of ckbpos is 0x%x\n", offsetof(struct mmcr, memregs.eccckbpos));
+printf("offset of cktest is 0x%x\n", offsetof(struct mmcr, memregs.ecccktest));
+printf("offset of sbadd is 0x%x\n", offsetof(struct mmcr, memregs.eccsbadd));
+printf("offset of mbadd is 0x%x\n", offsetof(struct mmcr, memregs.eccmbadd));
+
+printf("\n");
+printf("offset of dbctl is 0x%x\n\n", offsetof(struct mmcr, dbctl));
+printf("offset of dbctl is 0x%x\n", offsetof(struct mmcr, dbctl.dbctl));
+
+printf("\n");
+printf("offset of romregs is 0x%x\n\n", offsetof(struct mmcr, romregs));
+printf("offset of bootcs is 0x%x\n", offsetof(struct mmcr, romregs.bootcs));
+printf("offset of romcs1 is 0x%x\n", offsetof(struct mmcr, romregs.romcs1));
+printf("offset of romcs2 is 0x%x\n", offsetof(struct mmcr, romregs.romcs2));
+
+printf("\n");
+printf("offset of hostbridge is 0x%x\n\n", offsetof(struct mmcr, hostbridge));
+printf("offset of hbctl is 0x%x\n",  offsetof(struct mmcr, hostbridge.hbctl));
+printf("offset of hbtgtirqctl is 0x%x\n",  offsetof(struct mmcr, hostbridge.hbtgtirqctl));
+printf("offset of hbtgtirqsta is 0x%x\n",  offsetof(struct mmcr, hostbridge.hbtgtirqsta));
+printf("offset of hbmstirqctl is 0x%x\n",  offsetof(struct mmcr, hostbridge.hbmstirqctl));
+printf("offset of hbmstirqsta is 0x%x\n",  offsetof(struct mmcr, hostbridge.hbmstirqsta));
+printf("offset of mstintadd is 0x%x\n",  offsetof(struct mmcr, hostbridge.mstintadd));
+
+
+printf("\n");
+printf("offset of sysarb is 0x%x\n\n", offsetof(struct mmcr, sysarb));
+printf("offset of sysarbctl is 0x%x\n", offsetof(struct mmcr, sysarb.sysarbctl));
+printf("offset of pciarbsta is 0x%x\n", offsetof(struct mmcr, sysarb.pciarbsta));
+printf("offset of sysarbmenb is 0x%x\n", offsetof(struct mmcr, sysarb.sysarbmenb));
+printf("offset of arbprictl is 0x%x\n", offsetof(struct mmcr, sysarb.arbprictl));
+
+printf("\n");
+printf("offset of sysmap is 0x%x\n\n", offsetof(struct mmcr, sysmap));
+printf("offset of adddecctl is 0x%x\n", offsetof(struct mmcr, sysmap.adddecctl));
+printf("offset of wpvsta is 0x%x\n", offsetof(struct mmcr, sysmap.wpvsta));
+printf("offset of par is 0x%x\n", offsetof(struct mmcr, sysmap.par));
+
+printf("\n");
+printf("offset of gpctl is 0x%x\n\n", offsetof(struct mmcr, gpctl));
+printf("offset of gpecho is 0x%x\n", offsetof(struct mmcr, gpctl.gpecho));
+printf("offset of gpcsdw is 0x%x\n", offsetof(struct mmcr, gpctl.gpcsdw));
+printf("offset of gpcsqual is 0x%x\n", offsetof(struct mmcr, gpctl.gpcsqual));
+printf("offset of gpcsrt is 0x%x\n", offsetof(struct mmcr, gpctl.gpcsrt));
+printf("offset of gpcspw is 0x%x\n", offsetof(struct mmcr, gpctl.gpcspw));
+printf("offset of gpcsoff is 0x%x\n", offsetof(struct mmcr, gpctl.gpcsoff));
+printf("offset of gprdw is 0x%x\n", offsetof(struct mmcr, gpctl.gprdw));
+printf("offset of gprdoff is 0x%x\n", offsetof(struct mmcr, gpctl.gprdoff));
+printf("offset of gpwrw is 0x%x\n", offsetof(struct mmcr, gpctl.gpwrw));
+printf("offset of gpwroff is 0x%x\n", offsetof(struct mmcr, gpctl.gpwroff));
+printf("offset of gpalew is 0x%x\n", offsetof(struct mmcr, gpctl.gpalew));
+printf("offset of gpaleoff is 0x%x\n", offsetof(struct mmcr, gpctl.gpaleoff));
+
+printf("\n");
+printf("offset of pio is 0x%x\n\n", offsetof(struct mmcr, pio));
+
+printf("offset of piopfs15_0 is 0x%x\n",  offsetof(struct mmcr, pio.piopfs15_0));
+printf("offset of piopfs31_16 is 0x%x\n",  offsetof(struct mmcr, pio.piopfs31_16));
+printf("offset of cspfs is 0x%x\n",  offsetof(struct mmcr, pio.cspfs));
+printf("offset of clksel is 0x%x\n",  offsetof(struct mmcr, pio.clksel));
+printf("offset of dsctl is 0x%x\n",  offsetof(struct mmcr, pio.dsctl));
+printf("offset of piodir15_0 is 0x%x\n",  offsetof(struct mmcr, pio.piodir15_0));
+printf("offset of piodir31_16 is 0x%x\n",  offsetof(struct mmcr, pio.piodir31_16));
+printf("offset of piodata15_0 is 0x%x\n",  offsetof(struct mmcr, pio.piodata15_0));
+printf("offset of piodata31_16 is 0x%x\n",  offsetof(struct mmcr, pio.piodata31_16));
+printf("offset of pioset15_0 is 0x%x\n",  offsetof(struct mmcr, pio.pioset15_0));
+printf("offset of pioset31_16 is 0x%x\n",  offsetof(struct mmcr, pio.pioset31_16));
+printf("offset of pioclr15_0 is 0x%x\n",  offsetof(struct mmcr, pio.pioclr15_0));
+printf("offset of pioclr31_16 is 0x%x\n",  offsetof(struct mmcr, pio.pioclr31_16));
+
+printf("\noffset of swtmr is 0x%x\n", offsetof(struct mmcr, swtmr));
+printf("offset of swtmrmilli is 0x%x\n", offsetof(struct mmcr, swtmr.swtmrmilli));
+printf("offset of swtmrmicro is 0x%x\n", offsetof(struct mmcr, swtmr.swtmrmicro));
+printf("offset of swtmrcfg is 0x%x\n", offsetof(struct mmcr, swtmr.swtmrcfg));
+
+printf("\noffset of gptimers is 0x%x\n", offsetof(struct mmcr, gptimers));
+printf("offset of status  is 0x%x\n", offsetof(struct mmcr, gptimers.status));
+printf("offset of pad  is 0x%x\n", offsetof(struct mmcr, gptimers.pad));
+printf("offset of timer  is 0x%x\n", offsetof(struct mmcr, gptimers.timer));
+
+printf("offset of timers[0].ctl is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[0].ctl));
+printf("offset of timers[0].cnt is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[0].cnt));
+printf("offset of timers[0].maxcmpa is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[0].maxcmpa));
+printf("offset of timers[0].maxcmpb is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[0].maxcmpb));
+
+printf("offset of timers[1].ctl is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[1].ctl));
+printf("offset of timers[1].cnt is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[1].cnt));
+printf("offset of timers[1].maxcmpa is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[1].maxcmpa));
+printf("offset of timers[1].maxcmpb is 0x%x\n",  offsetof(struct mmcr, gptimers.timer[1].maxcmpb));
+printf("offset of timers[2].ctl is 0x%x\n",  offsetof(struct mmcr, gptimers.ctl2));
+printf("offset of timers[2].cnt is 0x%x\n",  offsetof(struct mmcr, gptimers.cnt2));
+printf("offset of timers[2].maxcmpa is 0x%x\n",  offsetof(struct mmcr, gptimers.maxcmpa2));
+
+printf("\noffset of watchdog is 0x%x\n", offsetof(struct mmcr, watchdog));
+printf("offset of ctl  is 0x%x\n",  offsetof(struct mmcr, watchdog.ctl));
+printf("offset of cntll  is 0x%x\n",  offsetof(struct mmcr, watchdog.cntll));
+printf("offset of cntlh  is 0x%x\n",  offsetof(struct mmcr, watchdog.cntlh));
+
+printf("\noffset of uarts is 0x%x\n", offsetof(struct mmcr, uarts));
+printf("offset of uart 1 ctl is 0x%x\n", offsetof(struct mmcr, uarts.uart[0].ctl));
+printf("offset of uart 1 sta is 0x%x\n", offsetof(struct mmcr, uarts.uart[0].sta));
+printf("offset of uart 1 fcrshad is 0x%x\n", offsetof(struct mmcr, uarts.uart[0].fcrshad));
+printf("offset of uart 2 ctl is 0x%x\n", offsetof(struct mmcr, uarts.uart[1].ctl));
+printf("offset of uart 2 sta is 0x%x\n", offsetof(struct mmcr, uarts.uart[1].sta));
+printf("offset of uart 2 fcrshad is 0x%x\n", offsetof(struct mmcr, uarts.uart[1].fcrshad));
+
+printf("\noffset of ssi is 0x%x\n", offsetof(struct mmcr, ssi));
+printf("offset of ssi ctl is 0x%x\n", offsetof(struct mmcr, ssi.ctl));
+printf("offset of ssi xmit is 0x%x\n", offsetof(struct mmcr, ssi.xmit));
+printf("offset of ssi cmd is 0x%x\n", offsetof(struct mmcr, ssi.cmd));
+printf("offset of ssi sta is 0x%x\n", offsetof(struct mmcr, ssi.sta));
+printf("offset of ssi rcv is 0x%x\n", offsetof(struct mmcr, ssi.rcv));
+
+printf("\noffset of pic is 0x%x\n", offsetof(struct mmcr, pic));
+printf("offset of pcicr is 0x%x\n", offsetof(struct mmcr, pic.pcicr));
+printf("offset of mpicmode is 0x%x\n", offsetof(struct mmcr, pic.mpicmode));
+printf("offset of sl1picmode is 0x%x\n", offsetof(struct mmcr, pic.sl1picmode));
+printf("offset of sl2picmode is 0x%x\n", offsetof(struct mmcr, pic.sl2picmode));
+printf("offset of swint16_1 is 0x%x\n", offsetof(struct mmcr, pic.swint16_1));
+printf("offset of swint22_17 is 0x%x\n", offsetof(struct mmcr, pic.swint22_17));
+printf("offset of intpinpol is 0x%x\n", offsetof(struct mmcr, pic.intpinpol));
+printf("offset of pichostmap is 0x%x\n", offsetof(struct mmcr, pic.pichostmap));
+printf("offset of eccmap is 0x%x\n", offsetof(struct mmcr, pic.eccmap));
+printf("offset of gptmr0map is 0x%x\n", offsetof(struct mmcr, pic.gptmr0map));
+printf("offset of gptmr1map is 0x%x\n", offsetof(struct mmcr, pic.gptmr1map));
+printf("offset of gptmr2map is 0x%x\n", offsetof(struct mmcr, pic.gptmr2map));
+printf("offset of pit0map is 0x%x\n", offsetof(struct mmcr, pic.pit0map));
+printf("offset of pit1map is 0x%x\n", offsetof(struct mmcr, pic.pit1map));
+printf("offset of pit2map is 0x%x\n", offsetof(struct mmcr, pic.pit2map));
+printf("offset of uart1map is 0x%x\n", offsetof(struct mmcr, pic.uart1map));
+printf("offset of uart2map is 0x%x\n", offsetof(struct mmcr, pic.uart2map));
+printf("offset of pciintamap is 0x%x\n", offsetof(struct mmcr, pic.pciintamap));
+printf("offset of pciintbmap is 0x%x\n", offsetof(struct mmcr, pic.pciintbmap));
+printf("offset of pciintcmap is 0x%x\n", offsetof(struct mmcr, pic.pciintcmap));
+printf("offset of pciintdmap is 0x%x\n", offsetof(struct mmcr, pic.pciintdmap));
+printf("offset of dmabcintmap is 0x%x\n", offsetof(struct mmcr, pic.dmabcintmap));
+printf("offset of ssimap is 0x%x\n", offsetof(struct mmcr, pic.ssimap));
+printf("offset of wdtmap is 0x%x\n", offsetof(struct mmcr, pic.wdtmap));
+printf("offset of rtcmap is 0x%x\n", offsetof(struct mmcr, pic.rtcmap));
+printf("offset of wpvmap is 0x%x\n", offsetof(struct mmcr, pic.wpvmap));
+printf("offset of icemap is 0x%x\n", offsetof(struct mmcr, pic.icemap));
+printf("offset of ferrmap is 0x%x\n", offsetof(struct mmcr, pic.ferrmap));
+printf("offset of gp0imap is 0x%x\n", offsetof(struct mmcr, pic.gp0imap));
+printf("offset of gp1imap is 0x%x\n", offsetof(struct mmcr, pic.gp1imap));
+printf("offset of gp2imap is 0x%x\n", offsetof(struct mmcr, pic.gp2imap));
+printf("offset of gp3imap is 0x%x\n", offsetof(struct mmcr, pic.gp3imap));
+printf("offset of gp4imap is 0x%x\n", offsetof(struct mmcr, pic.gp4imap));
+printf("offset of gp5imap is 0x%x\n", offsetof(struct mmcr, pic.gp5imap));
+printf("offset of gp6imap is 0x%x\n", offsetof(struct mmcr, pic.gp6imap));
+printf("offset of gp7imap is 0x%x\n", offsetof(struct mmcr, pic.gp7imap));
+printf("offset of gp8imap is 0x%x\n", offsetof(struct mmcr, pic.gp8imap));
+printf("offset of gp9imap is 0x%x\n", offsetof(struct mmcr, pic.gp9imap));
+printf("offset of gp10imap is 0x%x\n", offsetof(struct mmcr, pic.gp10imap));
+
+printf("\noffset of reset is 0x%x\n\n", offsetof(struct mmcr, reset));
+printf("offset of sysinfo is 0x%x\n", offsetof(struct mmcr, reset.sysinfo));
+printf("offset of rescfg is 0x%x\n", offsetof(struct mmcr, reset.rescfg));
+printf("offset of ressta is 0x%x\n", offsetof(struct mmcr, reset.ressta));
+
+
+printf("\noffset of dmacontrol is 0x%x\n\n", offsetof(struct mmcr, dmacontrol));
+printf("offset of ctl is 0x%x\n", offsetof(struct mmcr, dmacontrol.ctl));
+printf("offset of mmio is 0x%x\n", offsetof(struct mmcr, dmacontrol.mmio));
+printf("offset of extchanmapa is 0x%x\n", offsetof(struct mmcr, dmacontrol.extchanmapa));
+printf("offset of extchanmapb is 0x%x\n", offsetof(struct mmcr, dmacontrol.extchanmapb));
+printf("offset of extpg0 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg0));
+printf("offset of extpg1 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg1));
+printf("offset of extpg2 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg2));
+printf("offset of extpg3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg3));
+printf("offset of extpg5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg5));
+printf("offset of extpg6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg6));
+printf("offset of extpg7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.extpg7));
+printf("offset of exttc3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.exttc3));
+printf("offset of exttc5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.exttc5));
+printf("offset of exttc6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.exttc6));
+printf("offset of exttc7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.exttc7));
+printf("offset of bcctl is 0x%x\n", offsetof(struct mmcr, dmacontrol.bcctl));
+printf("offset of bcsta is 0x%x\n", offsetof(struct mmcr, dmacontrol.bcsta));
+printf("offset of bsintenb is 0x%x\n", offsetof(struct mmcr, dmacontrol.bsintenb));
+printf("offset of bcval is 0x%x\n", offsetof(struct mmcr, dmacontrol.bcval));
+printf("offset of nxtaddl3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddl3));
+printf("offset of nxtaddh3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddh3));
+printf("offset of nxtaddl5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddl5));
+printf("offset of nxtaddh5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddh5));
+printf("offset of nxtaddl6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddl6));
+printf("offset of nxtaddh6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddh6));
+printf("offset of nxtaddl7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddl7));
+printf("offset of nxtaddh7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtaddh7));
+printf("offset of nxtttcl3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttcl3));
+printf("offset of nxtttch3 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttch3));
+printf("offset of nxtttcl5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttcl5));
+printf("offset of nxtttch5 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttch5));
+printf("offset of nxtttcl6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttcl6));
+printf("offset of nxtttch6 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttch6));
+printf("offset of nxtttcl7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttcl7));
+printf("offset of nxtttch7 is 0x%x\n", offsetof(struct mmcr, dmacontrol.nxtttch7));
+
+
+
+	printf("size is 0x%x\n", sizeof(struct mmcr));
+}
diff --git a/src/cpu/amd/sc520/mmcrval.c b/src/cpu/amd/sc520/mmcrval.c
new file mode 100644
index 0000000..7b8f285
--- /dev/null
+++ b/src/cpu/amd/sc520/mmcrval.c
@@ -0,0 +1,219 @@
+#include <stdio.h>
+#include "mmcr.h"
+
+#define offsetof(s,m) (size_t)(unsigned long)&(((s *)0)->m)
+#define val(s,m) (size_t)(unsigned long)&(((s))->m)
+
+main(){
+struct mmcr *mmcr = (struct mmcr *) 0xfffef000;
+printf("val of revid is 0x%x\n\n", val(mmcr, revid));
+printf("val of cpucontrol is 0x%x\n\n", val(mmcr, cpucontrol));
+
+/*
+printf("val of sysarb is 0x%x\n\n", val(mmcr, sysarb));
+printf("val of sysmap is 0x%x\n\n", val(mmcr, sysmap));
+printf("val of gpctl is 0x%x\n\n", val(mmcr, gpctl));
+printf("val of pio is 0x%x\n\n", val(mmcr, pio));
+printf("val of swtmr is 0x%x\n\n", val(mmcr, swtmr));
+printf("val of gptimers is 0x%x\n\n", val(mmcr, gptimers));
+printf("val of watchdog is 0x%x\n\n", val(mmcr, watchdog));
+printf("val of uarts is 0x%x\n\n", val(mmcr, uarts));
+printf("val of ssi is 0x%x\n\n", val(mmcr, ssi));
+printf("val of pic is 0x%x\n\n", val(mmcr, pic));
+printf("val of reset is 0x%x\n\n", val(mmcr, reset));
+printf("val of dmacontrol is 0x%x\n\n", val(mmcr, dmacontrol));
+ */
+
+printf("\n");
+printf("val of drcctl is 0x%x\n", val(mmcr, memregs.drcctl));
+printf("val of drctmctl is 0x%x\n", val(mmcr, memregs.drctmctl));
+printf("val of drccfg is 0x%x\n", val(mmcr, memregs.drccfg));
+printf("val of bendaddr is 0x%x\n", val(mmcr, memregs.drcbendadr));
+printf("val of eccctl is 0x%x\n", val(mmcr, memregs.eccctl));
+printf("val of eccsta is 0x%x\n", val(mmcr, memregs.eccsta));
+printf("val of ckbpos is 0x%x\n", val(mmcr, memregs.eccckbpos));
+printf("val of cktest is 0x%x\n", val(mmcr, memregs.ecccktest));
+printf("val of sbadd is 0x%x\n", val(mmcr, memregs.eccsbadd));
+printf("val of mbadd is 0x%x\n", val(mmcr, memregs.eccmbadd));
+
+printf("\n");
+printf("val of dbctl is 0x%x\n", val(mmcr, dbctl.dbctl));
+
+printf("\n");
+printf("val of bootcs is 0x%x\n", val(mmcr, romregs.bootcs));
+printf("val of romcs1 is 0x%x\n", val(mmcr, romregs.romcs1));
+printf("val of romcs2 is 0x%x\n", val(mmcr, romregs.romcs2));
+
+printf("\n");
+printf("val of hbctl is 0x%x\n",  val(mmcr, hostbridge.hbctl));
+printf("val of hbtgtirqctl is 0x%x\n",  val(mmcr, hostbridge.hbtgtirqctl));
+printf("val of hbtgtirqsta is 0x%x\n",  val(mmcr, hostbridge.hbtgtirqsta));
+printf("val of hbmstirqctl is 0x%x\n",  val(mmcr, hostbridge.hbmstirqctl));
+printf("val of hbmstirqsta is 0x%x\n",  val(mmcr, hostbridge.hbmstirqsta));
+printf("val of mstintadd is 0x%x\n",  val(mmcr, hostbridge.mstintadd));
+
+
+printf("\n");
+printf("val of sysarbctl is 0x%x\n", val(mmcr, sysarb.sysarbctl));
+printf("val of pciarbsta is 0x%x\n", val(mmcr, sysarb.pciarbsta));
+printf("val of sysarbmenb is 0x%x\n", val(mmcr, sysarb.sysarbmenb));
+printf("val of arbprictl is 0x%x\n", val(mmcr, sysarb.arbprictl));
+
+printf("\n");
+printf("val of adddecctl is 0x%x\n", val(mmcr, sysmap.adddecctl));
+printf("val of wpvsta is 0x%x\n", val(mmcr, sysmap.wpvsta));
+printf("val of par is 0x%x\n", val(mmcr, sysmap.par));
+
+printf("\n");
+printf("val of gpecho is 0x%x\n", val(mmcr, gpctl.gpecho));
+printf("val of gpcsdw is 0x%x\n", val(mmcr, gpctl.gpcsdw));
+printf("val of gpcsqual is 0x%x\n", val(mmcr, gpctl.gpcsqual));
+printf("val of gpcsrt is 0x%x\n", val(mmcr, gpctl.gpcsrt));
+printf("val of gpcspw is 0x%x\n", val(mmcr, gpctl.gpcspw));
+printf("val of gpcsoff is 0x%x\n", val(mmcr, gpctl.gpcsoff));
+printf("val of gprdw is 0x%x\n", val(mmcr, gpctl.gprdw));
+printf("val of gprdoff is 0x%x\n", val(mmcr, gpctl.gprdoff));
+printf("val of gpwrw is 0x%x\n", val(mmcr, gpctl.gpwrw));
+printf("val of gpwroff is 0x%x\n", val(mmcr, gpctl.gpwroff));
+printf("val of gpalew is 0x%x\n", val(mmcr, gpctl.gpalew));
+printf("val of gpaleoff is 0x%x\n", val(mmcr, gpctl.gpaleoff));
+
+printf("\n");
+
+printf("val of piopfs15_0 is 0x%x\n",  val(mmcr, pio.piopfs15_0));
+printf("val of piopfs31_16 is 0x%x\n",  val(mmcr, pio.piopfs31_16));
+printf("val of cspfs is 0x%x\n",  val(mmcr, pio.cspfs));
+printf("val of clksel is 0x%x\n",  val(mmcr, pio.clksel));
+printf("val of dsctl is 0x%x\n",  val(mmcr, pio.dsctl));
+printf("val of piodir15_0 is 0x%x\n",  val(mmcr, pio.piodir15_0));
+printf("val of piodir31_16 is 0x%x\n",  val(mmcr, pio.piodir31_16));
+printf("val of piodata15_0 is 0x%x\n",  val(mmcr, pio.piodata15_0));
+printf("val of piodata31_16 is 0x%x\n",  val(mmcr, pio.piodata31_16));
+printf("val of pioset15_0 is 0x%x\n",  val(mmcr, pio.pioset15_0));
+printf("val of pioset31_16 is 0x%x\n",  val(mmcr, pio.pioset31_16));
+printf("val of pioclr15_0 is 0x%x\n",  val(mmcr, pio.pioclr15_0));
+printf("val of pioclr31_16 is 0x%x\n",  val(mmcr, pio.pioclr31_16));
+
+printf("val of swtmrmilli is 0x%x\n", val(mmcr, swtmr.swtmrmilli));
+printf("val of swtmrmicro is 0x%x\n", val(mmcr, swtmr.swtmrmicro));
+printf("val of swtmrcfg is 0x%x\n", val(mmcr, swtmr.swtmrcfg));
+
+printf("val of status  is 0x%x\n", val(mmcr, gptimers.status));
+printf("val of pad  is 0x%x\n", val(mmcr, gptimers.pad));
+printf("val of timer  is 0x%x\n", val(mmcr, gptimers.timer));
+
+printf("val of timers[0].ctl is 0x%x\n",  val(mmcr, gptimers.timer[0].ctl));
+printf("val of timers[0].cnt is 0x%x\n",  val(mmcr, gptimers.timer[0].cnt));
+printf("val of timers[0].maxcmpa is 0x%x\n",  val(mmcr, gptimers.timer[0].maxcmpa));
+printf("val of timers[0].maxcmpb is 0x%x\n",  val(mmcr, gptimers.timer[0].maxcmpb));
+
+printf("val of timers[1].ctl is 0x%x\n",  val(mmcr, gptimers.timer[1].ctl));
+printf("val of timers[1].cnt is 0x%x\n",  val(mmcr, gptimers.timer[1].cnt));
+printf("val of timers[1].maxcmpa is 0x%x\n",  val(mmcr, gptimers.timer[1].maxcmpa));
+printf("val of timers[1].maxcmpb is 0x%x\n",  val(mmcr, gptimers.timer[1].maxcmpb));
+printf("val of timers[2].ctl is 0x%x\n",  val(mmcr, gptimers.ctl2));
+printf("val of timers[2].cnt is 0x%x\n",  val(mmcr, gptimers.cnt2));
+printf("val of timers[2].maxcmpa is 0x%x\n",  val(mmcr, gptimers.maxcmpa2));
+
+printf("val of ctl  is 0x%x\n",  val(mmcr, watchdog.ctl));
+printf("val of cntll  is 0x%x\n",  val(mmcr, watchdog.cntll));
+printf("val of cntlh  is 0x%x\n",  val(mmcr, watchdog.cntlh));
+
+printf("val of uart 1 ctl is 0x%x\n", val(mmcr, uarts.uart[0].ctl));
+printf("val of uart 1 sta is 0x%x\n", val(mmcr, uarts.uart[0].sta));
+printf("val of uart 1 fcrshad is 0x%x\n", val(mmcr, uarts.uart[0].fcrshad));
+printf("val of uart 2 ctl is 0x%x\n", val(mmcr, uarts.uart[1].ctl));
+printf("val of uart 2 sta is 0x%x\n", val(mmcr, uarts.uart[1].sta));
+printf("val of uart 2 fcrshad is 0x%x\n", val(mmcr, uarts.uart[1].fcrshad));
+
+printf("val of ssi ctl is 0x%x\n", val(mmcr, ssi.ctl));
+printf("val of ssi xmit is 0x%x\n", val(mmcr, ssi.xmit));
+printf("val of ssi cmd is 0x%x\n", val(mmcr, ssi.cmd));
+printf("val of ssi sta is 0x%x\n", val(mmcr, ssi.sta));
+printf("val of ssi rcv is 0x%x\n", val(mmcr, ssi.rcv));
+
+printf("val of pcicr is 0x%x\n", val(mmcr, pic.pcicr));
+printf("val of mpicmode is 0x%x\n", val(mmcr, pic.mpicmode));
+printf("val of sl1picmode is 0x%x\n", val(mmcr, pic.sl1picmode));
+printf("val of sl2picmode is 0x%x\n", val(mmcr, pic.sl2picmode));
+printf("val of swint16_1 is 0x%x\n", val(mmcr, pic.swint16_1));
+printf("val of swint22_17 is 0x%x\n", val(mmcr, pic.swint22_17));
+printf("val of intpinpol is 0x%x\n", val(mmcr, pic.intpinpol));
+printf("val of pichostmap is 0x%x\n", val(mmcr, pic.pichostmap));
+printf("val of eccmap is 0x%x\n", val(mmcr, pic.eccmap));
+printf("val of gptmr0map is 0x%x\n", val(mmcr, pic.gptmr0map));
+printf("val of gptmr1map is 0x%x\n", val(mmcr, pic.gptmr1map));
+printf("val of gptmr2map is 0x%x\n", val(mmcr, pic.gptmr2map));
+printf("val of pit0map is 0x%x\n", val(mmcr, pic.pit0map));
+printf("val of pit1map is 0x%x\n", val(mmcr, pic.pit1map));
+printf("val of pit2map is 0x%x\n", val(mmcr, pic.pit2map));
+printf("val of uart1map is 0x%x\n", val(mmcr, pic.uart1map));
+printf("val of uart2map is 0x%x\n", val(mmcr, pic.uart2map));
+printf("val of pciintamap is 0x%x\n", val(mmcr, pic.pciintamap));
+printf("val of pciintbmap is 0x%x\n", val(mmcr, pic.pciintbmap));
+printf("val of pciintcmap is 0x%x\n", val(mmcr, pic.pciintcmap));
+printf("val of pciintdmap is 0x%x\n", val(mmcr, pic.pciintdmap));
+printf("val of dmabcintmap is 0x%x\n", val(mmcr, pic.dmabcintmap));
+printf("val of ssimap is 0x%x\n", val(mmcr, pic.ssimap));
+printf("val of wdtmap is 0x%x\n", val(mmcr, pic.wdtmap));
+printf("val of rtcmap is 0x%x\n", val(mmcr, pic.rtcmap));
+printf("val of wpvmap is 0x%x\n", val(mmcr, pic.wpvmap));
+printf("val of icemap is 0x%x\n", val(mmcr, pic.icemap));
+printf("val of ferrmap is 0x%x\n", val(mmcr, pic.ferrmap));
+printf("val of gp0imap is 0x%x\n", val(mmcr, pic.gp0imap));
+printf("val of gp1imap is 0x%x\n", val(mmcr, pic.gp1imap));
+printf("val of gp2imap is 0x%x\n", val(mmcr, pic.gp2imap));
+printf("val of gp3imap is 0x%x\n", val(mmcr, pic.gp3imap));
+printf("val of gp4imap is 0x%x\n", val(mmcr, pic.gp4imap));
+printf("val of gp5imap is 0x%x\n", val(mmcr, pic.gp5imap));
+printf("val of gp6imap is 0x%x\n", val(mmcr, pic.gp6imap));
+printf("val of gp7imap is 0x%x\n", val(mmcr, pic.gp7imap));
+printf("val of gp8imap is 0x%x\n", val(mmcr, pic.gp8imap));
+printf("val of gp9imap is 0x%x\n", val(mmcr, pic.gp9imap));
+printf("val of gp10imap is 0x%x\n", val(mmcr, pic.gp10imap));
+
+printf("val of sysinfo is 0x%x\n", val(mmcr, reset.sysinfo));
+printf("val of rescfg is 0x%x\n", val(mmcr, reset.rescfg));
+printf("val of ressta is 0x%x\n", val(mmcr, reset.ressta));
+
+
+printf("val of ctl is 0x%x\n", val(mmcr, dmacontrol.ctl));
+printf("val of mmio is 0x%x\n", val(mmcr, dmacontrol.mmio));
+printf("val of extchanmapa is 0x%x\n", val(mmcr, dmacontrol.extchanmapa));
+printf("val of extchanmapb is 0x%x\n", val(mmcr, dmacontrol.extchanmapb));
+printf("val of extpg0 is 0x%x\n", val(mmcr, dmacontrol.extpg0));
+printf("val of extpg1 is 0x%x\n", val(mmcr, dmacontrol.extpg1));
+printf("val of extpg2 is 0x%x\n", val(mmcr, dmacontrol.extpg2));
+printf("val of extpg3 is 0x%x\n", val(mmcr, dmacontrol.extpg3));
+printf("val of extpg5 is 0x%x\n", val(mmcr, dmacontrol.extpg5));
+printf("val of extpg6 is 0x%x\n", val(mmcr, dmacontrol.extpg6));
+printf("val of extpg7 is 0x%x\n", val(mmcr, dmacontrol.extpg7));
+printf("val of exttc3 is 0x%x\n", val(mmcr, dmacontrol.exttc3));
+printf("val of exttc5 is 0x%x\n", val(mmcr, dmacontrol.exttc5));
+printf("val of exttc6 is 0x%x\n", val(mmcr, dmacontrol.exttc6));
+printf("val of exttc7 is 0x%x\n", val(mmcr, dmacontrol.exttc7));
+printf("val of bcctl is 0x%x\n", val(mmcr, dmacontrol.bcctl));
+printf("val of bcsta is 0x%x\n", val(mmcr, dmacontrol.bcsta));
+printf("val of bsintenb is 0x%x\n", val(mmcr, dmacontrol.bsintenb));
+printf("val of bcval is 0x%x\n", val(mmcr, dmacontrol.bcval));
+printf("val of nxtaddl3 is 0x%x\n", val(mmcr, dmacontrol.nxtaddl3));
+printf("val of nxtaddh3 is 0x%x\n", val(mmcr, dmacontrol.nxtaddh3));
+printf("val of nxtaddl5 is 0x%x\n", val(mmcr, dmacontrol.nxtaddl5));
+printf("val of nxtaddh5 is 0x%x\n", val(mmcr, dmacontrol.nxtaddh5));
+printf("val of nxtaddl6 is 0x%x\n", val(mmcr, dmacontrol.nxtaddl6));
+printf("val of nxtaddh6 is 0x%x\n", val(mmcr, dmacontrol.nxtaddh6));
+printf("val of nxtaddl7 is 0x%x\n", val(mmcr, dmacontrol.nxtaddl7));
+printf("val of nxtaddh7 is 0x%x\n", val(mmcr, dmacontrol.nxtaddh7));
+printf("val of nxtttcl3 is 0x%x\n", val(mmcr, dmacontrol.nxtttcl3));
+printf("val of nxtttch3 is 0x%x\n", val(mmcr, dmacontrol.nxtttch3));
+printf("val of nxtttcl5 is 0x%x\n", val(mmcr, dmacontrol.nxtttcl5));
+printf("val of nxtttch5 is 0x%x\n", val(mmcr, dmacontrol.nxtttch5));
+printf("val of nxtttcl6 is 0x%x\n", val(mmcr, dmacontrol.nxtttcl6));
+printf("val of nxtttch6 is 0x%x\n", val(mmcr, dmacontrol.nxtttch6));
+printf("val of nxtttcl7 is 0x%x\n", val(mmcr, dmacontrol.nxtttcl7));
+printf("val of nxtttch7 is 0x%x\n", val(mmcr, dmacontrol.nxtttch7));
+
+
+
+	printf("size is 0x%x\n", sizeof(struct mmcr));
+}
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index 273e0a4..b35a267 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -162,13 +162,50 @@ setupsc520(void){
    * with these short pointers, it now reliably comes up after power cycle
    * with printk. Ah yi yi.
    */
+  /* turn off the write buffer*/
+  /* per the note above, make this a short? Let's try it. 
+   */
+  sp = (unsigned short *)0xfffef040;
+  *sp = 0;
+
+  /* as per the book: */
+  /* PAR register setup */
+	/* set up the PAR registers as they are on the MSM586SEG */
+	par = (unsigned long *) 0xfffef088;
 
+	/* NOTE: move this to mainboard.c ASAP */
+#if 1
 
-	/* turn off the write buffer*/
-        /* per the note above, make this a short? Let's try it. 
-	 */
-  sp = (unsigned short *)0xfffef040;
-	*sp = 0;
+
+	*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
+	*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
+	*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
+	*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
+	*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
+	*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
+	*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
+	*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
+	*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
+	*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
+	*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
+	*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
+	*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
+	*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
+	*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
+#else
+	par += 15;
+#endif
+	*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
+
+
+	/* CPCSF register */
+
+	sp =  (unsigned short *)0xfffefc24;
+	*sp = 0xfe;
+
+	/* ADDDECTL */
+	sp =  (unsigned short *)0xfffefc80;
+	*sp = 0x10;
 
 	/* byte writes in AMD assembly */
 	/* we do short anyway, since u-boot does ... */
@@ -223,16 +260,18 @@ setupsc520(void){
 #endif
 
 /*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
+/* enable interrupts here? Why not? */
 	cp = (unsigned char *)0xfffefcc0;
-	*cp = 4;					/* uart 1 clock source */
+	*cp = 4 | 3;					/* uart 1 clock source */
 	cp = (unsigned char *)0xfffefcc4;
 	*cp = 4;					/* uart 2 clock source */
+
 #if 0
 /*; set the interrupt mapping registers.*/
 	cp = (unsigned char *)0x0fffefd20;
 	*cp = 0x01;
 	
-x	cp = (unsigned char *)0x0fffefd28;
+	cp = (unsigned char *)0x0fffefd28;
 	*cp = 0x0c;
 	
 	cp = (unsigned char *)0x0fffefd29;
@@ -246,7 +285,7 @@ x	cp = (unsigned char *)0x0fffefd28;
 	
 	cp = (unsigned char *)0x0fffefd51;
 	*cp = 0x02;
-	
+#endif	
 /*; "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
 	outl(0xcf8, 0x08000683c);
 	outl(0xcfc, 0xc); /* set the interrupt line */
@@ -257,32 +296,7 @@ x	cp = (unsigned char *)0x0fffefd28;
 	outl(0x0cf8,0x080000004);	/*index the status command register on device 0*/
 	outl(0xcfc, 0x2);			/*set the memory access enable bit*/
 	OUTC(0x0fffef072, 1);		/* enable req bits in SYSARBMENB */
-#endif
-	/* set up the PAR registers as they are on the MSM586SEG */
-	par = (unsigned long *) 0xfffef088;
 
-#if 0
-
-
-	*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
-	*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
-	*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
-	*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
-	*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
-	*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
-	*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
-	*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
-	*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
-	*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
-	*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
-	*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
-	*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
-	*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
-	*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
-#else
-	par += 15;
-#endif
-	*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
 
 
 }