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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-06 15:19:56 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-09 21:54:53 +0200 |
| commit | 6b583a454c24c0c8fb41da9eaef52a830e83b3e4 (patch) | |
| tree | 8c010ad5fdd9c98e20a73f5fca3f585888f97a66 | |
| parent | 8395e90bc0a737f09ef5b5e2c94e37c66748b505 (diff) | |
| download | coreboot-staging-6b583a454c24c0c8fb41da9eaef52a830e83b3e4.zip coreboot-staging-6b583a454c24c0c8fb41da9eaef52a830e83b3e4.tar.gz | |
vendorcode/amd/agesa: Do not hardcode ROM base address
The ROM address range is set up in the LPC PCI device, register 0x6c.
Coreboot already sets that up correctly in the bootblock, however
AGESA overrides that to 0xffffff00, which will always map the ROM from
0xff000000. This may conflict with other devices which are assigned
address space in that range.
If a device is assigned a range between 0xff000000 and the real ROM
base, accesses to that device will be diverted to the system ROM,
regardless of how other BARs are set up. Since we already need to set
up the ROM address range in the bootblock, before calling AGESA, just
remove the override from AGESA.
Note that not all AGESA versions override this mapping.
Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5467
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
3 files changed, 0 insertions, 6 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c index 8e9bee7..e4aca36 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c @@ -98,8 +98,6 @@ FchInitResetLpc ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetLpcPciTable[0]), sizeof (FchInitResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); if ( LocalCfgPtr->LegacyFree ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c index adbfab3..36259d3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -99,8 +99,6 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); // diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c index 1a02218..ab71bb9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c @@ -125,8 +125,6 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), sizeof (FchInitYangtzeResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); if ( LocalCfgPtr->Spi.LpcClk0 ) { |
