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author | Matt DeVillier <matt.devillier@gmail.com> | 2015-05-14 21:58:33 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2015-05-16 08:14:21 +0200 |
commit | 5b667df135dc4736f87d0650cc64b2c052bc9b73 (patch) | |
tree | f2e6fda525a0271aaafd98344d73cec63634250f | |
parent | 7780c4f213df157c51ff45f62d644cd90080ae47 (diff) | |
download | coreboot-staging-5b667df135dc4736f87d0650cc64b2c052bc9b73.zip coreboot-staging-5b667df135dc4736f87d0650cc64b2c052bc9b73.tar.gz |
util/inteltool: add Broadwell-U support
add handling of PCI IDs for Broadwell-U/Wildcat Point LP,
using same functions as Haswell-U/Lynx Point LP
Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r-- | util/inteltool/gpio.c | 2 | ||||
-rw-r--r-- | util/inteltool/inteltool.c | 2 | ||||
-rw-r--r-- | util/inteltool/inteltool.h | 2 | ||||
-rw-r--r-- | util/inteltool/memory.c | 1 | ||||
-rw-r--r-- | util/inteltool/pcie.c | 3 | ||||
-rw-r--r-- | util/inteltool/powermgt.c | 1 | ||||
-rw-r--r-- | util/inteltool/rootcmplx.c | 1 | ||||
-rw-r--r-- | util/inteltool/spi.c | 1 |
8 files changed, 13 insertions, 0 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index aaacd57..7084c44 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -856,6 +856,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = lynxpoint_lp_gpio_registers; size = ARRAY_SIZE(lynxpoint_lp_gpio_registers); @@ -1050,6 +1051,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: for (i = 0; i < 95; i++) { io_register_t tmp_gpio; char gpio_name[32]; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 1a6bda2..a3712c5 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -84,6 +84,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -163,6 +164,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, "Wildcat Point Low Power SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3014b3e..6c1977e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -112,6 +112,7 @@ #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -173,6 +174,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 3aa3e4f..950d4a3 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -216,6 +216,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 6fa94e9..ecfa2f1 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -216,6 +216,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -321,6 +322,7 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: dmi_registers = haswell_ult_dmi_registers; size = ARRAY_SIZE(haswell_ult_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -418,6 +420,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 2cefabe..865cfba 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -705,6 +705,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index f57e773..c099737 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -98,6 +98,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index e4a77b6..8873fc0 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -170,6 +170,7 @@ int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; size = ARRAY_SIZE(spi_bar_registers); spi_register = spi_bar_registers; |