diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2006-10-27 11:38:22 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2006-10-27 11:38:22 +0000 |
commit | 586470c646ac1b8753858b013b268f049a28b818 (patch) | |
tree | e701bc449d20bf89c784194f34ffd3c4a11bc8eb | |
parent | e0e1d425274d5e2c90e19eec6ef125d1fffd73a1 (diff) | |
download | coreboot-staging-586470c646ac1b8753858b013b268f049a28b818.zip coreboot-staging-586470c646ac1b8753858b013b268f049a28b818.tar.gz |
Rename E7520 to e7520, and E7525 to e7525 in the code. The next commit
will then rename the E7520 and E7525 directories respectively.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
34 files changed, 52 insertions, 52 deletions
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb index 50ab93c..0640f38 100644 --- a/src/mainboard/dell/s1850/Config.lb +++ b/src/mainboard/dell/s1850/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c index 4061813..7840613 100644 --- a/src/mainboard/dell/s1850/auto.c +++ b/src/mainboard/dell/s1850/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "s2850_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/dell/s1850/failover.c b/src/mainboard/dell/s1850/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/dell/s1850/failover.c +++ b/src/mainboard/dell/s1850/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb index c355640..69795b0 100644 --- a/src/mainboard/intel/jarrell/Config.lb +++ b/src/mainboard/intel/jarrell/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 +chip northbridge/intel/e7520 device pci_domain 0 on device pci 00.0 on end device pci 00.1 on end diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c index f102746..d5e68e2 100644 --- a/src/mainboard/intel/jarrell/auto.c +++ b/src/mainboard/intel/jarrell/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "power_reset_check.c" #include "jarrell_fixups.c" #include "superio/nsc/pc87427/pc87427_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #define SIO_GPIO_BASE 0x680 @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" #include "debug.c" diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/intel/jarrell/failover.c +++ b/src/mainboard/intel/jarrell/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 8d4ada5..a246f16 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7525 # mch +chip northbridge/intel/e7525 # mch device pci_domain 0 on chip southbridge/intel/esb6300 # esb6300 register "pirq_a_d" = "0x0b0a0a05" diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c index f148a8c..9c5fce5 100644 --- a/src/mainboard/supermicro/x6dai_g/auto.c +++ b/src/mainboard/supermicro/x6dai_g/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7525/raminit.h" +#include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -19,7 +19,7 @@ #include "watchdog.c" #include "reset.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7525/memory_initialized.c" +#include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" @@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7525/raminit.c" +#include "northbridge/intel/e7525/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dai_g/failover.c b/src/mainboard/supermicro/x6dai_g/failover.c index 1a4a88e..29b7eed 100644 --- a/src/mainboard/supermicro/x6dai_g/failover.c +++ b/src/mainboard/supermicro/x6dai_g/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7525/memory_initialized.c" +#include "northbridge/intel/e7525/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index 672da82..60be506 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # MCH +chip northbridge/intel/e7520 # MCH chip drivers/generic/debug # DEBUGGING device pnp 00.0 on end device pnp 00.1 off end diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c index be5affc..fd78ab4 100644 --- a/src/mainboard/supermicro/x6dhe_g/auto.c +++ b/src/mainboard/supermicro/x6dhe_g/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g/failover.c b/src/mainboard/supermicro/x6dhe_g/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/supermicro/x6dhe_g/failover.c +++ b/src/mainboard/supermicro/x6dhe_g/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index 9256788..37986b9 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # MCH +chip northbridge/intel/e7520 # MCH chip drivers/generic/debug # DEBUGGING device pnp 00.0 off end device pnp 00.1 off end diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c index 854a74a..afd389c 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g2_fixups.c" #include "superio/nsc/pc87427/pc87427_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c index b4966a7..934cdb4 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/failover.c b/src/mainboard/supermicro/x6dhe_g2/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/supermicro/x6dhe_g2/failover.c +++ b/src/mainboard/supermicro/x6dhe_g2/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 2fb4ac6..3b4826b 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c index 6df3e66..41e8599 100644 --- a/src/mainboard/supermicro/x6dhr_ig/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhr_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/failover.c b/src/mainboard/supermicro/x6dhr_ig/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/supermicro/x6dhr_ig/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index bfc9c21..c3c6b9a 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c index 1998d34..70607d0 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhr2_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/failover.c b/src/mainboard/supermicro/x6dhr_ig2/failover.c index 5029d98..c5f3f80 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig2/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/northbridge/intel/E7520/chip.h b/src/northbridge/intel/E7520/chip.h index e9ee0a2..b02b8b8 100644 --- a/src/northbridge/intel/E7520/chip.h +++ b/src/northbridge/intel/E7520/chip.h @@ -1,7 +1,7 @@ -struct northbridge_intel_E7520_config +struct northbridge_intel_e7520_config { /* Interrupt line connect */ unsigned int intrline; }; -extern struct chip_operations northbridge_intel_E7520_ops; +extern struct chip_operations northbridge_intel_e7520_ops; diff --git a/src/northbridge/intel/E7520/northbridge.c b/src/northbridge/intel/E7520/northbridge.c index 4449086..160c5a7 100644 --- a/src/northbridge/intel/E7520/northbridge.c +++ b/src/northbridge/intel/E7520/northbridge.c @@ -264,7 +264,7 @@ static void enable_dev(device_t dev) } } -struct chip_operations northbridge_intel_E7520_ops = { +struct chip_operations northbridge_intel_e7520_ops = { CHIP_NAME("Intel E7520 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/E7520/pciexp_porta.c b/src/northbridge/intel/E7520/pciexp_porta.c index 5443d66..a869172 100644 --- a/src/northbridge/intel/E7520/pciexp_porta.c +++ b/src/northbridge/intel/E7520/pciexp_porta.c @@ -8,7 +8,7 @@ #include "chip.h" #include <part/hard_reset.h> -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_porta1.c b/src/northbridge/intel/E7520/pciexp_porta1.c index b4dcb2f..fd32919 100644 --- a/src/northbridge/intel/E7520/pciexp_porta1.c +++ b/src/northbridge/intel/E7520/pciexp_porta1.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_portb.c b/src/northbridge/intel/E7520/pciexp_portb.c index 7f17925..491a075 100644 --- a/src/northbridge/intel/E7520/pciexp_portb.c +++ b/src/northbridge/intel/E7520/pciexp_portb.c @@ -8,7 +8,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_portc.c b/src/northbridge/intel/E7520/pciexp_portc.c index c46610b..82d8769 100644 --- a/src/northbridge/intel/E7520/pciexp_portc.c +++ b/src/northbridge/intel/E7520/pciexp_portc.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/chip.h b/src/northbridge/intel/E7525/chip.h index 19d8c4e..7daadef 100644 --- a/src/northbridge/intel/E7525/chip.h +++ b/src/northbridge/intel/E7525/chip.h @@ -1,7 +1,7 @@ -struct northbridge_intel_E7525_config +struct northbridge_intel_e7525_config { /* Interrupt line connect */ unsigned int intrline; }; -extern struct chip_operations northbridge_intel_E7525_ops; +extern struct chip_operations northbridge_intel_e7525_ops; diff --git a/src/northbridge/intel/E7525/northbridge.c b/src/northbridge/intel/E7525/northbridge.c index 71f1722..2fa6678 100644 --- a/src/northbridge/intel/E7525/northbridge.c +++ b/src/northbridge/intel/E7525/northbridge.c @@ -264,7 +264,7 @@ static void enable_dev(device_t dev) } } -struct chip_operations northbridge_intel_E7525_ops = { +struct chip_operations northbridge_intel_e7525_ops = { CHIP_NAME("Intel E7525 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/E7525/pciexp_porta.c b/src/northbridge/intel/E7525/pciexp_porta.c index 093edec..aea9ab0 100644 --- a/src/northbridge/intel/E7525/pciexp_porta.c +++ b/src/northbridge/intel/E7525/pciexp_porta.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_porta1.c b/src/northbridge/intel/E7525/pciexp_porta1.c index 7118caa..ac3c97c 100644 --- a/src/northbridge/intel/E7525/pciexp_porta1.c +++ b/src/northbridge/intel/E7525/pciexp_porta1.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_portb.c b/src/northbridge/intel/E7525/pciexp_portb.c index f623a54..e207c6c 100644 --- a/src/northbridge/intel/E7525/pciexp_portb.c +++ b/src/northbridge/intel/E7525/pciexp_portb.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_portc.c b/src/northbridge/intel/E7525/pciexp_portc.c index 05e0b68..f211f3a 100644 --- a/src/northbridge/intel/E7525/pciexp_portc.c +++ b/src/northbridge/intel/E7525/pciexp_portc.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { |