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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-12-17 13:11:50 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-17 21:13:57 +0100 |
| commit | 2e8d4ed794f7fe58a11bd84ea7da04840b5f7a00 (patch) | |
| tree | 45065ca8f1eddaddd0c619903eb87b864569d456 | |
| parent | 3bdd45e714ebfa38e352c705b8bb7374827bc1e3 (diff) | |
| download | coreboot-staging-2e8d4ed794f7fe58a11bd84ea7da04840b5f7a00.zip coreboot-staging-2e8d4ed794f7fe58a11bd84ea7da04840b5f7a00.tar.gz | |
soc/imgtec/pistachio: add implementation for system reset
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
- watchdog scratch registers will be unaffected (hard reset
will clear them)
- the real time clock will be unaffected
BUG=none
TEST=tested on Pistachio bring up board
Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
| -rw-r--r-- | src/soc/imgtec/pistachio/reset.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c index 7bf4d03..fc581df 100644 --- a/src/soc/imgtec/pistachio/reset.c +++ b/src/soc/imgtec/pistachio/reset.c @@ -13,13 +13,15 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <reset.h> +#define PISTACHIO_WD_ADDR 0xB8102100 +#define PISTACHIO_WD_SW_RST_OFFSET 0x0000 + void hard_reset(void) { - printk(BIOS_EMERG, "reset failed!\n"); - /* TBD */ - for (;;) - ; + /* Generate system reset */ + write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); } |
