Various minor cosmetic changes in the ITE Super I/Os, mostly whitespace

changes and fixing of comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

21 files changed, 60 insertions, 56 deletions

diff --git a/src/superio/ite/it8661f/Config.lb b/src/superio/ite/it8661f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8661f/Config.lb
+++ b/src/superio/ite/it8661f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h
index 4931655..691f0e2 100644
--- a/src/superio/ite/it8661f/chip.h
+++ b/src/superio/ite/it8661f/chip.h
@@ -23,14 +23,12 @@
 
 /* This chip doesn't seem to have keyboard and mouse support. */
 
-/* #include <pc80/keyboard.h> */
 #include <uart8250.h>
 
 extern struct chip_operations superio_ite_it8661f_ops;
 
 struct superio_ite_it8661f_config {
 	struct uart8250 com1, com2;
-	/* struct pc_keyboard keyboard; */
 };
 
 #endif /* _SUPERIO_ITE_IT8661F */
diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h
index 434aebc..0905981 100644
--- a/src/superio/ite/it8661f/it8661f.h
+++ b/src/superio/ite/it8661f/it8661f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 
 /* This chip doesn't seem to have keyboard and mouse support. */
 
diff --git a/src/superio/ite/it8661f/it8661f_early_serial.c b/src/superio/ite/it8661f/it8661f_early_serial.c
index ffec3bc..522ddf7 100644
--- a/src/superio/ite/it8661f/it8661f_early_serial.c
+++ b/src/superio/ite/it8661f/it8661f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                  SIO_BASE
 #define SIO_DATA                   SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8661F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
 #define IT8661F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
 #define IT8661F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
@@ -35,7 +35,7 @@
 #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
 
 /* Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data. */
+   each line determine the address port, the last four are data. */
 static const uint8_t init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
@@ -44,7 +44,7 @@ static const uint8_t init_values[] = {
 };
 
 /* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
@@ -53,7 +53,7 @@ static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8661F Super IO chip. */
+/* Enable the peripheral devices on the IT8661F Super I/O chip. */
 static void it8661f_enable_serial(device_t dev, unsigned iobase)
 {
 	uint8_t i;
@@ -88,10 +88,10 @@ static void it8661f_enable_serial(device_t dev, unsigned iobase)
 	it8661f_sio_write(IT8661F_IR,   0x30, 0x1); /* IR */
 
 	/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
-           (clear bit 0). */
+	   (clear bit 0). */
 	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02); 
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8671f/Config.lb b/src/superio/ite/it8671f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8671f/Config.lb
+++ b/src/superio/ite/it8671f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8671f/it8671f_early_serial.c b/src/superio/ite/it8671f/it8671f_early_serial.c
index 1c30ff5..68cfcd4 100644
--- a/src/superio/ite/it8671f/it8671f_early_serial.c
+++ b/src/superio/ite/it8671f/it8671f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                  SIO_BASE
 #define SIO_DATA                   SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8671F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
 #define IT8671F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
 #define IT8671F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
@@ -35,7 +35,7 @@
 #define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
 
 /* Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data. */
+   each line determine the address port, the last four are data. */
 static const uint8_t init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
@@ -44,7 +44,7 @@ static const uint8_t init_values[] = {
 };
 
 /* The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
@@ -53,7 +53,7 @@ static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8671F Super IO chip. */
+/* Enable the peripheral devices on the IT8671F Super I/O chip. */
 static void it8671f_enable_serial(device_t dev, unsigned iobase)
 {
 	uint8_t i;
@@ -80,7 +80,7 @@ static void it8671f_enable_serial(device_t dev, unsigned iobase)
            PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
 	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
 
-	/* Activate all devices. */  
+	/* Activate all devices. */
 	it8671f_sio_write(IT8671F_FDC,  0x30, 0x01); /* Floppy */
 	it8671f_sio_write(IT8671F_SP1,  0x30, 0x01); /* Serial port 1 */
 	it8671f_sio_write(IT8671F_SP2,  0x30, 0x01); /* Serial port 2 */
@@ -93,6 +93,6 @@ static void it8671f_enable_serial(device_t dev, unsigned iobase)
 	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); 
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8673f/Config.lb b/src/superio/ite/it8673f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8673f/Config.lb
+++ b/src/superio/ite/it8673f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8673f/it8673f.h b/src/superio/ite/it8673f/it8673f.h
index d3e577e..8513a18 100644
--- a/src/superio/ite/it8673f/it8673f.h
+++ b/src/superio/ite/it8673f/it8673f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 
 #define IT8673F_FDC  0x00 /* Floppy */
 #define IT8673F_SP1  0x01 /* Com1 */
diff --git a/src/superio/ite/it8673f/it8673f_early_serial.c b/src/superio/ite/it8673f/it8673f_early_serial.c
index 3047a76..3c8c492 100644
--- a/src/superio/ite/it8673f/it8673f_early_serial.c
+++ b/src/superio/ite/it8673f/it8673f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                   SIO_BASE
 #define SIO_DATA                    SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8673F_CONFIG_REG_CC       0x02   /* Configure Control (write-only). */
 #define IT8673F_CONFIG_REG_LDN      0x07   /* Logical Device Number. */
 #define IT8673F_CONFIG_REG_CLOCKSEL 0x23   /* Clock Selection. */
@@ -35,7 +35,7 @@
 #define IT8673F_CONFIGURATION_PORT  0x0279 /* Write-only. */
 
 /* Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data. */
+   each line determine the address port, the last four are data. */
 static const uint8_t init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
@@ -44,7 +44,7 @@ static const uint8_t init_values[] = {
 };
 
 /* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
@@ -53,7 +53,7 @@ static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8673F Super IO chip. */
+/* Enable the peripheral devices on the IT8673F Super I/O chip. */
 static void it8673f_enable_serial(device_t dev, unsigned iobase)
 {
 	uint8_t i;
@@ -92,6 +92,6 @@ static void it8673f_enable_serial(device_t dev, unsigned iobase)
 	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); 
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8705f/Config.lb b/src/superio/ite/it8705f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8705f/Config.lb
+++ b/src/superio/ite/it8705f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8705f/it8705f.h b/src/superio/ite/it8705f/it8705f.h
index 54a2b28..75a2a9d 100644
--- a/src/superio/ite/it8705f/it8705f.h
+++ b/src/superio/ite/it8705f/it8705f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 /* Note: This should also work on an IT8705AF, they're almost the same. */
 
 /* This chip doesn't seem to have keyboard and mouse support. */
diff --git a/src/superio/ite/it8705f/it8705f_early_serial.c b/src/superio/ite/it8705f/it8705f_early_serial.c
index eca0d62..3ae5127 100644
--- a/src/superio/ite/it8705f/it8705f_early_serial.c
+++ b/src/superio/ite/it8705f/it8705f_early_serial.c
@@ -26,19 +26,19 @@
 #define SIO_INDEX                    SIO_BASE
 #define SIO_DATA                     SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8705F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8705F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
 
 /* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
-#define IT8705F_CONFIG_REG_CLOCKSEL  0x24 /* Clock Selection. */
-#define IT8705F_CONFIG_REG_SWSUSP    0x23 /* Software Suspend, Flash I/F. */
+#define IT8705F_CONFIG_REG_CLOCKSEL  0x24 /* Clock Selection, Flash I/F. */
+#define IT8705F_CONFIG_REG_SWSUSP    0x23 /* Software Suspend. */
 
 #define IT8705F_CONFIGURATION_PORT   0x2e /* Write-only. */
 
 /* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
@@ -47,7 +47,7 @@ static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8705F Super IO chip. */
+/* Enable the peripheral devices on the IT8705F Super I/O chip. */
 static void it8705f_enable_serial(device_t dev, unsigned iobase)
 {
 	/* (1) Enter the configuration state (MB PnP mode). */
@@ -63,8 +63,8 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase)
 	/* (2) Modify the data of configuration registers. */
 
 	/* Select the chip to configure (if there's more than one).
-         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-         * If this register is not written, both chips are configured. */
+           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+           If this register is not written, both chips are configured. */
 	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
 
 	/* Enable all devices. */
@@ -73,18 +73,17 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase)
 	it8705f_sio_write(IT8705F_SP2,  0x30, 0x1); /* Serial port 2 */
 	it8705f_sio_write(IT8705F_PP,   0x30, 0x1); /* Parallel port */
 	it8705f_sio_write(IT8705F_EC,   0x30, 0x1); /* Environment controller */
-	/* GPIO */
 	it8705f_sio_write(IT8705F_GAME, 0x30, 0x1); /* GAME port */
 	it8705f_sio_write(IT8705F_IR,   0x30, 0x1); /* Consumer IR */
 	it8705f_sio_write(IT8705F_MIDI, 0x30, 0x1); /* MIDI port */
 
 	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
-	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x00); */
+	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); */
 
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); 
+	it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8712f/Config.lb b/src/superio/ite/it8712f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8712f/Config.lb
+++ b/src/superio/ite/it8712f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h
index dd0413a..22edd90 100644
--- a/src/superio/ite/it8712f/it8712f.h
+++ b/src/superio/ite/it8712f/it8712f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 
 #define IT8712F_FDC  0x00 /* Floppy */
 #define IT8712F_SP1  0x01 /* Com1 */
diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c
index dc6b266..e0828df 100644
--- a/src/superio/ite/it8712f/it8712f_early_serial.c
+++ b/src/superio/ite/it8712f/it8712f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                    SIO_BASE
 #define SIO_DATA                     SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8712F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
@@ -36,7 +36,7 @@
 #define IT8712F_CONFIGURATION_PORT   0x2e /* Write-only. */
 
 /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
@@ -45,7 +45,7 @@ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8712F Super IO chip. */
+/* Enable the peripheral devices on the IT8712F Super I/O chip. */
 static void it8712f_enable_serial(device_t dev, unsigned iobase)
 {
 	/* (1) Enter the configuration state (MB PnP mode). */
@@ -61,8 +61,8 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase)
 	/* (2) Modify the data of configuration registers. */
 
 	/* Select the chip to configure (if there's more than one).
-         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-         * If this register is not written, both chips are configured. */
+           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+           If this register is not written, both chips are configured. */
 	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
 
 	/* Enable all devices. */
@@ -78,12 +78,12 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase)
 	it8712f_sio_write(IT8712F_IR,   0x30, 0x1); /* Consumer IR */
 
 	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
-	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x00); */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); */
 
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); 
+	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8716f/Config.lb b/src/superio/ite/it8716f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8716f/Config.lb
+++ b/src/superio/ite/it8716f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h
index f839124..6afb58d 100644
--- a/src/superio/ite/it8716f/it8716f.h
+++ b/src/superio/ite/it8716f/it8716f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 
 #define IT8716F_FDC  0x00 /* Floppy */
 #define IT8716F_SP1  0x01 /* Com1 */
diff --git a/src/superio/ite/it8716f/it8716f_early_serial.c b/src/superio/ite/it8716f/it8716f_early_serial.c
index 1865624..4dedc8f 100644
--- a/src/superio/ite/it8716f/it8716f_early_serial.c
+++ b/src/superio/ite/it8716f/it8716f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                    SIO_BASE
 #define SIO_DATA                     SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8716F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8716F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
@@ -36,7 +36,7 @@
 #define IT8716F_CONFIGURATION_PORT   0x2e /* Write-only. */
 
 /* The content of IT8716F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8716f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8716F_CONFIG_REG_LDN, SIO_BASE);
@@ -45,7 +45,7 @@ static void it8716f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8716F Super IO chip. */
+/* Enable the peripheral devices on the IT8716F Super I/O chip. */
 static void it8716f_enable_serial(device_t dev, unsigned iobase)
 {
 	/* (1) Enter the configuration state (MB PnP mode). */
@@ -61,8 +61,8 @@ static void it8716f_enable_serial(device_t dev, unsigned iobase)
 	/* (2) Modify the data of configuration registers. */
 
 	/* Select the chip to configure (if there's more than one).
-         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-         * If this register is not written, both chips are configured. */
+           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+           If this register is not written, both chips are configured. */
 	/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CONFIGSEL, 0x00); */
 
 	/* Enable all devices. */
@@ -78,12 +78,12 @@ static void it8716f_enable_serial(device_t dev, unsigned iobase)
 	it8716f_sio_write(IT8716F_IR,   0x30, 0x1); /* Consumer IR */
 
 	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
-	/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x00); */
+	/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x01); */
 
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CC, 0x02); 
+	it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CC, 0x02);
 }
 
diff --git a/src/superio/ite/it8718f/Config.lb b/src/superio/ite/it8718f/Config.lb
index 6a4d526..a03c28b 100644
--- a/src/superio/ite/it8718f/Config.lb
+++ b/src/superio/ite/it8718f/Config.lb
@@ -20,3 +20,4 @@
 
 config chip.h
 object superio.o
+
diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h
index 783d691..5e4ccf0 100644
--- a/src/superio/ite/it8718f/it8718f.h
+++ b/src/superio/ite/it8718f/it8718f.h
@@ -19,7 +19,7 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
-/* Status: untested on real hardware, but it compiles. */
+/* Status: Untested on real hardware, but it compiles. */
 
 #define IT8718F_FDC  0x00 /* Floppy */
 #define IT8718F_SP1  0x01 /* Com1 */
diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c
index a75842d..212f964 100644
--- a/src/superio/ite/it8718f/it8718f_early_serial.c
+++ b/src/superio/ite/it8718f/it8718f_early_serial.c
@@ -26,7 +26,7 @@
 #define SIO_INDEX                    SIO_BASE
 #define SIO_DATA                     SIO_BASE+1
 
-/* Global Configuration Registers. */
+/* Global configuration registers. */
 #define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
@@ -36,7 +36,7 @@
 #define IT8718F_CONFIGURATION_PORT   0x2e /* Write-only. */
 
 /* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register. */
+   LDN the register belongs to, before you can access the register. */
 static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
 	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
@@ -45,7 +45,7 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8718F Super IO chip. */
+/* Enable the peripheral devices on the IT8718F Super I/O chip. */
 static void it8718f_enable_serial(device_t dev, unsigned iobase)
 {
 	/* (1) Enter the configuration state (MB PnP mode). */
@@ -61,8 +61,8 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
 	/* (2) Modify the data of configuration registers. */
 
 	/* Select the chip to configure (if there's more than one).
-         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-         * If this register is not written, both chips are configured. */
+           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+           If this register is not written, both chips are configured. */
 	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
 
 	/* Enable all devices. */
@@ -76,12 +76,12 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
 	it8718f_sio_write(IT8718F_IR,   0x30, 0x1); /* Consumer IR */
 
 	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x00); */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01); */
 
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); 
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
 }