Initial import of modified u-boot tree

Original upstream URL: git://git.denx.de/u-boot.git Original upstream GIT hash: 62c175fbb8a0f9a926c88294ea9f7e88eb898f6c
author: Timothy Pearson <tpearson@raptorengineering.com> 2017-08-23 15:54:21 -0500
committer: Timothy Pearson <tpearson@raptorengineering.com> 2017-08-23 15:54:21 -0500
commit: 0223e595f4033e91e93403a7317bcc9e47676b8f (patch)
tree: 2ccd7127bc343f82456b76eeb0da2d380f6eaf65 /board/aspeed/ast2050
download: ast2050-uboot-0223e595f4033e91e93403a7317bcc9e47676b8f.zip
ast2050-uboot-0223e595f4033e91e93403a7317bcc9e47676b8f.tar.gz
34 files changed, 10781 insertions, 0 deletions
diff --git a/board/aspeed/ast2050/Makefile b/board/aspeed/ast2050/Makefile
new file mode 100644
index 0000000..c6218f9
--- /dev/null
+++ b/board/aspeed/ast2050/Makefile
@@ -0,0 +1,45 @@
+# (c) 2017 Raptor Engineering, LLC
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= ast2050.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o
+
+ifdef CONFIG_FPGA_ASPEED
+SOBJS   := platform_fpga.o
+else
+SOBJS   := platform.o
+endif
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+#	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/aspeed/ast2050/aes.c b/board/aspeed/ast2050/aes.c
new file mode 100644
index 0000000..d9e1cd4
--- /dev/null
+++ b/board/aspeed/ast2050/aes.c
@@ -0,0 +1,575 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  AES implementation
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/* uncomment the following line to run the test suite */
+
+/* #define TEST */
+
+/* uncomment the following line to use pre-computed tables */
+/* otherwise the tables will be generated at the first run */
+
+#define FIXED_TABLES
+
+#ifndef FIXED_TABLES
+
+/* forward S-box & tables */
+
+uint32 FSb[256];
+uint32 FT0[256]; 
+uint32 FT1[256]; 
+uint32 FT2[256]; 
+uint32 FT3[256]; 
+
+/* reverse S-box & tables */
+
+uint32 RSb[256];
+uint32 RT0[256];
+uint32 RT1[256];
+uint32 RT2[256];
+uint32 RT3[256];
+
+/* round constants */
+
+uint32 RCON[10];
+
+/* tables generation flag */
+
+int do_init = 1;
+
+/* tables generation routine */
+
+#define ROTR8(x) ( ( ( x << 24 ) & 0xFFFFFFFF ) | \
+                   ( ( x & 0xFFFFFFFF ) >>  8 ) )
+
+#define XTIME(x) ( ( x <<  1 ) ^ ( ( x & 0x80 ) ? 0x1B : 0x00 ) )
+#define MUL(x,y) ( ( x &&  y ) ? pow[(log[x] + log[y]) % 255] : 0 )
+
+void aes_gen_tables( void )
+{
+    int i;
+    uint8 x, y;
+    uint8 pow[256];
+    uint8 log[256];
+
+    /* compute pow and log tables over GF(2^8) */
+
+    for( i = 0, x = 1; i < 256; i++, x ^= XTIME( x ) )
+    {
+        pow[i] = x;
+        log[x] = i;
+    }
+
+    /* calculate the round constants */
+
+    for( i = 0, x = 1; i < 10; i++, x = XTIME( x ) )
+    {
+        RCON[i] = (uint32) x << 24;
+    }
+
+    /* generate the forward and reverse S-boxes */
+
+    FSb[0x00] = 0x63;
+    RSb[0x63] = 0x00;
+
+    for( i = 1; i < 256; i++ )
+    {
+        x = pow[255 - log[i]];
+
+        y = x;  y = ( y << 1 ) | ( y >> 7 );
+        x ^= y; y = ( y << 1 ) | ( y >> 7 );
+        x ^= y; y = ( y << 1 ) | ( y >> 7 );
+        x ^= y; y = ( y << 1 ) | ( y >> 7 );
+        x ^= y ^ 0x63;
+
+        FSb[i] = x;
+        RSb[x] = i;
+    }
+
+    /* generate the forward and reverse tables */
+
+    for( i = 0; i < 256; i++ )
+    {
+        x = (unsigned char) FSb[i]; y = XTIME( x );
+
+        FT0[i] =   (uint32) ( x ^ y ) ^
+                 ( (uint32) x <<  8 ) ^
+                 ( (uint32) x << 16 ) ^
+                 ( (uint32) y << 24 );
+
+        FT0[i] &= 0xFFFFFFFF;
+
+        FT1[i] = ROTR8( FT0[i] );
+        FT2[i] = ROTR8( FT1[i] );
+        FT3[i] = ROTR8( FT2[i] );
+
+        y = (unsigned char) RSb[i];
+
+        RT0[i] = ( (uint32) MUL( 0x0B, y )       ) ^
+                 ( (uint32) MUL( 0x0D, y ) <<  8 ) ^
+                 ( (uint32) MUL( 0x09, y ) << 16 ) ^
+                 ( (uint32) MUL( 0x0E, y ) << 24 );
+
+        RT0[i] &= 0xFFFFFFFF;
+
+        RT1[i] = ROTR8( RT0[i] );
+        RT2[i] = ROTR8( RT1[i] );
+        RT3[i] = ROTR8( RT2[i] );
+    }
+}
+
+#else
+
+/* forward S-box */
+
+static const uint32 FSb[256] =
+{
+    0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
+    0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
+    0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
+    0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
+    0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
+    0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
+    0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
+    0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
+    0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
+    0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
+    0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
+    0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
+    0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
+    0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
+    0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
+    0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
+    0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
+    0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
+    0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
+    0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
+    0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
+    0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
+    0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
+    0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
+    0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
+    0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
+    0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
+    0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
+    0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
+    0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
+    0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
+    0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
+};
+
+/* forward tables */
+
+#define FT \
+\
+    V(C6,63,63,A5), V(F8,7C,7C,84), V(EE,77,77,99), V(F6,7B,7B,8D), \
+    V(FF,F2,F2,0D), V(D6,6B,6B,BD), V(DE,6F,6F,B1), V(91,C5,C5,54), \
+    V(60,30,30,50), V(02,01,01,03), V(CE,67,67,A9), V(56,2B,2B,7D), \
+    V(E7,FE,FE,19), V(B5,D7,D7,62), V(4D,AB,AB,E6), V(EC,76,76,9A), \
+    V(8F,CA,CA,45), V(1F,82,82,9D), V(89,C9,C9,40), V(FA,7D,7D,87), \
+    V(EF,FA,FA,15), V(B2,59,59,EB), V(8E,47,47,C9), V(FB,F0,F0,0B), \
+    V(41,AD,AD,EC), V(B3,D4,D4,67), V(5F,A2,A2,FD), V(45,AF,AF,EA), \
+    V(23,9C,9C,BF), V(53,A4,A4,F7), V(E4,72,72,96), V(9B,C0,C0,5B), \
+    V(75,B7,B7,C2), V(E1,FD,FD,1C), V(3D,93,93,AE), V(4C,26,26,6A), \
+    V(6C,36,36,5A), V(7E,3F,3F,41), V(F5,F7,F7,02), V(83,CC,CC,4F), \
+    V(68,34,34,5C), V(51,A5,A5,F4), V(D1,E5,E5,34), V(F9,F1,F1,08), \
+    V(E2,71,71,93), V(AB,D8,D8,73), V(62,31,31,53), V(2A,15,15,3F), \
+    V(08,04,04,0C), V(95,C7,C7,52), V(46,23,23,65), V(9D,C3,C3,5E), \
+    V(30,18,18,28), V(37,96,96,A1), V(0A,05,05,0F), V(2F,9A,9A,B5), \
+    V(0E,07,07,09), V(24,12,12,36), V(1B,80,80,9B), V(DF,E2,E2,3D), \
+    V(CD,EB,EB,26), V(4E,27,27,69), V(7F,B2,B2,CD), V(EA,75,75,9F), \
+    V(12,09,09,1B), V(1D,83,83,9E), V(58,2C,2C,74), V(34,1A,1A,2E), \
+    V(36,1B,1B,2D), V(DC,6E,6E,B2), V(B4,5A,5A,EE), V(5B,A0,A0,FB), \
+    V(A4,52,52,F6), V(76,3B,3B,4D), V(B7,D6,D6,61), V(7D,B3,B3,CE), \
+    V(52,29,29,7B), V(DD,E3,E3,3E), V(5E,2F,2F,71), V(13,84,84,97), \
+    V(A6,53,53,F5), V(B9,D1,D1,68), V(00,00,00,00), V(C1,ED,ED,2C), \
+    V(40,20,20,60), V(E3,FC,FC,1F), V(79,B1,B1,C8), V(B6,5B,5B,ED), \
+    V(D4,6A,6A,BE), V(8D,CB,CB,46), V(67,BE,BE,D9), V(72,39,39,4B), \
+    V(94,4A,4A,DE), V(98,4C,4C,D4), V(B0,58,58,E8), V(85,CF,CF,4A), \
+    V(BB,D0,D0,6B), V(C5,EF,EF,2A), V(4F,AA,AA,E5), V(ED,FB,FB,16), \
+    V(86,43,43,C5), V(9A,4D,4D,D7), V(66,33,33,55), V(11,85,85,94), \
+    V(8A,45,45,CF), V(E9,F9,F9,10), V(04,02,02,06), V(FE,7F,7F,81), \
+    V(A0,50,50,F0), V(78,3C,3C,44), V(25,9F,9F,BA), V(4B,A8,A8,E3), \
+    V(A2,51,51,F3), V(5D,A3,A3,FE), V(80,40,40,C0), V(05,8F,8F,8A), \
+    V(3F,92,92,AD), V(21,9D,9D,BC), V(70,38,38,48), V(F1,F5,F5,04), \
+    V(63,BC,BC,DF), V(77,B6,B6,C1), V(AF,DA,DA,75), V(42,21,21,63), \
+    V(20,10,10,30), V(E5,FF,FF,1A), V(FD,F3,F3,0E), V(BF,D2,D2,6D), \
+    V(81,CD,CD,4C), V(18,0C,0C,14), V(26,13,13,35), V(C3,EC,EC,2F), \
+    V(BE,5F,5F,E1), V(35,97,97,A2), V(88,44,44,CC), V(2E,17,17,39), \
+    V(93,C4,C4,57), V(55,A7,A7,F2), V(FC,7E,7E,82), V(7A,3D,3D,47), \
+    V(C8,64,64,AC), V(BA,5D,5D,E7), V(32,19,19,2B), V(E6,73,73,95), \
+    V(C0,60,60,A0), V(19,81,81,98), V(9E,4F,4F,D1), V(A3,DC,DC,7F), \
+    V(44,22,22,66), V(54,2A,2A,7E), V(3B,90,90,AB), V(0B,88,88,83), \
+    V(8C,46,46,CA), V(C7,EE,EE,29), V(6B,B8,B8,D3), V(28,14,14,3C), \
+    V(A7,DE,DE,79), V(BC,5E,5E,E2), V(16,0B,0B,1D), V(AD,DB,DB,76), \
+    V(DB,E0,E0,3B), V(64,32,32,56), V(74,3A,3A,4E), V(14,0A,0A,1E), \
+    V(92,49,49,DB), V(0C,06,06,0A), V(48,24,24,6C), V(B8,5C,5C,E4), \
+    V(9F,C2,C2,5D), V(BD,D3,D3,6E), V(43,AC,AC,EF), V(C4,62,62,A6), \
+    V(39,91,91,A8), V(31,95,95,A4), V(D3,E4,E4,37), V(F2,79,79,8B), \
+    V(D5,E7,E7,32), V(8B,C8,C8,43), V(6E,37,37,59), V(DA,6D,6D,B7), \
+    V(01,8D,8D,8C), V(B1,D5,D5,64), V(9C,4E,4E,D2), V(49,A9,A9,E0), \
+    V(D8,6C,6C,B4), V(AC,56,56,FA), V(F3,F4,F4,07), V(CF,EA,EA,25), \
+    V(CA,65,65,AF), V(F4,7A,7A,8E), V(47,AE,AE,E9), V(10,08,08,18), \
+    V(6F,BA,BA,D5), V(F0,78,78,88), V(4A,25,25,6F), V(5C,2E,2E,72), \
+    V(38,1C,1C,24), V(57,A6,A6,F1), V(73,B4,B4,C7), V(97,C6,C6,51), \
+    V(CB,E8,E8,23), V(A1,DD,DD,7C), V(E8,74,74,9C), V(3E,1F,1F,21), \
+    V(96,4B,4B,DD), V(61,BD,BD,DC), V(0D,8B,8B,86), V(0F,8A,8A,85), \
+    V(E0,70,70,90), V(7C,3E,3E,42), V(71,B5,B5,C4), V(CC,66,66,AA), \
+    V(90,48,48,D8), V(06,03,03,05), V(F7,F6,F6,01), V(1C,0E,0E,12), \
+    V(C2,61,61,A3), V(6A,35,35,5F), V(AE,57,57,F9), V(69,B9,B9,D0), \
+    V(17,86,86,91), V(99,C1,C1,58), V(3A,1D,1D,27), V(27,9E,9E,B9), \
+    V(D9,E1,E1,38), V(EB,F8,F8,13), V(2B,98,98,B3), V(22,11,11,33), \
+    V(D2,69,69,BB), V(A9,D9,D9,70), V(07,8E,8E,89), V(33,94,94,A7), \
+    V(2D,9B,9B,B6), V(3C,1E,1E,22), V(15,87,87,92), V(C9,E9,E9,20), \
+    V(87,CE,CE,49), V(AA,55,55,FF), V(50,28,28,78), V(A5,DF,DF,7A), \
+    V(03,8C,8C,8F), V(59,A1,A1,F8), V(09,89,89,80), V(1A,0D,0D,17), \
+    V(65,BF,BF,DA), V(D7,E6,E6,31), V(84,42,42,C6), V(D0,68,68,B8), \
+    V(82,41,41,C3), V(29,99,99,B0), V(5A,2D,2D,77), V(1E,0F,0F,11), \
+    V(7B,B0,B0,CB), V(A8,54,54,FC), V(6D,BB,BB,D6), V(2C,16,16,3A)
+
+#define V(a,b,c,d) 0x##a##b##c##d
+static const uint32 FT0[256] = { FT };
+#undef V
+
+#define V(a,b,c,d) 0x##d##a##b##c
+static const uint32 FT1[256] = { FT };
+#undef V
+
+#define V(a,b,c,d) 0x##c##d##a##b
+static const uint32 FT2[256] = { FT };
+#undef V
+
+#define V(a,b,c,d) 0x##b##c##d##a
+static const uint32 FT3[256] = { FT };
+#undef V
+
+#undef FT
+
+/* reverse S-box */
+
+static const uint32 RSb[256] =
+{
+    0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
+    0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
+    0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
+    0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
+    0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
+    0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
+    0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
+    0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
+    0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
+    0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
+    0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
+    0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
+    0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
+    0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
+    0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
+    0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
+    0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
+    0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
+    0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
+    0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
+    0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
+    0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
+    0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
+    0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
+    0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
+    0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
+    0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
+    0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
+    0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
+    0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
+    0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
+    0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
+};
+
+/* reverse tables */
+
+#define RT \
+\
+    V(51,F4,A7,50), V(7E,41,65,53), V(1A,17,A4,C3), V(3A,27,5E,96), \
+    V(3B,AB,6B,CB), V(1F,9D,45,F1), V(AC,FA,58,AB), V(4B,E3,03,93), \
+    V(20,30,FA,55), V(AD,76,6D,F6), V(88,CC,76,91), V(F5,02,4C,25), \
+    V(4F,E5,D7,FC), V(C5,2A,CB,D7), V(26,35,44,80), V(B5,62,A3,8F), \
+    V(DE,B1,5A,49), V(25,BA,1B,67), V(45,EA,0E,98), V(5D,FE,C0,E1), \
+    V(C3,2F,75,02), V(81,4C,F0,12), V(8D,46,97,A3), V(6B,D3,F9,C6), \
+    V(03,8F,5F,E7), V(15,92,9C,95), V(BF,6D,7A,EB), V(95,52,59,DA), \
+    V(D4,BE,83,2D), V(58,74,21,D3), V(49,E0,69,29), V(8E,C9,C8,44), \
+    V(75,C2,89,6A), V(F4,8E,79,78), V(99,58,3E,6B), V(27,B9,71,DD), \
+    V(BE,E1,4F,B6), V(F0,88,AD,17), V(C9,20,AC,66), V(7D,CE,3A,B4), \
+    V(63,DF,4A,18), V(E5,1A,31,82), V(97,51,33,60), V(62,53,7F,45), \
+    V(B1,64,77,E0), V(BB,6B,AE,84), V(FE,81,A0,1C), V(F9,08,2B,94), \
+    V(70,48,68,58), V(8F,45,FD,19), V(94,DE,6C,87), V(52,7B,F8,B7), \
+    V(AB,73,D3,23), V(72,4B,02,E2), V(E3,1F,8F,57), V(66,55,AB,2A), \
+    V(B2,EB,28,07), V(2F,B5,C2,03), V(86,C5,7B,9A), V(D3,37,08,A5), \
+    V(30,28,87,F2), V(23,BF,A5,B2), V(02,03,6A,BA), V(ED,16,82,5C), \
+    V(8A,CF,1C,2B), V(A7,79,B4,92), V(F3,07,F2,F0), V(4E,69,E2,A1), \
+    V(65,DA,F4,CD), V(06,05,BE,D5), V(D1,34,62,1F), V(C4,A6,FE,8A), \
+    V(34,2E,53,9D), V(A2,F3,55,A0), V(05,8A,E1,32), V(A4,F6,EB,75), \
+    V(0B,83,EC,39), V(40,60,EF,AA), V(5E,71,9F,06), V(BD,6E,10,51), \
+    V(3E,21,8A,F9), V(96,DD,06,3D), V(DD,3E,05,AE), V(4D,E6,BD,46), \
+    V(91,54,8D,B5), V(71,C4,5D,05), V(04,06,D4,6F), V(60,50,15,FF), \
+    V(19,98,FB,24), V(D6,BD,E9,97), V(89,40,43,CC), V(67,D9,9E,77), \
+    V(B0,E8,42,BD), V(07,89,8B,88), V(E7,19,5B,38), V(79,C8,EE,DB), \
+    V(A1,7C,0A,47), V(7C,42,0F,E9), V(F8,84,1E,C9), V(00,00,00,00), \
+    V(09,80,86,83), V(32,2B,ED,48), V(1E,11,70,AC), V(6C,5A,72,4E), \
+    V(FD,0E,FF,FB), V(0F,85,38,56), V(3D,AE,D5,1E), V(36,2D,39,27), \
+    V(0A,0F,D9,64), V(68,5C,A6,21), V(9B,5B,54,D1), V(24,36,2E,3A), \
+    V(0C,0A,67,B1), V(93,57,E7,0F), V(B4,EE,96,D2), V(1B,9B,91,9E), \
+    V(80,C0,C5,4F), V(61,DC,20,A2), V(5A,77,4B,69), V(1C,12,1A,16), \
+    V(E2,93,BA,0A), V(C0,A0,2A,E5), V(3C,22,E0,43), V(12,1B,17,1D), \
+    V(0E,09,0D,0B), V(F2,8B,C7,AD), V(2D,B6,A8,B9), V(14,1E,A9,C8), \
+    V(57,F1,19,85), V(AF,75,07,4C), V(EE,99,DD,BB), V(A3,7F,60,FD), \
+    V(F7,01,26,9F), V(5C,72,F5,BC), V(44,66,3B,C5), V(5B,FB,7E,34), \
+    V(8B,43,29,76), V(CB,23,C6,DC), V(B6,ED,FC,68), V(B8,E4,F1,63), \
+    V(D7,31,DC,CA), V(42,63,85,10), V(13,97,22,40), V(84,C6,11,20), \
+    V(85,4A,24,7D), V(D2,BB,3D,F8), V(AE,F9,32,11), V(C7,29,A1,6D), \
+    V(1D,9E,2F,4B), V(DC,B2,30,F3), V(0D,86,52,EC), V(77,C1,E3,D0), \
+    V(2B,B3,16,6C), V(A9,70,B9,99), V(11,94,48,FA), V(47,E9,64,22), \
+    V(A8,FC,8C,C4), V(A0,F0,3F,1A), V(56,7D,2C,D8), V(22,33,90,EF), \
+    V(87,49,4E,C7), V(D9,38,D1,C1), V(8C,CA,A2,FE), V(98,D4,0B,36), \
+    V(A6,F5,81,CF), V(A5,7A,DE,28), V(DA,B7,8E,26), V(3F,AD,BF,A4), \
+    V(2C,3A,9D,E4), V(50,78,92,0D), V(6A,5F,CC,9B), V(54,7E,46,62), \
+    V(F6,8D,13,C2), V(90,D8,B8,E8), V(2E,39,F7,5E), V(82,C3,AF,F5), \
+    V(9F,5D,80,BE), V(69,D0,93,7C), V(6F,D5,2D,A9), V(CF,25,12,B3), \
+    V(C8,AC,99,3B), V(10,18,7D,A7), V(E8,9C,63,6E), V(DB,3B,BB,7B), \
+    V(CD,26,78,09), V(6E,59,18,F4), V(EC,9A,B7,01), V(83,4F,9A,A8), \
+    V(E6,95,6E,65), V(AA,FF,E6,7E), V(21,BC,CF,08), V(EF,15,E8,E6), \
+    V(BA,E7,9B,D9), V(4A,6F,36,CE), V(EA,9F,09,D4), V(29,B0,7C,D6), \
+    V(31,A4,B2,AF), V(2A,3F,23,31), V(C6,A5,94,30), V(35,A2,66,C0), \
+    V(74,4E,BC,37), V(FC,82,CA,A6), V(E0,90,D0,B0), V(33,A7,D8,15), \
+    V(F1,04,98,4A), V(41,EC,DA,F7), V(7F,CD,50,0E), V(17,91,F6,2F), \
+    V(76,4D,D6,8D), V(43,EF,B0,4D), V(CC,AA,4D,54), V(E4,96,04,DF), \
+    V(9E,D1,B5,E3), V(4C,6A,88,1B), V(C1,2C,1F,B8), V(46,65,51,7F), \
+    V(9D,5E,EA,04), V(01,8C,35,5D), V(FA,87,74,73), V(FB,0B,41,2E), \
+    V(B3,67,1D,5A), V(92,DB,D2,52), V(E9,10,56,33), V(6D,D6,47,13), \
+    V(9A,D7,61,8C), V(37,A1,0C,7A), V(59,F8,14,8E), V(EB,13,3C,89), \
+    V(CE,A9,27,EE), V(B7,61,C9,35), V(E1,1C,E5,ED), V(7A,47,B1,3C), \
+    V(9C,D2,DF,59), V(55,F2,73,3F), V(18,14,CE,79), V(73,C7,37,BF), \
+    V(53,F7,CD,EA), V(5F,FD,AA,5B), V(DF,3D,6F,14), V(78,44,DB,86), \
+    V(CA,AF,F3,81), V(B9,68,C4,3E), V(38,24,34,2C), V(C2,A3,40,5F), \
+    V(16,1D,C3,72), V(BC,E2,25,0C), V(28,3C,49,8B), V(FF,0D,95,41), \
+    V(39,A8,01,71), V(08,0C,B3,DE), V(D8,B4,E4,9C), V(64,56,C1,90), \
+    V(7B,CB,84,61), V(D5,32,B6,70), V(48,6C,5C,74), V(D0,B8,57,42)
+
+#define V(a,b,c,d) 0x##a##b##c##d
+static const uint32 RT0[256] = { RT };
+#undef V
+
+#define V(a,b,c,d) 0x##d##a##b##c
+static const uint32 RT1[256] = { RT };
+#undef V
+
+#define V(a,b,c,d) 0x##c##d##a##b
+static const uint32 RT2[256] = { RT };
+#undef V
+
+#define V(a,b,c,d) 0x##b##c##d##a
+static const uint32 RT3[256] = { RT };
+#undef V
+
+#undef RT
+
+/* round constants */
+
+static const uint32 RCON[10] =
+{
+    0x01000000, 0x02000000, 0x04000000, 0x08000000,
+    0x10000000, 0x20000000, 0x40000000, 0x80000000,
+    0x1B000000, 0x36000000
+};
+
+int do_init = 0;
+
+void aes_gen_tables( void )
+{
+}
+
+#endif
+
+/* platform-independant 32-bit integer manipulation macros */
+
+#define GET_UINT32_aes(n,b,i)                       \
+{                                               \
+    (n) = ( (uint32) (b)[(i)    ] << 24 )       \
+        | ( (uint32) (b)[(i) + 1] << 16 )       \
+        | ( (uint32) (b)[(i) + 2] <<  8 )       \
+        | ( (uint32) (b)[(i) + 3]       );      \
+}
+
+#define PUT_UINT32_aes(n,b,i)                       \
+{                                               \
+    (b)[(i)    ] = (uint8) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (uint8) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (uint8) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (uint8) ( (n)       );       \
+}
+
+/* decryption key schedule tables */
+
+int KT_init = 1;
+
+uint32 KT0[256];
+uint32 KT1[256];
+uint32 KT2[256];
+uint32 KT3[256];
+
+/* AES key scheduling routine */
+int aes_set_key( aes_context *ctx, uint8 *key, int nbits )
+{
+    int i;
+    uint32 *RK, *SK;
+
+    if( do_init )
+    {
+        aes_gen_tables();
+
+        do_init = 0;
+    }
+
+    switch( nbits )
+    {
+        case 128: ctx->nr = 10; break;
+        case 192: ctx->nr = 12; break;
+        case 256: ctx->nr = 14; break;
+        default : return( 1 );
+    }
+
+    RK = ctx->erk;
+
+    for( i = 0; i < (nbits >> 5); i++ )
+    {
+        GET_UINT32_aes( RK[i], key, i * 4 );
+    }
+
+    /* setup encryption round keys */
+
+    switch( nbits )
+    {
+    case 128:
+
+        for( i = 0; i < 10; i++, RK += 4 )
+        {
+            RK[4]  = RK[0] ^ RCON[i] ^
+                        ( FSb[ (uint8) ( RK[3] >> 16 ) ] << 24 ) ^
+                        ( FSb[ (uint8) ( RK[3] >>  8 ) ] << 16 ) ^
+                        ( FSb[ (uint8) ( RK[3]       ) ] <<  8 ) ^
+                        ( FSb[ (uint8) ( RK[3] >> 24 ) ]       );
+
+            RK[5]  = RK[1] ^ RK[4];
+            RK[6]  = RK[2] ^ RK[5];
+            RK[7]  = RK[3] ^ RK[6];
+        }
+        break;
+
+    case 192:
+
+        for( i = 0; i < 8; i++, RK += 6 )
+        {
+            RK[6]  = RK[0] ^ RCON[i] ^
+                        ( FSb[ (uint8) ( RK[5] >> 16 ) ] << 24 ) ^
+                        ( FSb[ (uint8) ( RK[5] >>  8 ) ] << 16 ) ^
+                        ( FSb[ (uint8) ( RK[5]       ) ] <<  8 ) ^
+                        ( FSb[ (uint8) ( RK[5] >> 24 ) ]       );
+
+            RK[7]  = RK[1] ^ RK[6];
+            RK[8]  = RK[2] ^ RK[7];
+            RK[9]  = RK[3] ^ RK[8];
+            RK[10] = RK[4] ^ RK[9];
+            RK[11] = RK[5] ^ RK[10];
+        }
+        break;
+
+    case 256:
+
+        for( i = 0; i < 7; i++, RK += 8 )
+        {
+            RK[8]  = RK[0] ^ RCON[i] ^
+                        ( FSb[ (uint8) ( RK[7] >> 16 ) ] << 24 ) ^
+                        ( FSb[ (uint8) ( RK[7] >>  8 ) ] << 16 ) ^
+                        ( FSb[ (uint8) ( RK[7]       ) ] <<  8 ) ^
+                        ( FSb[ (uint8) ( RK[7] >> 24 ) ]       );
+
+            RK[9]  = RK[1] ^ RK[8];
+            RK[10] = RK[2] ^ RK[9];
+            RK[11] = RK[3] ^ RK[10];
+
+            RK[12] = RK[4] ^
+                        ( FSb[ (uint8) ( RK[11] >> 24 ) ] << 24 ) ^
+                        ( FSb[ (uint8) ( RK[11] >> 16 ) ] << 16 ) ^
+                        ( FSb[ (uint8) ( RK[11] >>  8 ) ] <<  8 ) ^
+                        ( FSb[ (uint8) ( RK[11]       ) ]       );
+
+            RK[13] = RK[5] ^ RK[12];
+            RK[14] = RK[6] ^ RK[13];
+            RK[15] = RK[7] ^ RK[14];
+        }
+        break;
+    }
+
+    /* setup decryption round keys */
+
+    if( KT_init )
+    {
+        for( i = 0; i < 256; i++ )
+        {
+            KT0[i] = RT0[ FSb[i] ];
+            KT1[i] = RT1[ FSb[i] ];
+            KT2[i] = RT2[ FSb[i] ];
+            KT3[i] = RT3[ FSb[i] ];
+        }
+
+        KT_init = 0;
+    }
+
+    SK = ctx->drk;
+
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+
+    for( i = 1; i < ctx->nr; i++ )
+    {
+        RK -= 8;
+
+        *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
+                KT1[ (uint8) ( *RK >> 16 ) ] ^
+                KT2[ (uint8) ( *RK >>  8 ) ] ^
+                KT3[ (uint8) ( *RK       ) ]; RK++;
+
+        *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
+                KT1[ (uint8) ( *RK >> 16 ) ] ^
+                KT2[ (uint8) ( *RK >>  8 ) ] ^
+                KT3[ (uint8) ( *RK       ) ]; RK++;
+
+        *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
+                KT1[ (uint8) ( *RK >> 16 ) ] ^
+                KT2[ (uint8) ( *RK >>  8 ) ] ^
+                KT3[ (uint8) ( *RK       ) ]; RK++;
+
+        *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
+                KT1[ (uint8) ( *RK >> 16 ) ] ^
+                KT2[ (uint8) ( *RK >>  8 ) ] ^
+                KT3[ (uint8) ( *RK       ) ]; RK++;
+    }
+
+    RK -= 8;
+
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+    *SK++ = *RK++;
+
+    return( 0 );
+}
diff --git a/board/aspeed/ast2050/ast2050.c b/board/aspeed/ast2050/ast2050.c
new file mode 100644
index 0000000..efad86c
--- /dev/null
+++ b/board/aspeed/ast2050/ast2050.c
@@ -0,0 +1,197 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include "hwreg.h"
+
+int board_init (void)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+//    unsigned char data;
+    unsigned long reg;
+
+    /* AHB Controller */
+    *((volatile ulong*) 0x1E600000)  = 0xAEED1A03;	/* unlock AHB controller */
+    *((volatile ulong*) 0x1E60008C) |= 0x01;		/* map DRAM to 0x00000000 */
+#ifdef CONFIG_PCI
+    *((volatile ulong*) 0x1E60008C) |= 0x30;		/* map PCI */
+#endif
+
+    /* Flash Controller */
+#ifdef CONFIG_FLASH_AST2050
+    *((volatile ulong*) 0x16000000) |= 0x00001c00;	/* enable Flash Write */
+#else
+# ifdef	CONFIG_FLASH_AST2300
+    *((volatile ulong*) 0x1e620000) |= 0x800f0000;	/* enable Flash Write */
+# else
+    *((volatile ulong*) 0x16000000) |= 0x00001ff1;	/* enable Flash Write */
+# endif
+#endif
+
+    /* SCU */
+    *((volatile ulong*) 0x1e6e2000) = 0x1688A8A8;	/* unlock SCU */
+    reg = *((volatile ulong*) 0x1e6e2008);
+    reg &= 0x1c0fffff;
+    reg |= 0x61800000;					/* PCLK  = HPLL/8 */
+#ifdef CONFIG_AST1070
+	reg |= 0x300000;				/* LHCLK = HPLL/8 */
+	reg |= 0x80000;					/* LPC Host Clock */
+#endif
+    *((volatile ulong*) 0x1e6e2008) = reg;
+
+    reg = *((volatile ulong*) 0x1e6e200c);		/* enable 2D Clk */
+    *((volatile ulong*) 0x1e6e200c) &= 0xFFFFFFFD;
+
+#ifdef ASUS_CONFIGURE_GPIO
+    /* Initialize GPIOs PA4, PH0, and PH1 */
+    *((volatile ulong*) AST_GPIO_BASE) |= 0x00000010;
+    reg = *((volatile ulong*) (AST_GPIO_BASE+0x20));
+    reg &= 0xfeffffff;
+    reg |= 0x02000000;
+    *((volatile ulong*) (AST_GPIO_BASE+0x20)) = reg;
+    *((volatile ulong*) (AST_GPIO_BASE+0x04)) |= 0x00000010;
+    *((volatile ulong*) (AST_GPIO_BASE+0x24)) |= 0x03000000;
+#endif
+
+#ifndef CONFIG_AST2050
+    /* enable wide screen. If your video driver does not support wide screen, don't
+     * enable this bit 0x1e6e2040 D[0]
+     */
+    reg = *((volatile ulong*) 0x1e6e2040);
+    *((volatile ulong*) 0x1e6e2040) |= 0x01;
+#endif
+
+#ifdef CONFIG_AST1070
+/*set VPPL1 */
+
+    *((volatile ulong*) 0x1e6e201c) = 0x6420;
+
+// set d2-pll & enable d2-pll D[21:20], D[4]
+    reg = *((volatile ulong*) 0x1e6e202c);
+    reg &= 0xffcfffef;
+    reg |= 0x00200010;
+    *((volatile ulong*) 0x1e6e202c) = reg;
+
+// set OSCCLK = VPLL1
+    *((volatile ulong*) 0x1e6e2010) = 0x8;
+
+// enable OSCCLK
+    reg = *((volatile ulong*) 0x1e6e202c);
+    reg &= 0xfffffffd;
+    reg |= 0x00000002;
+    *((volatile ulong*) 0x1e6e202c) = reg;
+
+// enable AST1050's LPC master
+    reg = *((volatile ulong*) 0x1e7890a0);
+    *((volatile ulong*) 0x1e7890a0) |= 0x11;
+#endif
+
+    /* arch number */
+    gd->bd->bi_arch_number = MACH_TYPE_ASPEED;
+
+    /* adress of boot parameters */
+    gd->bd->bi_boot_params = 0x40000100;
+
+    return 0;
+}
+
+int dram_init (void)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+
+    /* dram_init must store complete ramsize in gd->ram_size */
+    gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+
+    return 0;
+}
+
+/*
+SCU7C: Silicon Revision ID Register
+D[31:24]: Chip ID
+0: AST2050/AST2100/AST2150/AST2200/AST3000
+1: AST2300
+
+D[23:16] Silicon revision ID for AST2300 generation and later
+0: A0
+1: A1
+2: A2
+.
+.
+.
+FPGA revision starts from 0x80
+
+
+D[11:8] Bounding option
+
+D[7:0] Silicon revision ID for AST2050/AST2100 generation (for software compatible)
+0: A0
+1: A1
+2: A2
+3: A3
+.
+.
+FPGA revision starts from 0x08, 8~10 means A0, 11+ means A1, AST2300 should be assigned to 3
+*/
+int misc_init_r(void)
+{
+    unsigned int reg1, revision, chip_id;
+
+    /* Show H/W Version */
+    reg1 = (unsigned int) (*((ulong*) 0x1e6e207c));
+    chip_id = (reg1 & 0xff000000) >> 24;
+    revision = (reg1 & 0xff0000) >> 16;
+
+    puts ("H/W:   ");
+    if (chip_id == 1) {
+    	if (revision >= 0x80) {
+    		printf("AST2300 series FPGA Rev. %02x \n", revision);
+    	}
+    	else {
+    		printf("AST2300 series chip Rev. %02x \n", revision);
+    	}
+    }
+    else if (chip_id == 0) {
+	printf("AST2050/AST2150 series chip\n");
+    }
+
+#ifdef CONFIG_AST1070
+	puts ("C/C:   ");
+	revision = (unsigned int) (*((ulong*) 0x60002034));
+	printf("AST1070 ID [%08x] \n", revision);
+#endif
+
+#ifdef	CONFIG_PCI
+    pci_init ();
+#endif
+
+    if (getenv ("verify") == NULL) {
+	setenv ("verify", "n");
+    }
+    if (getenv ("eeprom") == NULL) {
+	setenv ("eeprom", "y");
+    }
+return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void aspeed_init_pci (struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+    aspeed_init_pci(&hose);
+}
+#endif
diff --git a/board/aspeed/ast2050/config.mk b/board/aspeed/ast2050/config.mk
new file mode 100644
index 0000000..328e108
--- /dev/null
+++ b/board/aspeed/ast2050/config.mk
@@ -0,0 +1,15 @@
+#  (c) 2017 Raptor Engineering, LLC
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# SPI flash is mapped to 0x00000000 initially
+CONFIG_SYS_TEXT_BASE = 0x00000000
diff --git a/board/aspeed/ast2050/crc32.c b/board/aspeed/ast2050/crc32.c
new file mode 100644
index 0000000..b11eee2
--- /dev/null
+++ b/board/aspeed/ast2050/crc32.c
@@ -0,0 +1,129 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <environment.h>
+
+#ifdef CONFIG_2SPIFLASH
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/* ========================================================================
+ * Table of CRC-32's of all single-byte values (made by make_aspeed_crc_table)
+ */
+unsigned long aspeed_crc_table[256] = {
+  0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+  0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+  0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+  0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+  0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+  0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+  0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+  0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+  0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+  0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+  0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+  0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+  0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+  0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+  0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+  0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+  0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+  0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+  0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+  0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+  0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+  0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+  0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+  0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+  0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+  0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+  0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+  0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+  0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+  0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+  0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+  0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+  0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+  0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+  0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+  0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+  0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+  0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+  0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+  0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+  0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+  0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+  0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+  0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+  0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+  0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+  0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+  0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+  0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+  0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+  0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+  0x2d02ef8dL
+};
+
+/* ========================================================================= */
+#define ASPEED_DO1(buf)  crc = aspeed_crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+#define ASPEED_DO2(buf)  ASPEED_DO1(buf); ASPEED_DO1(buf);
+#define ASPEED_DO4(buf)  ASPEED_DO2(buf); ASPEED_DO2(buf);
+#define ASPEED_DO8(buf)  ASPEED_DO4(buf); ASPEED_DO4(buf);
+
+/* ========================================================================= */
+unsigned long spi2_crc32(crc, buf, len)
+    unsigned long crc;
+    unsigned char *buf;
+    unsigned long len;
+{
+
+    size_t len1, len2;
+    char *s;
+
+    len1 = len2 = 0;
+    if ( (ulong)(buf) <= (flash_info[0].start[0] + flash_info[0].size) )
+        len1 = (flash_info[0].start[0] + flash_info[0].size) - (ulong)(buf);
+    
+    len1 = (len < len1) ? len:len1;
+    len2 = (len < len1) ? 0: (len - len1);
+
+    crc = crc ^ 0xffffffffL;
+    while (len1 >= 8)
+    {
+      ASPEED_DO8(buf);
+      len1 -= 8;
+    }
+    if (len1) do {
+      ASPEED_DO1(buf);
+    } while (--len1);
+    
+    //s = (char *) flash_info[1].start[0];
+    s= (char *) flash_make_addr (&flash_info[1], 0, 0);
+    while (len2 >= 8)
+    {
+      ASPEED_DO8(s);
+      len2 -= 8;
+    }
+    if (len2) do {
+      ASPEED_DO1(s);
+    } while (--len2);   
+
+    return crc ^ 0xffffffffL;
+    
+}
+
+#endif /* CONFIG_2SPIFLASH */
+
diff --git a/board/aspeed/ast2050/crt.c b/board/aspeed/ast2050/crt.c
new file mode 100644
index 0000000..c3cc82b
--- /dev/null
+++ b/board/aspeed/ast2050/crt.c
@@ -0,0 +1,324 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <common.h>
+#include <command.h>
+
+#include "type.h"
+#include "vesa.h"
+#include "vdef.h"
+#include "vfun.h"
+#include "vreg.h"
+#include "crt.h"
+
+ULONG AST3000DCLKTableV [] = {
+    0x00046515,     /* 00: VCLK25_175 */  
+    0x00047255,     /* 01: VCLK28_322 */
+    0x0004682a,     /* 02: VCLK31_5         */
+    0x0004672a,     /* 03: VCLK36          */
+    0x00046c50,     /* 04: VCLK40           */
+    0x00046842,     /* 05: VCLK49_5         */
+    0x00006c32,     /* 06: VCLK50           */
+    0x00006a2f,     /* 07: VCLK56_25        */
+    0x00006c41,     /* 08: VCLK65  */
+    0x00006832,     /* 09: VCLK75         */
+    0x0000672e,     /* 0A: VCLK78_75        */
+    0x0000683f,     /* 0B: VCLK94_5         */
+    0x00004824,     /* 0C: VCLK108          */
+	0x00004723,		/* 0D: VCLK119			*/
+    0x0000482d,     /* 0E: VCLK135          */
+	0x00004B37,		/* 0F: VCLK146_25		*/
+    0x0000472e,     /* 10: VCLK157_5        */
+    0x00004836,     /* 11: VCLK162          */
+
+};
+
+BOOL CheckDAC(int nCRTIndex)
+{
+	BYTE	btValue;	
+	BOOL	bValue;
+
+	BYTE btDeviceSelect;
+
+	switch (nCRTIndex)
+	{
+	case CRT_1:
+		btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT1;
+		break;
+	case CRT_2:
+		btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT2;
+		break;
+	default:
+		printf("CRTIndex is not 1 or 2");
+		return FALSE;
+		break;
+	}
+
+	//Enable all DAC's and set register 21h[0] = '0'
+	//DVIP and DVIL disable for DAC
+	SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_PM_REG, 0x00);
+
+	btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG);
+	btValue = btValue & 0xFE;
+	SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG, btValue);
+
+	//Set SENSE bit to 1
+	btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
+	btValue = btValue | 0x01;
+	SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
+
+	//Reset SENSE bit to 0
+	btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
+	btValue = btValue & 0xFE;
+	SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
+
+	bValue = (GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG) & CD_DACT) ? TRUE : FALSE;
+
+	return bValue;
+}
+
+VOID  SetCH7301C(ULONG	MMIOBase,
+				 int	nCRTIndex,
+                 int	inFreqRange,
+				 int	inOperating)
+{
+	BYTE btDeviceSelect;
+//	BYTE btValue;
+
+//#ifdef EVB_CLIENT
+	//output RGB doesn't need to set CH7301
+	//if (1 == inOperating)
+	//	return;
+//#endif
+
+	switch (nCRTIndex)
+	{
+	case CRT_1:
+		btDeviceSelect = 0xEA;
+
+		break;
+	case CRT_2:
+		btDeviceSelect = 0xEC;
+
+		break;
+	default:
+		printf("CRTIndex is not 1 or 2");
+		return;
+		break;
+	}
+
+	if (inFreqRange <= VCLK65)
+	{
+	  printf("ch7301: low f \n");
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x08);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x16);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0x60);
+	}
+	else
+	{
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x06);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x26);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0xA0);
+	}
+
+	switch (inOperating)
+	{
+	case 0:
+		//DVI is normal function
+		 SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0xC0);
+		 SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x47);
+		break;
+	case 1:
+		//RGB
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x48, 0x18);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0x0);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x56, 0x0);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x21, 0x9);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x48);
+		SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1C, 0x00);
+		break;
+	default:
+		break;
+	};
+}
+
+void SetASTModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
+{
+    ULONG    temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
+
+//  Access CRT Engine
+	//  SetPolarity
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, ((vModeTable[ModeIndex].HorPolarity << HOR_SYNC_SELECT_BIT) | (vModeTable[ModeIndex].VerPolarity << VER_SYNC_SELECT_BIT)), (HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK));
+
+#if CONFIG_AST3000
+	WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xc0);
+#else
+    //2100 is single edge
+	WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0x80);
+#endif    
+	//  Horizontal Timing
+	temp = 0;
+    temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[ModeIndex].HorizontalTotal - 1) << HOR_TOTAL_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG  + nCRTIndex*0x60, temp);
+
+    RetraceStart = vModeTable[ModeIndex].HorizontalTotal - vModeTable[ModeIndex].HBackPorch - vModeTable[ModeIndex].HSyncTime - vModeTable[ModeIndex].HLeftBorder - 1;
+    RetraceEnd = (RetraceStart + vModeTable[ModeIndex].HSyncTime);
+	temp = 0;
+    temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG  + nCRTIndex*0x60, temp);
+
+	//  Vertical Timing
+	temp = 0;
+    temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[ModeIndex].VerticalTotal - 1) << VER_TOTAL_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG  + nCRTIndex*0x60, temp);
+
+	temp = 0;
+    RetraceStart = vModeTable[ModeIndex].VerticalTotal - vModeTable[ModeIndex].VBackPorch - vModeTable[ModeIndex].VSyncTime - vModeTable[ModeIndex].VTopBorder - 1;
+    RetraceEnd = (RetraceStart + vModeTable[ModeIndex].VSyncTime);
+    temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG  + nCRTIndex*0x60, temp);
+
+	//  Set CRT Display Offset and Terminal Count
+    if (ColorDepth == RGB_565) {
+        bpp = 16;
+    }
+    else {
+        bpp = 32;
+    }
+
+    DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
+    TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
+    if (ColorDepth == YUV_444) {
+        TerminalCount = TerminalCount * 3 / 4;
+    }
+    if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
+        TerminalCount++;
+    }
+
+    WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, ((TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset));
+
+	//  Set Color Format
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
+
+	//  Set Threshold
+	temp = 0;
+    temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
+
+	WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
+}
+
+void SetASTCenter1024ModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
+{
+    ULONG    temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
+
+	//  Access CRT Engine
+	//  SetPolarity
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (HOR_NEGATIVE << HOR_SYNC_SELECT_BIT) | (VER_NEGATIVE << VER_SYNC_SELECT_BIT), HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK);
+
+	WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xC0);
+
+	//  Horizontal Timing
+	temp = 0;
+    temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[10].HorizontalTotal - 1) << HOR_TOTAL_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
+
+    RetraceStart = vModeTable[10].HorizontalTotal - vModeTable[10].HBackPorch - vModeTable[10].HSyncTime - vModeTable[10].HLeftBorder - 1;
+    RetraceStart = RetraceStart - (vModeTable[10].HorizontalActive - vModeTable[ModeIndex].HorizontalActive) / 2 - 1;
+    RetraceEnd = (RetraceStart + vModeTable[10].HSyncTime);
+	temp = 0;
+    temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
+
+	//  Vertical Timing
+	temp = 0;
+    temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[10].VerticalTotal - 1) << VER_TOTAL_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
+
+    RetraceStart = vModeTable[10].VerticalTotal - vModeTable[10].VBackPorch - vModeTable[10].VSyncTime - vModeTable[10].VTopBorder - 1;
+    RetraceStart = RetraceStart - (vModeTable[10].VerticalActive - vModeTable[ModeIndex].VerticalActive) / 2 - 1;
+    RetraceEnd = (RetraceStart + vModeTable[10].VSyncTime);
+    temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
+
+	//  Set CRT Display Offset and Terminal Count
+    if (ColorDepth == RGB_565) {
+        bpp = 16;
+    }
+    else {
+        bpp = 32;
+    }
+    DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
+    TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
+    if (ColorDepth == YUV_444) {
+        TerminalCount = TerminalCount * 3 / 4;
+    }
+    if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
+        TerminalCount++;
+    }
+
+    WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, (TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset);
+
+	//  Set Color Format
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
+
+	//  Set Threshold
+	temp = 0;
+    temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
+    WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
+    
+	// Set DCLK
+	WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
+
+}
+
+BOOL  ASTSetModeV (ULONG MMIOBase, int nCRTIndex, ULONG VGABaseAddr, USHORT Horizontal, USHORT Vertical, BYTE ColorFormat, BYTE CenterMode)
+{
+    BYTE    i/*, ModeIndex*/;
+//    BOOL	bDAC;	
+//    ULONG   ulTemp;
+
+    //  Access CRT Engine
+    //Enable CRT1 graph
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + 0x60*nCRTIndex, GRAPH_DISPLAY_ON, GRAPH_DISPLAY_MASK);
+    
+    //  Set CRT Display Start Address
+    WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_DISPLAY_ADDRESS + 0x60*nCRTIndex, VGABaseAddr, DISPLAY_ADDRESS_MASK);
+
+    for (i = 0; i < Mode60HZCount; i++) {
+        if ((vModeTable[i].HorizontalActive == Horizontal) && (vModeTable[i].VerticalActive == Vertical)) {
+
+//	    ModeIndex = i;
+
+            if (CenterMode != 1) {
+                SetASTModeTiming(MMIOBase, nCRTIndex, i, ColorFormat);
+            }
+            else {
+                SetASTCenter1024ModeTiming (MMIOBase, nCRTIndex, i, ColorFormat);
+            }
+
+            //use internal video out sigal and don't need use 7301
+            /*
+			bDAC = CheckDAC(nCRTIndex);
+            
+			SetCH7301C(0,
+				nCRTIndex,
+				vModeTable[ModeIndex].PixelClock,
+				bDAC);		//For RGB
+			*/	
+			return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
diff --git a/board/aspeed/ast2050/crt.h b/board/aspeed/ast2050/crt.h
new file mode 100644
index 0000000..2ad8f09
--- /dev/null
+++ b/board/aspeed/ast2050/crt.h
@@ -0,0 +1,123 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _CRT_H_
+#define _CRT_H_
+
+#ifdef Watcom
+#define		CRT_REMAP_OFFSET	0x10000
+#else
+#define		CRT_REMAP_OFFSET	0x0
+#endif
+
+/********************************************************/
+/*    CRT register                                      */
+/********************************************************/
+#define		CRT_BASE_OFFSET						0x6000+CRT_REMAP_OFFSET
+
+#define		CRT1_CONTROL_REG					0x00 + CRT_BASE_OFFSET
+	#define		GRAPH_DISPLAY_BIT				0
+	#define     GRAPH_DISPLAY_MASK				(1<<0)
+		#define		GRAPH_DISPLAY_ON			1
+		#define		GRAPH_DISPLAY_OFF			0
+    #define     FORMAT_SELECT_BIT               8
+    #define     FORMAT_SELECT_MASK              (3<<8)   
+	#define		HOR_SYNC_SELECT_BIT				16
+    #define		HOR_SYNC_SELECT_MASK			(1<<16)	
+		#define		HOR_NEGATIVE				1
+		#define		HOR_POSITIVE				0
+	#define		VER_SYNC_SELECT_BIT				17
+    #define		VER_SYNC_SELECT_MASK			(1<<17)	
+		#define		VER_NEGATIVE				1
+		#define		VER_POSITIVE				0
+
+#define		CRT1_CONTROL2_REG					0x04 + CRT_BASE_OFFSET
+        
+#define     CRT1_VIDEO_PLL_REG                  0x0C + CRT_BASE_OFFSET
+    #define     POST_DIV_BIT                    18
+    #define     POST_DIV_MASK                   3<<18
+        #define     DIV_1_1                     0
+        //#define     DIV_1_2                     1
+        #define     DIV_1_2                     2
+        #define     DIV_1_4                     3
+        
+#define     CRT1_HOR_TOTAL_END_REG              0x10 + CRT_BASE_OFFSET
+    #define     HOR_TOTAL_BIT                   0
+    #define     HOR_ENABLE_END_BIT              16
+
+#define     CRT1_HOR_RETRACE_REG                0x14 + CRT_BASE_OFFSET
+    #define     HOR_RETRACE_START_BIT           0
+    #define     HOR_RETRACE_END_BIT             16
+
+#define     CRT1_VER_TOTAL_END_REG              0x18 + CRT_BASE_OFFSET
+    #define     VER_TOTAL_BIT                   0
+    #define     VER_ENABLE_END_BIT              16
+
+#define     CRT1_VER_RETRACE_REG                0x1C + CRT_BASE_OFFSET
+    #define     VER_RETRACE_START_BIT           0
+    #define     VER_RETRACE_END_BIT             16
+
+#define     CRT1_DISPLAY_ADDRESS				0x20 + CRT_BASE_OFFSET
+	#define		DISPLAY_ADDRESS_MASK			0x0FFFFFFF
+
+#define     CRT1_DISPLAY_OFFSET                 0x24 + CRT_BASE_OFFSET
+    #define     DISPLAY_OFFSET_ALIGN            7 /* 8 byte alignment*/
+    #define     TERMINAL_COUNT_BIT              16    
+
+#define     CRT1_THRESHOLD_REG                  0x28 + CRT_BASE_OFFSET
+    #define     THRES_LOW_BIT                   0
+    #define     THRES_HIGHT_BIT                 8
+
+#define    CURSOR_POSITION                  0x30 + OFFSET
+#define    CURSOR_OFFSET                    0x34 + OFFSET
+#define    CURSOR_PATTERN                   0x38 + OFFSET
+#define    OSD_HORIZONTAL                   0x40 + OFFSET
+#define    OSD_VERTICAL                     0x44 + OFFSET
+#define    OSD_PATTERN                      0x48 + OFFSET
+#define    OSD_OFFSET                       0x4C + OFFSET
+#define    OSD_THRESHOLD                    0x50 + OFFSET
+
+//Ch7301c
+#define		DEVICE_ADDRESS_CH7301_CRT1	0xEA
+#define		DEVICE_ADDRESS_CH7301_CRT2	0xEC
+
+
+#define		DEVICE_SELECT_CH7301		0x3
+
+/* CH7301 Register Definition */
+#define     CH7301_CD_REG				0x20
+	#define     CD_DACT					0x0E
+	#define		CD_DVIT					1 << 5
+#define     CH7301_DC_REG				0x21
+#define     CH7301_PM_REG				0x49
+
+BOOL CheckHotPlug(int nCRTIndex);
+BOOL CheckDAC(int nCRTIndex);
+
+BOOL  ASTSetModeV (ULONG MMIOBase, 
+                int nCRTIndex, 
+                ULONG VGABaseAddr, 
+                USHORT Horizontal, 
+                USHORT Vertical, 
+                BYTE ColorFormat, 
+                BYTE CenterMode);
+                
+BOOL  SelCRTClock(ULONG MMIOBase,
+				  int	nCRTIndex,
+				  USHORT Horizontal, 
+				  USHORT Vertical);
+
+void DisableCRT(ULONG MMIOBase, int nCRTIndex);
+void ClearCRTWithBlack(ULONG ulCRTAddr, int iWidth, int iHeight);
+
+#endif /* _CRT_H_ */
+
diff --git a/board/aspeed/ast2050/flash.c b/board/aspeed/ast2050/flash.c
new file mode 100644
index 0000000..70de0f8
--- /dev/null
+++ b/board/aspeed/ast2050/flash.c
@@ -0,0 +1,1653 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 01/20/2004 - combined variants of original driver.
+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
+ * 01/27/2004 - Little endian support Ed Okerson
+ *
+ * Tested Architectures
+ * Port Width  Chip Width    # of banks	   Flash Chip  Board
+ * 32	       16	     1		   28F128J3    seranoa/eagle
+ * 64	       16	     1		   28F128J3    seranoa/falcon
+ */
+// (Sun) This CFI driver is written for fixed-width flash chips.
+// It was not designed for flexible 8-bit/16-bit chips, which are the norm.
+// When those chips are connected to a bus in 8-bit mode, the address wires
+// right-shifted by 1.
+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
+
+/* The DEBUG define must be before common to enable debugging */
+// (Sun) Changed to DEBUG_FLASH because flash debug()s are too numerous.
+// #define DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <environment.h>
+#ifdef	CONFIG_SYS_FLASH_CFI
+
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ *
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
+ * Table (ALT) to determine if protection is available
+ *
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#ifndef CONFIG_FLASH_BANKS_LIST
+#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
+#define AMD_CMD_WRITE_TO_BUFFER		0x25
+#define AMD_CMD_BUFFER_TO_FLASH		0x29
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+//FIXME: These 3 were also changed for 8-bit/16-bit flash chips.
+#define AMD_ADDR_ERASE_START		(0xAAA/info->portwidth)
+#define AMD_ADDR_START			(0xAAA/info->portwidth)
+#define AMD_ADDR_ACK			(0x555/info->portwidth)
+
+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
+#define FLASH_OFFSET_CFI		(0xAA/info->portwidth)
+#define FLASH_OFFSET_CFI_RESP		(0x20/info->portwidth)
+#define FLASH_OFFSET_CFI_RESP1		(0x22/info->portwidth)
+#define FLASH_OFFSET_CFI_RESP2		(0x24/info->portwidth)
+#define FLASH_OFFSET_PRIMARY_VENDOR	(0x26/info->portwidth)
+#define FLASH_OFFSET_WTOUT		(0x3E/info->portwidth)
+#define FLASH_OFFSET_WBTOUT		(0x40/info->portwidth)
+#define FLASH_OFFSET_ETOUT		(0x42/info->portwidth)
+#define FLASH_OFFSET_CETOUT		(0x44/info->portwidth)
+#define FLASH_OFFSET_WMAX_TOUT		(0x46/info->portwidth)
+#define FLASH_OFFSET_WBMAX_TOUT		(0x48/info->portwidth)
+#define FLASH_OFFSET_EMAX_TOUT		(0x4A/info->portwidth)
+#define FLASH_OFFSET_CEMAX_TOUT		(0x4C/info->portwidth)
+#define FLASH_OFFSET_SIZE		(0x4E/info->portwidth)
+#define FLASH_OFFSET_INTERFACE		(0x50/info->portwidth)
+#define FLASH_OFFSET_BUFFER_SIZE	(0x54/info->portwidth)
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	(0x58/info->portwidth)
+#define FLASH_OFFSET_ERASE_REGIONS	(0x5A/info->portwidth)
+#define FLASH_OFFSET_PROTECT		(0x02/info->portwidth)
+#define FLASH_OFFSET_USER_PROTECTION	(0x85/info->portwidth)
+#define FLASH_OFFSET_INTEL_PROTECTION	(0x81/info->portwidth)
+
+#define MAX_NUM_ERASE_REGIONS		4
+
+#define FLASH_MAN_CFI			0x01000000
+
+#define CFI_CMDSET_NONE		    0
+#define CFI_CMDSET_INTEL_EXTENDED   1
+#define CFI_CMDSET_AMD_STANDARD	    2
+#define CFI_CMDSET_INTEL_STANDARD   3
+#define CFI_CMDSET_AMD_EXTENDED	    4
+#define CFI_CMDSET_MITSU_STANDARD   256
+#define CFI_CMDSET_MITSU_EXTENDED   257
+#define CFI_CMDSET_SST		    258
+
+
+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
+# undef  FLASH_CMD_RESET
+# define FLASH_CMD_RESET                AMD_CMD_RESET /* use AMD-Reset instead */
+#endif
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+	unsigned long long ll;
+} cfiword_t;
+
+typedef union {
+	volatile unsigned char *cp;
+	volatile unsigned short *wp;
+	volatile unsigned long *lp;
+	volatile unsigned long long *llp;
+} cfiptr_t;
+
+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT];	/* FLASH chips info */
+#else
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];		/* FLASH chips info */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static void flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static void flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd, int noDebug);
+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static int flash_detect_cfi (flash_info_t * info);
+ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
+				    ulong tout, char *prompt);
+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector);				    
+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+static flash_info_t *flash_get_info(ulong base);
+#endif
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * Debug support
+ */
+#ifdef DEBUG_FLASH
+static void print_longlong (char *str, unsigned long long data)
+{
+	int i;
+	char *cp;
+
+	cp = (unsigned char *) &data;
+	for (i = 0; i < 8; i++)
+		sprintf (&str[i * 2], "%2.2x", *cp++);
+}
+#endif
+
+#if defined(DEBUG_FLASH)
+static void flash_printqry (flash_info_t * info, flash_sect_t sect)
+{
+	cfiptr_t cptr;
+	int x, y;
+
+	for (x = 0; x < 0x40; x += 16U / info->portwidth) {
+		cptr.cp =
+			flash_make_addr (info, sect,
+					 x + FLASH_OFFSET_CFI_RESP);
+		debug ("%p : ", cptr.cp);
+		for (y = 0; y < 16; y++) {
+			debug ("%2.2x ", cptr.cp[y]);
+		}
+		debug (" ");
+		for (y = 0; y < 16; y++) {
+			if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
+				debug ("%c", cptr.cp[y]);
+			} else {
+				debug (".");
+			}
+		}
+		debug ("\n");
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
+{
+	uchar *cp;
+
+	cp = flash_make_addr (info, 0, offset);
+#if defined(__LITTLE_ENDIAN)
+	return (cp[0]);
+#else
+	return (cp[info->portwidth - 1]);
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+#if 0
+static ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	uchar *addr;
+	ushort retval;
+
+#ifdef DEBUG_FLASH
+	int x;
+#endif
+	addr = flash_make_addr (info, sect, offset);
+
+#ifdef DEBUG_FLASH
+	debug ("ushort addr is at %p info->portwidth = %d\n", addr,
+	       info->portwidth);
+	for (x = 0; x < 2 * info->portwidth; x++) {
+		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN)
+	if (info->interface == FLASH_CFI_X8X16) {
+	    retval = (addr[0] | (addr[2] << 8));
+	} else {
+	    retval = (addr[0] | (addr[(info->portwidth)] << 8));
+	}
+#else
+	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
+		  addr[info->portwidth - 1]);
+#endif
+
+	debug ("retval = 0x%x\n", retval);
+	return retval;
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maximum
+ * port size word. Swap for ppc format.
+ */
+static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	uchar *addr;
+	ulong retval;
+#ifdef DEBUG_FLASH
+	int x;
+#endif
+#if 0
+	switch (info->interface) {
+	case FLASH_CFI_X8:
+	case FLASH_CFI_X16:
+	    break;
+	case FLASH_CFI_X8X16:
+	    offset <<= 1;
+	}
+#endif	
+	// flash_make_addr() multiplies offset by info->portwidth.
+	addr = flash_make_addr (info, sect, offset);
+
+#ifdef DEBUG_FLASH
+	debug ("long addr is at %p info->portwidth = %d\n", addr,
+	       info->portwidth);
+	for (x = 0; x < 4 * info->portwidth; x++) {
+		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN)
+	if (info->interface == FLASH_CFI_X8X16) {
+	    retval = (addr[0] | (addr[2] << 8) | (addr[4] << 16) | (addr[6] << 24));
+	} else {
+	    retval = (addr[0] | (addr[(info->portwidth)] << 8) |
+		      (addr[(2 * info->portwidth)] << 16) |
+		      (addr[(3 * info->portwidth)] << 24));
+	}
+#else
+	//FIXME: This undocumented code appears to match broken bus wiring.
+	retval = (addr[(2 * info->portwidth) - 1] << 24) |
+		(addr[(info->portwidth) - 1] << 16) |
+		(addr[(4 * info->portwidth) - 1] << 8) |
+		addr[(3 * info->portwidth) - 1];
+#endif
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size (bank_base[i], i);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+#ifndef CFG_FLASH_QUIET_TEST
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, flash_info[i].size, flash_info[i].size << 20);
+#endif /* CFG_FLASH_QUIET_TEST */
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_MONITOR_BASE,
+		       CONFIG_MONITOR_BASE + monitor_flash_len  - 1,
+		       flash_get_info(CONFIG_MONITOR_BASE));
+#endif
+
+	/* Environment protection ON by default */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		       flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	/* Redundant environment protection ON by default */
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
+		       flash_get_info(CONFIG_ENV_ADDR_REDUND));
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	flash_sect_t sect;
+        uchar ch;
+	uchar *addr;
+  
+	if (info->flash_id != FLASH_MAN_CFI) {
+		puts ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		puts ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		putc ('\n');
+	}
+
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			switch (info->vendor) {
+			case CFI_CMDSET_INTEL_STANDARD:
+			case CFI_CMDSET_INTEL_EXTENDED:
+				flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+				flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+				flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+				break;
+			case CFI_CMDSET_AMD_STANDARD:
+			case CFI_CMDSET_AMD_EXTENDED:
+				flash_unlock_seq (info, sect);
+				flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
+							AMD_CMD_ERASE_START);
+				flash_unlock_seq (info, sect);
+				flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
+				
+				/* toggle */
+	                        addr = flash_make_addr (info, sect, 0);				
+				do {
+				    ch = *(volatile uchar *)(addr);
+                                } while ( ((ch & 0x80) == 0) || (ch != 0xFF) );
+				break;
+			default:
+				debug ("Unkown flash vendor %d\n",
+				       info->vendor);
+				break;
+			}
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				putc ('.');
+		}
+	}
+	puts (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf ("CFI conformant FLASH (%d x %d)",
+		(info->portwidth << 3), (info->chipwidth << 3));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+		info->erase_blk_tout,
+		info->write_tout,
+		info->buffer_write_tout,
+		info->buffer_size);
+
+	puts ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else	/* ! CFG_FLASH_EMPTY_INFO */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	putc ('\n');
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	unsigned char pat[] = {'|', '-', '/', '\\'};
+       	int patcnt = 0;
+	int buffered_size;
+#endif
+	/* get lower aligned address */
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte (info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+	/* handle the aligned part */
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	buffered_size = (info->portwidth / info->chipwidth);
+	buffered_size *= info->buffer_size;
+	while (cnt >= info->portwidth) {
+		/* Show processing */
+		if ((++patcnt % 256) == 0)
+		    printf("%c\b", pat[(patcnt / 256) & 0x03]);
+
+		i = buffered_size > cnt ? cnt : buffered_size;
+		if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
+			return rc;
+		i -= i & (info->portwidth - 1);
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte (info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte (info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte (info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword (info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#ifdef CFG_FLASH_PROTECTION
+
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check (info, sector, info->erase_blk_tout,
+				      prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			flash_sect_t i;
+
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect (info, i, 1);
+			}
+		}
+	}
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ * flash_read_user_serial - read the OneTimeProgramming cells
+ */
+void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
+			     int len)
+{
+	uchar *src;
+	uchar *dst;
+
+	dst = buffer;
+	src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
+	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
+	memcpy (dst, src + offset, len);
+	flash_write_cmd (info, 0, 0, info->cmd_reset);
+}
+
+/*
+ * flash_read_factory_serial - read the device Id from the protection area
+ */
+void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
+				int len)
+{
+	uchar *src;
+
+	src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
+	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
+	memcpy (buffer, src + offset, len);
+	flash_write_cmd (info, 0, 0, info->cmd_reset);
+}
+
+#endif /* CFG_FLASH_PROTECTION */
+
+/*
+ * flash_is_busy - check to see if the flash is busy
+ * This routine checks the status of the chip and returns true if the chip is busy
+ */
+static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
+{
+	int retval;
+
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_STANDARD:
+	case CFI_CMDSET_INTEL_EXTENDED:
+		retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
+		break;
+	case CFI_CMDSET_AMD_STANDARD:
+	case CFI_CMDSET_AMD_EXTENDED:
+		retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
+		break;
+	default:
+		retval = 0;
+	}
+#ifdef DEBUG_FLASH
+	if (retval)
+	    debug ("flash_is_busy: %d\n", retval);
+#endif
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check (flash_info_t * info, flash_sect_t sector,
+			       ulong tout, char *prompt)
+{
+	ulong start, now;
+
+	/* Wait for command completion */
+	// (Sun) Fix order of checking time so it works when the CPU is very
+	// slow, e.g., single-stepping or emulation.
+	start = get_timer (0);
+	while (now = get_timer(start),
+	       flash_is_busy (info, sector))
+	{
+		if (now > info->erase_blk_tout) {
+			printf ("Flash %s timeout at address %lx data %lx\n",
+				prompt, info->start[sector],
+				flash_read_long (info, sector, 0));
+			flash_write_cmd (info, sector, 0, info->cmd_reset);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
+				    ulong tout, char *prompt)
+{
+	int retcode;
+
+	retcode = flash_status_check (info, sector, tout, prompt);
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_EXTENDED:
+	case CFI_CMDSET_INTEL_STANDARD:
+		if ((retcode != ERR_OK)
+		    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+			retcode = ERR_INVAL;
+			printf ("Flash %s error at address %lx\n", prompt,
+				info->start[sector]);
+			if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+				puts ("Command Sequence Error.\n");
+			} else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
+				puts ("Block Erase Error.\n");
+				retcode = ERR_NOT_ERASED;
+			} else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
+				puts ("Locking Error\n");
+			}
+			if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
+				puts ("Block locked.\n");
+				retcode = ERR_PROTECTED;
+			}
+			if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
+				puts ("Vpp Low Error.\n");
+		}
+		flash_write_cmd (info, sector, 0, info->cmd_reset);
+		break;
+	default:
+		break;
+	}
+	return retcode;
+}
+
+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector)
+{
+     flash_write_cmd (info, sector, 0xaaa, 0xaa);
+     flash_write_cmd (info, sector, 0x555, 0x55);
+     flash_write_cmd (info, sector, 0xaaa, 0xf0);    	
+}	
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+{
+#if defined(__LITTLE_ENDIAN)
+	unsigned short	w;
+	unsigned int	l;
+	unsigned long long ll;
+#endif
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+#if defined(__LITTLE_ENDIAN)
+		w = c;
+		w <<= 8;
+		cword->w = (cword->w >> 8) | w;
+#else
+		cword->w = (cword->w << 8) | c;
+#endif
+		break;
+	case FLASH_CFI_32BIT:
+#if defined(__LITTLE_ENDIAN)
+		l = c;
+		l <<= 24;
+		cword->l = (cword->l >> 8) | l;
+#else
+		cword->l = (cword->l << 8) | c;
+#endif
+		break;
+	case FLASH_CFI_64BIT:
+#if defined(__LITTLE_ENDIAN)
+		ll = c;
+		ll <<= 56;
+		cword->ll = (cword->ll >> 8) | ll;
+#else
+		cword->ll = (cword->ll << 8) | c;
+#endif
+		break;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *) cmdbuf;
+
+#if defined(__LITTLE_ENDIAN)
+	for (i = info->portwidth; i > 0; i--)
+#else
+	for (i = 1; i <= info->portwidth; i++)
+#endif
+		*cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void
+flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset,
+		 uchar cmd)
+{
+#ifdef DEBUG_FLASH
+    const int noDebug = 0;
+#else
+    const int noDebug = 1;
+#endif
+    return flash_write_cmd_int(info, sect, offset, cmd, noDebug);
+}
+static void
+flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset,
+		       uchar cmd)
+{
+    return flash_write_cmd_int(info, sect, offset, cmd, 1);
+}
+
+static void
+flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset,
+		     uchar cmd, int noDebug)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+
+	addr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		if (noDebug == 0)
+		debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
+		       cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		if (noDebug == 0)
+		debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
+		       cmd, cword.w,
+		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		if (noDebug == 0)
+		debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
+		       cmd, cword.l,
+		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		*addr.lp = cword.l;
+		break;
+	case FLASH_CFI_64BIT:
+#ifdef DEBUG_FLASH
+		if (noDebug == 0)
+		{
+			char str[20];
+
+			print_longlong (str, cword.ll);
+
+			debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
+			       addr.llp, cmd, str,
+			       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		}
+#endif
+		*addr.llp = cword.ll;
+		break;
+	}
+}
+
+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
+{
+	flash_write_cmd_nodbg (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
+	flash_write_cmd_nodbg (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+#ifdef DEBUG_FLASH
+	const int dbg = 1;
+#else
+	const int dbg = 0;
+#endif
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+
+	if (dbg)
+	    debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		if (dbg)
+		    debug ("is= %x %x\n", cptr.cp[0], cword.c);
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		if (dbg)
+		    debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		if (dbg)
+		    debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+#ifdef DEBUG_FLASH
+		{
+			char str1[20];
+			char str2[20];
+
+			print_longlong (str1, cptr.llp[0]);
+			print_longlong (str2, cword.ll);
+			debug ("is= %s %s\n", str1, str2);
+		}
+#endif
+		retval = (cptr.llp[0] == cword.ll);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+		retval = ((cptr.llp[0] & cword.ll) == cword.ll);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
+		break;
+	case FLASH_CFI_64BIT:
+		retval = ((cptr.llp[0] & cword.ll) !=
+			  (cptr.llp[0] & cword.ll));
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi (flash_info_t * info)
+{
+        ulong data;
+        	
+	debug ("flash_detect_cfi()... ");
+
+#if     defined(CONFIG_FLASH_AST2300)
+        data = *(ulong *)(0x1e6e2070);		/* hardware traping */
+        if (data & 0x10)			/* D[4]: 0/1 (8/16) */
+            info->portwidth = FLASH_CFI_16BIT;
+        else
+            info->portwidth = FLASH_CFI_8BIT;            
+#else
+        info->portwidth = FLASH_CFI_8BIT;
+#endif
+
+	{     	
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    //FIXME: Next 3 lines were changed for 8-bit/16-bit flash chips.
+			    && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP1, 'R')
+			    && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP2, 'Y')) {
+				info->interface = flash_read_uchar (info, FLASH_OFFSET_INTERFACE);
+				debug ("device interface is %d\n",
+				       info->interface);
+				debug ("found port %d chip %d ",
+				       info->portwidth, info->chipwidth);
+				debug ("port %d bits chip %d bits\n",
+				       info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+				       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+				return 1;
+			}
+		}
+	}
+	debug ("not found\n");
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	flash_sect_t sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+
+	if (flash_detect_cfi (info)) {
+		info->vendor = flash_read_uchar (info, FLASH_OFFSET_PRIMARY_VENDOR);
+#if defined(DEBUG_FLASH)
+		flash_printqry (info, 0);
+#endif
+		switch (info->vendor) {
+		case CFI_CMDSET_INTEL_STANDARD:
+		case CFI_CMDSET_INTEL_EXTENDED:
+		default:
+			info->cmd_reset = FLASH_CMD_RESET;
+			break;
+		case CFI_CMDSET_AMD_STANDARD:
+		case CFI_CMDSET_AMD_EXTENDED:
+			info->cmd_reset = AMD_CMD_RESET;
+			break;
+		}
+
+		debugX(2, "manufacturer is %d\n", info->vendor);
+		size_ratio = info->portwidth / info->chipwidth;
+		/* if the chip is x8/x16 reduce the ratio by half */
+#if 0
+		if ((info->interface == FLASH_CFI_X8X16)
+		    && (info->chipwidth == FLASH_CFI_BY8)) {
+			size_ratio >>= 1;
+		}
+#endif
+		num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+		debugX(2, "size_ratio %d port %d bits chip %d bits\n",
+		       size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		debugX(2, "found %d erase regions\n", num_erase_regions);
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > MAX_NUM_ERASE_REGIONS) {
+				printf ("%d erase regions found, only %d used\n",
+					num_erase_regions, MAX_NUM_ERASE_REGIONS);
+				break;
+			}
+			// CFI Erase Block Region Information:
+			// Bits[31:16] = sect_size/256, 0 means 128-byte
+			// Bits[15:0]  = num_sectors - 1
+			tmp = flash_read_long(info, 0,
+					      FLASH_OFFSET_ERASE_REGIONS + i * 4);
+			debug("CFI erase block region info[%d]: 0x%08x, ",
+			      i, tmp);
+			erase_region_count = (tmp & 0xffff) + 1;
+			tmp >>= 16;
+			erase_region_size = (tmp ? tmp * 256 : 128);
+			debug ("erase_region_count=%d erase_region_size=%d\n",
+				erase_region_count, erase_region_size);
+#if 0
+                        erase_region_size  = CFG_FLASH_SECTOR_SIZE;	// Commented out
+                        erase_region_count = CFG_FLASH_SECTOR_COUNT;	// Commented out
+#endif
+			if (sect_cnt + erase_region_count > CONFIG_SYS_MAX_FLASH_SECT) {
+			    printf("Warning: Erase region %d adds too many flash sectors"
+				   " %d+%d; reducing to fit total limit of %d\n",
+				   i, sect_cnt, erase_region_count, CONFIG_SYS_MAX_FLASH_SECT);
+			    erase_region_count = CONFIG_SYS_MAX_FLASH_SECT - sect_cnt;
+			}
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+
+				/*
+				 * Only read protection status from supported devices (intel...)
+				 */
+				switch (info->vendor) {
+				case CFI_CMDSET_INTEL_EXTENDED:
+				case CFI_CMDSET_INTEL_STANDARD:
+					info->protect[sect_cnt] =
+						flash_isset (info, sect_cnt,
+							     FLASH_OFFSET_PROTECT,
+							     FLASH_STATUS_PROTECT);
+					break;
+				default:
+					info->protect[sect_cnt] = 0; /* default: not protected */
+				}
+
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		// info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
+		// Use only the sectors that fit within the flash_info array size.
+		info->size = sector - base;
+		printf("Flash bank %d at %08x has 0x%x bytes in %d sectors"
+		       " (chipSize 1<<%d, size_ratio %d).\n",
+		       banknum, base, info->size, info->sector_count,
+		       flash_read_uchar(info, FLASH_OFFSET_SIZE), size_ratio);
+
+		info->buffer_size = (1 << flash_read_uchar (info, FLASH_OFFSET_BUFFER_SIZE));		
+		/* Limit the buffer size to 32bytes to meet most of AMD-styles flash's minimum requirement */
+		if (info->buffer_size > 32)
+		    info->buffer_size = 32;    
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
+		info->flash_id = FLASH_MAN_CFI;
+#if 0
+		if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
+			info->portwidth >>= 1;	/* XXX - Need to test on x8/x16 in parallel. */
+		}
+#endif
+	}
+
+	flash_write_cmd (info, 0, 0, info->cmd_reset);
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+				cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr (info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+		flag = ((cptr.llp[0] & cword.ll) == cword.ll);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_EXTENDED:
+	case CFI_CMDSET_INTEL_STANDARD:
+		flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+		flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_WRITE);
+		break;
+	case CFI_CMDSET_AMD_EXTENDED:
+	case CFI_CMDSET_AMD_STANDARD:
+		flash_unlock_seq (info, 0);
+		flash_write_cmd_nodbg (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
+		break;
+	}
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	case FLASH_CFI_64BIT:
+		cptr.llp[0] = cword.ll;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	return flash_full_status_check (info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static flash_sect_t find_sector (flash_info_t * info, ulong addr)
+{
+	flash_sect_t sector;
+
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+				  int len)
+{
+	flash_sect_t sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+/* Add AMD write buffer mode support, ycchen@102006 */
+#if 0
+	/* buffered writes in the AMD chip set is not supported yet */
+	if((info->vendor ==  CFI_CMDSET_AMD_STANDARD) ||
+		(info->vendor == CFI_CMDSET_AMD_EXTENDED))
+		return ERR_INVAL;
+#endif
+	if((info->vendor ==  CFI_CMDSET_AMD_STANDARD) ||
+		(info->vendor == CFI_CMDSET_AMD_EXTENDED))
+	{
+		retcode = flash_write_cfibuffer_amd(info, dest, cp, len);
+                return retcode;
+        }
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector (info, dest);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode =
+	     flash_status_check (info, sector, info->buffer_write_tout,
+				 "write to buffer")) == ERR_OK) {
+		/* reduce the number of loops by the width of the port	*/
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		case FLASH_CFI_64BIT:
+			cnt = len >> 3;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			case FLASH_CFI_64BIT:
+				*dst.llp++ = *src.llp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd (info, sector, 0,
+				 FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+			flash_full_status_check (info, sector,
+						 info->buffer_write_tout,
+						 "buffer write");
+	}
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+
+
+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp,
+				  int len)
+{
+	flash_sect_t sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+	volatile cfiword_t tmpsrc, tmpdst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector (info, dest);
+	flash_unlock_seq (info, 0);
+	if ((retcode =
+	     flash_status_check (info, sector, info->buffer_write_tout,
+				 "write to buffer")) == ERR_OK) {
+		/* reduce the number of loops by the width of the port	*/
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			*dst.cp = (uchar) (AMD_CMD_WRITE_TO_BUFFER);
+			*dst.cp = (uchar) (cnt -1);
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			*dst.wp = (unsigned short) (AMD_CMD_WRITE_TO_BUFFER);
+			*dst.wp = (unsigned short) (cnt -1);
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			*dst.lp = (unsigned long) (AMD_CMD_WRITE_TO_BUFFER);
+			*dst.lp = (unsigned long) (cnt -1);
+			break;
+		case FLASH_CFI_64BIT:
+			cnt = len >> 3;
+			*dst.llp = (unsigned long long) (AMD_CMD_WRITE_TO_BUFFER);
+			*dst.llp = (unsigned long long) (cnt -1);
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			case FLASH_CFI_64BIT:
+				*dst.llp++ = *src.llp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}				
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+		        src.cp--;
+		        dst.cp--;
+			*dst.cp = (unsigned char) (AMD_CMD_BUFFER_TO_FLASH);
+		        tmpsrc.c = *src.cp & 0x80;
+		        
+		        do {
+		            tmpdst.c = *(volatile uchar *)(dst.cp);		        
+		        	
+		            if (tmpdst.c & 0x20) {	/* toggle DQ5 */
+		                 tmpdst.c = *(volatile uchar *)(dst.cp);		        
+		                 if ((tmpdst.c & 0x80) != tmpsrc.c)
+		                 {
+		                     printf("program error occurred\n");
+			             flash_write_cmd (info, sector, 0, info->cmd_reset);		            
+			             return ERR_PROG_ERROR;			             
+			         }    
+		            }
+		            else if (tmpdst.c & 0x02) {	/* toggle DQ1 */
+		                 tmpdst.c = *(volatile uchar *)(dst.cp);		        
+		                 if ((tmpdst.c & 0x80) != tmpsrc.c)
+		                 {
+		                     printf("write buffer error occurred \n");
+		                     write_buffer_abort_reset(info, sector);
+			             return ERR_PROG_ERROR;			             
+			         } 		            
+		            }	
+		            		                	
+		        } while ((tmpdst.c & 0x80) != tmpsrc.c);
+		        			        
+			break;
+		case FLASH_CFI_16BIT:
+		        src.wp--;
+		        dst.wp--;
+			*dst.wp = (unsigned short) (AMD_CMD_BUFFER_TO_FLASH);
+		        tmpsrc.w = *src.wp & 0x80;
+
+		        do {
+		            tmpdst.w = *(volatile short *)(dst.wp);		        
+		        	
+		            if (tmpdst.w & 0x20) {	/* toggle DQ5 */
+		                 tmpdst.w = *(volatile ushort *)(dst.wp);		        
+		                 if ((tmpdst.w & 0x80) != tmpsrc.w)
+		                 {
+		                     printf("program error occurred\n");
+			             flash_write_cmd (info, sector, 0, info->cmd_reset);		            
+			             return ERR_PROG_ERROR;			             
+			         }    
+		            }
+		            else if (tmpdst.w & 0x02) {	/* toggle DQ1 */
+		                 tmpdst.w = *(volatile ushort *)(dst.wp);		        
+		                 if ((tmpdst.w & 0x80) != tmpsrc.w)
+		                 {
+		                     printf("write buffer error occurred \n");
+		                     write_buffer_abort_reset(info, sector);
+			             return ERR_PROG_ERROR;			             
+			         } 		            
+		            }	
+		            		                	
+		        } while ((tmpdst.w & 0x80) != tmpsrc.w);
+		        
+			break;
+		case FLASH_CFI_32BIT:
+		        src.lp--;
+		        dst.lp--;
+			*dst.lp = (unsigned long) (AMD_CMD_BUFFER_TO_FLASH);
+		        tmpsrc.l = *src.lp & 0x80;
+		        
+		        do {
+		            tmpdst.l = *(volatile ulong *)(dst.lp);		        
+		        	
+		            if (tmpdst.l & 0x20) {	/* toggle DQ5 */
+		                 tmpdst.l = *(volatile ulong *)(dst.lp);		        
+		                 if ((tmpdst.l & 0x80) != tmpsrc.l)
+		                 {
+		                     printf("program error occurred\n");
+			             flash_write_cmd (info, sector, 0, info->cmd_reset);		            
+			             return ERR_PROG_ERROR;			             
+			         }    
+		            }
+		            else if (tmpdst.l & 0x02) {	/* toggle DQ1 */
+		                 tmpdst.l = *(volatile ulong *)(dst.lp);		        
+		                 if ((tmpdst.l & 0x80) != tmpsrc.l)
+		                 {
+		                     printf("write buffer error occurred \n");
+		                     write_buffer_abort_reset(info, sector);
+			             return ERR_PROG_ERROR;			             
+			         } 		            
+		            }	
+		            		                	
+		        } while ((tmpdst.l & 0x80) != tmpsrc.l);
+		        
+			break;
+		case FLASH_CFI_64BIT:
+		        src.llp--;
+		        dst.llp--;
+			*dst.llp = (unsigned long long) (AMD_CMD_BUFFER_TO_FLASH);
+		        tmpsrc.ll = *src.llp & 0x80;
+		        
+		        do {
+		            tmpdst.ll = *(volatile unsigned long long *)(dst.llp);		        
+		        	
+		            if (tmpdst.ll & 0x20) {	/* toggle DQ5 */
+		                 tmpdst.ll = *(volatile unsigned long long *)(dst.llp);		        
+		                 if ((tmpdst.ll & 0x80) != tmpsrc.ll)
+		                 {
+		                     printf("program error occurred\n");
+			             flash_write_cmd (info, sector, 0, info->cmd_reset);		            
+			             return ERR_PROG_ERROR;			             
+			         }    
+		            }
+		            else if (tmpdst.ll & 0x02) {	/* toggle DQ1 */
+		                 tmpdst.ll = *(volatile unsigned long long *)(dst.llp);		        
+		                 if ((tmpdst.ll & 0x80) != tmpsrc.ll)
+		                 {
+		                     printf("write buffer error occurred \n");
+		                     write_buffer_abort_reset(info, sector);
+			             return ERR_PROG_ERROR;			             
+			         } 		            
+		            }	
+		            		                	
+		        } while ((tmpdst.ll & 0x80) != tmpsrc.ll);
+		        
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+
+		retcode =
+			flash_full_status_check (info, sector,
+						 info->buffer_write_tout,
+						 "buffer write");
+	}
+
+	return retcode;
+}
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#ifdef	CONFIG_FLASH_AST2300_DMA
+#define STCBaseAddress			0x1e620000
+
+/* for DMA */
+#define REG_FLASH_INTERRUPT_STATUS	0x08
+#define REG_FLASH_DMA_CONTROL		0x80
+#define REG_FLASH_DMA_FLASH_BASE	0x84
+#define REG_FLASH_DMA_DRAM_BASE		0x88
+#define REG_FLASH_DMA_LENGTH		0x8c
+
+#define FLASH_STATUS_DMA_BUSY		0x0000
+#define FLASH_STATUS_DMA_READY		0x0800
+#define FLASH_STATUS_DMA_CLEAR		0x0800
+
+#define FLASH_DMA_ENABLE		0x01
+
+void * memmove_dma(void * dest,const void *src,size_t count)
+{
+	ulong count_align, poll_time, data;
+	
+	count_align = (count + 3) & 0xFFFFFFFC;	/* 4-bytes align */
+        poll_time = 100;			/* set 100 us as default */
+
+	*(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
+	
+	*(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
+	*(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
+	*(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
+        udelay(10);
+	*(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
+	
+	/* wait poll */
+	do {
+	    udelay(poll_time);	
+	    data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
+	} while (!(data & FLASH_STATUS_DMA_READY));
+	
+	/* clear status */
+	*(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
+}	
+#endif
+#endif /* CFG_FLASH_CFI */
diff --git a/board/aspeed/ast2050/flash_spi.c b/board/aspeed/ast2050/flash_spi.c
new file mode 100644
index 0000000..8eda064
--- /dev/null
+++ b/board/aspeed/ast2050/flash_spi.c
@@ -0,0 +1,836 @@
+/*
+ * (C) Copyright 2002-2004
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Modified to work with AMD flashes
+ *
+ * Copyright (C) 2004
+ * Ed Okerson
+ * Modified to work with little-endian systems.
+ *
+ * Copyright (C) 2017 Raptor Engineering, LLC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 01/20/2004 - combined variants of original driver.
+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
+ * 01/27/2004 - Little endian support Ed Okerson
+ *
+ * Tested Architectures
+ * Port Width  Chip Width    # of banks	   Flash Chip  Board
+ * 32	       16	     1		   28F128J3    seranoa/eagle
+ * 64	       16	     1		   28F128J3    seranoa/falcon
+ *
+ */
+
+/* The DEBUG define must be before common to enable debugging */
+/* #define DEBUG	*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <environment.h>
+
+#ifdef CONFIG_FLASH_SPI
+
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ *
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
+ * Table (ALT) to determine if protection is available
+ *
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#ifndef CONFIG_FLASH_BANKS_LIST
+#define CONFIG_FLASH_BANKS_LIST { CONFIG_FLASH_BASE }
+#endif
+
+/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];	/* FLASH chips info */
+#else
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];		/* FLASH chips info */
+#endif
+
+/* Support Flash ID */
+#define STM25P64		0x172020
+#define STM25P128		0x182020
+#define S25FL128P		0x182001
+#define S25FL064A		0x160201
+#define MX25L12805D	    0x1820c2
+
+#define W25X16	      0x1530ef
+#define W25X32	      0x1630ef
+#define W25X64	      0x1730ef
+
+/* SPI Define */
+#define STCBaseAddress		0x16000000
+#define SPICtrlRegOffset	0x0C
+
+#define CMD_MASK		0xFFFFFFF8
+
+#define NORMALREAD		0x00
+#define	FASTREAD		0x01
+#define NORMALWRITE		0x02
+#define USERMODE		0x03
+
+#define CE_LOW			0x00
+#define CE_HIGH			0x04
+
+#define BufferSize		256
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+typedef unsigned long flash_sect_t;
+
+static void reset_flash (flash_info_t * info);
+static void enable_write (flash_info_t * info);
+static void write_status_register (flash_info_t * info, uchar data);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len);
+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_FLASH_BASE)
+static flash_info_t *flash_get_info(ulong base);
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * 1)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
+{
+	uchar *cp;
+
+	cp = flash_make_addr (info, 0, offset);
+#if defined(__LITTLE_ENDIAN)
+	return (cp[0]);
+#else
+	return (cp[1 - 1]);
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	uchar *addr;
+	ushort retval;
+
+#ifdef DEBUG
+	int x;
+#endif
+	addr = flash_make_addr (info, sect, offset);
+
+#ifdef DEBUG
+	debug ("ushort addr is at %p 1 = %d\n", addr,
+	       1);
+	for (x = 0; x < 2 * 1; x++) {
+		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN)
+	retval = ((addr[(1)] << 8) | addr[0]);
+#else
+	retval = ((addr[(2 * 1) - 1] << 8) |
+		  addr[1 - 1]);
+#endif
+
+	debug ("retval = 0x%x\n", retval);
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+	uchar *addr;
+	ulong retval;
+
+#ifdef DEBUG
+	int x;
+#endif
+	addr = flash_make_addr (info, sect, offset);
+
+#ifdef DEBUG
+	debug ("long addr is at %p 1 = %d\n", addr,
+	       1);
+	for (x = 0; x < 4 * 1; x++) {
+		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN)
+	retval = (addr[0] << 16) | (addr[(1)] << 24) |
+		(addr[(2 * 1)]) | (addr[(3 * 1)] << 8);
+#else
+	retval = (addr[(2 * 1) - 1] << 24) |
+		(addr[(1) - 1] << 16) |
+		(addr[(4 * 1) - 1] << 8) |
+		addr[(3 * 1) - 1];
+#endif
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void reset_flash (flash_info_t * info)
+{
+	ulong ulCtrlData;
+
+	ulCtrlData  = (0x0b0000) | (info->tCK_Read << 8) | (info->dummybyte << 6);
+	ulCtrlData |= CE_HIGH | FASTREAD;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+}
+	
+static void enable_write (flash_info_t * info)
+{
+	ulong base;
+	ulong ulCtrlData;
+	uchar jReg;
+
+	base = info->start[0];
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x06);
+	udelay(10);
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x05);
+	udelay(10);
+	do {
+	    jReg = *(volatile uchar *) (base);
+	} while (!(jReg & 0x02));		  	
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+
+}
+	
+static void write_status_register (flash_info_t * info, uchar data)
+{
+	ulong base;
+	ulong ulCtrlData;
+	uchar jReg;
+
+	base = info->start[0];
+
+	enable_write (info);
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x01);
+	udelay(10);
+	*(uchar *) (base) = (uchar) (data);
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+
+/*
+	ulCtrlData = CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x05);
+	udelay(10);
+	do {
+	    jReg = *(volatile uchar *) (base);
+	} while ((jReg & 0x02));		  	
+	ulCtrlData = CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+*/
+	ulCtrlData = CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x05);
+	udelay(10);
+	do {
+	    jReg = *(volatile uchar *) (base);
+	} while ((jReg & 0x01));		  	
+	ulCtrlData = CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+
+}
+
+/*
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int j;
+	unsigned long sector;
+	int erase_region_size;
+	ulong ulCtrlData;
+	int usID;
+	ulong cpuclk, div, reg;
+	ulong WriteClk, EraseClk, ReadClk;
+
+	info->start[0] = base;
+	cpuclk = 266;
+	erase_region_size  = 0x10000;
+	WriteClk = 40;
+	EraseClk = 20;
+	ReadClk  = 40;
+
+	/* Get Flash ID */
+	ulCtrlData  = *(ulong *) (STCBaseAddress + SPICtrlRegOffset) & CMD_MASK;
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x9F);
+	udelay(10);
+	usID = *(int *) (base) & 0xFFFFFF;
+	ulCtrlData  = *(ulong *) (STCBaseAddress + SPICtrlRegOffset) & CMD_MASK;
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	info->flash_id = usID;
+
+	printf("SPI Flash ID: %x \n", usID);
+
+	switch (info->flash_id)
+	{
+	case STM25P64:
+	    info->sector_count = 128;
+	    info->size = 0x800000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+	    WriteClk = 40;
+	    EraseClk = 20;
+	    ReadClk  = 40;
+	    break;
+	case STM25P128:
+	    info->sector_count = 64;
+	    info->size = 0x1000000;
+	    erase_region_size  = 0x40000;
+	    info->dummybyte = 1;
+	    WriteClk = 50;
+	    EraseClk = 20;
+	    ReadClk  = 50;
+	    break;
+	case S25FL128P:
+	    info->sector_count = 256;
+	    info->size = 0x1000000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+	    WriteClk = 100;
+	    EraseClk = 40;
+	    ReadClk  = 100;
+	    break;
+	case S25FL064A:
+	    info->sector_count = 128;
+	    info->size = 0x800000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+	    WriteClk = 50;
+	    EraseClk = 25;
+	    ReadClk  = 50;
+	    break;
+
+	case W25X16:
+	   info->sector_count = 32;
+	    info->size = 0x200000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+	    WriteClk = 50;
+	    EraseClk = 25;
+	    ReadClk  = 50;
+	    break;
+	case W25X32:
+	   info->sector_count = 64;
+	    info->size = 0x400000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+		  WriteClk = 50;
+	    EraseClk = 25;
+	    ReadClk  = 50;
+	    break;
+	case W25X64:
+	   info->sector_count = 128;
+	    info->size = 0x800000;		
+	    erase_region_size  = 0x10000;
+	    info->dummybyte = 1;
+		  WriteClk = 50;
+	    EraseClk = 25;
+	    ReadClk  = 50;
+	    break;
+	case MX25L12805D:
+	    info->sector_count = 256;
+	    info->size = 0x1000000;
+	    erase_region_size = 0x10000;
+	    info->dummybyte = 1;
+	    WriteClk = 50;
+	    EraseClk = 33;
+	    ReadClk  = 50;
+	    break;
+
+	default:
+	    printf("Can't support this SPI Flash!! \n");
+	    break;
+	}
+			
+	debug ("erase_region_size = %d\n",
+		erase_region_size);
+
+	sector = base;			
+	for (j = 0; j < info->sector_count; j++) {
+		
+		info->start[j] = sector;
+		sector += erase_region_size;
+		info->protect[j] = 0; /* default: not protected */
+	}
+
+	/* set SPI flash extended info */
+	reg = *((volatile ulong*) 0x1e6e2070);
+	switch (reg & 0xe00)
+	{
+	case 0x000:
+		 cpuclk = 266;
+		 break;
+	case 0x200:
+		 cpuclk = 233;
+		 break;
+	case 0x400:
+		 cpuclk = 200;
+		 break;
+	case 0x600:
+		 cpuclk = 166;
+		 break;
+	case 0x800:
+		 cpuclk = 133;
+		 break;
+	case 0xA00:
+		 cpuclk = 100;
+		 break;
+	case 0xC00:
+		 cpuclk = 300;
+		 break;
+	case 0xE00:	
+		 cpuclk = 24;
+		 break;
+	}	
+	switch (reg & 0x3000)
+	{
+	case 0x1000:
+		 cpuclk /= 2;
+		 break;
+	case 0x2000:
+		 cpuclk /= 4;
+		 break;
+	case 0x3000:	
+		 cpuclk /= 3;
+		 break;
+	}	
+	div = 2;
+	info->tCK_Write = 7;
+	while ( (cpuclk/div) > WriteClk )
+	{
+	    info->tCK_Write--;	
+	    div +=2;	
+	}
+	div = 2;
+	info->tCK_Erase = 7;
+	while ( (cpuclk/div) > EraseClk )
+	{
+	    info->tCK_Erase--;	
+	    div +=2;	
+	}
+	div = 2;
+	info->tCK_Read = 7;
+	while ( (cpuclk/div) > ReadClk )
+	{
+	    info->tCK_Read--;	
+	    div +=2;	
+	}
+	
+	/* unprotect flash */	
+	write_status_register(info, 0);
+
+	reset_flash(info);
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len)
+{
+	ulong j, base, offset;
+	ulong ulCtrlData;
+	uchar jReg;
+
+	base = info->start[0];
+	offset = addr - base;
+	
+	enable_write (info);
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x02);
+	udelay(10);
+	*(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
+	udelay(10);
+	*(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
+	udelay(10);
+	*(uchar *) (base) = (uchar) ((offset & 0x0000ff));
+	udelay(10);
+
+	for (j=0; j<len; j++)
+	{
+	    *(uchar *) (base) = *(uchar *) (src++);
+	    udelay(10);
+	}
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_LOW | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+	*(uchar *) (base) = (uchar) (0x05);
+	udelay(10);
+	do {
+	    jReg = *(volatile uchar *) (base);
+	} while ((jReg & 0x01));
+	ulCtrlData  = (info->tCK_Write << 8);
+	ulCtrlData |= CE_HIGH | USERMODE;
+	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+	udelay(100);
+		return 0;
+}	
+
+/*-----------------------------------------------------------------------
+ */
+//static int flash_read_buffer (flash_info_t *info, uchar *dest, ulong addr, int len)
+//{
+//	ulong j, base, offset;
+//	ulong ulCtrlData;
+//	uchar jReg;
+//
+//	base = info->start[0];
+//	offset = addr - base;
+//	
+//	/* Set Normal Reading */
+//	ulCtrlData  = (info->tCK_Read << 8);
+//	ulCtrlData &= 0xfffffffC;
+//	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+//	udelay(100);
+//	*(uchar *) (base) = (uchar) (0x03);
+//	udelay(10);
+//	*(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
+//	udelay(10);
+//	*(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
+//	udelay(10);
+//	*(uchar *) (base) = (uchar) ((offset & 0x0000ff));
+//	udelay(10);
+//
+//    for (j=0; j<len; j++)
+//	{
+//		*(uchar *) (dest++) = *(uchar *) (base);
+//		udelay(10);
+//	}
+//
+//	ulCtrlData  = (info->tCK_Write << 8);
+//	ulCtrlData |= CE_LOW | USERMODE;
+//	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+//	udelay(100);
+//	*(uchar *) (base) = (uchar) (0x05);
+//	udelay(10);
+//	do {
+//		jReg = *(volatile uchar *) (base);
+//	} while ((jReg & 0x01));
+//	ulCtrlData  = (info->tCK_Write << 8);
+//	ulCtrlData |= CE_HIGH | USERMODE;
+//	*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+//	udelay(100);
+//
+//	return 0;
+//}	
+
+/*-----------------------------------------------------------------------
+ *
+ * export functions
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ *
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size (bank_base[i], i);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+#ifndef CONFIG_FLASH_QUIET_TEST
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, flash_info[i].size, flash_info[i].size << 20);
+#endif /* CONFIG_FLASH_QUIET_TEST */
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CONFIG_MONITOR_BASE >= CONFIG_FLASH_BASE)
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_MONITOR_BASE,
+		       CONFIG_MONITOR_BASE + monitor_flash_len  - 1,
+		       flash_get_info(CONFIG_MONITOR_BASE));
+#endif
+
+	/* Environment protection ON by default */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		       flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	/* Redundant environment protection ON by default */
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
+		       flash_get_info(CONFIG_ENV_ADDR_REDUND));
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_FLASH_BASE)
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++)
+	{
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	flash_sect_t sect;
+
+	ulong base, offset;
+	ulong ulCtrlData;
+	uchar jReg;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		puts ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		putc ('\n');
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			/* start erasing */
+			enable_write(info);
+
+			base = info->start[0];
+			offset = info->start[sect] - base;
+
+			ulCtrlData  = (info->tCK_Erase << 8);
+			ulCtrlData |= CE_LOW | USERMODE;
+			*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+			udelay(100);
+			*(uchar *) (base) = (uchar) (0xd8);
+			udelay(10);
+			*(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
+			udelay(10);
+			*(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
+			udelay(10);
+			*(uchar *) (base) = (uchar) ((offset & 0x0000ff));
+			udelay(10);
+
+			ulCtrlData  = (info->tCK_Erase << 8);
+			ulCtrlData |= CE_HIGH | USERMODE;
+			*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+			udelay(100);
+
+			ulCtrlData  = (info->tCK_Erase << 8);
+			ulCtrlData |= CE_LOW | USERMODE;
+			*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+			udelay(100);
+			*(uchar *) (base) = (uchar) (0x05);
+			udelay(10);
+			do {
+			    jReg = *(volatile uchar *) (base);
+			} while ((jReg & 0x01));
+			ulCtrlData  = (info->tCK_Erase << 8);
+			ulCtrlData |= CE_HIGH | USERMODE;
+			*(ulong *) (STCBaseAddress + SPICtrlRegOffset) = ulCtrlData;
+			udelay(100);
+
+			putc ('.');
+		}
+	}
+	puts (" done\n");
+	
+	reset_flash(info);
+	
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	putc ('\n');
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int count;
+	
+	/* get lower aligned address */	
+	if (addr & (BufferSize - 1))
+	{
+	    count = cnt >= BufferSize ? (BufferSize - (addr & 0xff)):cnt;	
+	    flash_write_buffer (info, src, addr, count);
+	    addr+= count;
+	    src += count;
+	    cnt -= count;	
+	}
+	
+	/* prog */		
+	while (cnt > 0) {				
+	    count = cnt >= BufferSize ? BufferSize:cnt;
+	    flash_write_buffer (info, src, addr, count);
+	    addr+= count;
+	    src += count;
+	    cnt -= count;
+	} 		
+
+	reset_flash(info);
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int read_buff (flash_info_t * info, uchar * dest, ulong addr, ulong cnt)
+{
+	ulong buf;
+
+	while (cnt >=4) {
+
+		buf = *(ulong *)addr;
+		*(dest+3) = buf >> 24;
+		*(dest+2) = buf >> 16;
+		*(dest+1) = buf >> 8;
+		*(dest+0) = buf;
+
+		dest += 4;
+		addr +=4;
+	cnt -= 4;
+	};
+
+	while (cnt--)
+	{
+		*dest = *(uchar *)addr;
+		dest++,addr++;
+	}
+	return 0;
+}
+#endif /* CONFIG_FLASH_SPI */
diff --git a/board/aspeed/ast2050/hactest.c b/board/aspeed/ast2050/hactest.c
new file mode 100644
index 0000000..23e65e2
--- /dev/null
+++ b/board/aspeed/ast2050/hactest.c
@@ -0,0 +1,764 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Diagnostics support
+ */
+#include <common.h>
+#include <command.h>
+#include <post.h>
+#include "slt.h"
+
+#if ((CFG_CMD_SLT & CFG_CMD_HACTEST) && defined(CONFIG_SLT))
+#include "hactest.h"
+
+#include "aes.c"
+#include "rc4.c"
+
+static unsigned char crypto_src[CRYPTO_MAX_SRC], crypto_dst[CRYPTO_MAX_DST], crypto_context[CRYPTO_MAX_CONTEXT];
+static unsigned char hash_src[HASH_MAX_SRC], hash_dst[HASH_MAX_DST], hmac_key[HMAC_MAX_KEY];
+
+/*
+ * table 
+ */
+static aes_test aestest[] = {
+    { CRYPTOMODE_ECB, 128,
+     {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c, '\0'},
+     {0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d, 0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34, '\0'},
+     {0x39, 0x25, 0x84, 0x1d, 0x02, 0xdc, 0x09, 0xfb, 0xdc, 0x11, 0x85, 0x97, 0x19, 0x6a, 0x0b, 0x32, '\0'} },
+    {0xFF, 0xFF, "", "", ""},		/* End Mark */
+};
+
+static rc4_test rc4test[] = {
+    {{0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'},
+     {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'}}, 	
+    {{0xff}, {0xff}},				/* End Mark */	
+};
+
+static hash_test hashtest[] = {
+    {HASHMODE_SHA1, 20,
+     "abc",
+     {0x53, 0x20, 0xb0, 0x8c, 0xa1, 0xf5, 0x74, 0x62, 0x50, 0x71, 0x89, 0x41, 0xc5, 0x0a, 0xdf, 0x4e, 0xbb, 0x55, 0x76, 0x06, '\0'}},
+    {0xFF, 0xFF, "", ""},			/* End Mark */ 
+};
+
+static hmac_test hmactest[] = {
+    {HASHMODE_SHA1, 64, 20,
+     {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, '\0' },
+     "Sample #1",
+     {0xbf, 0x39, 0xda, 0xb1, 0x7d, 0xc2, 0xe1, 0x23, 0x0d, 0x28, 0x35, 0x3b, 0x8c, 0xcb, 0x14, 0xb6, 0x22, 0x02, 0x65, 0xb3, '\0'}},
+    {0xFF, 0xFF, 0xFF, "", "", ""},			/* End Mark */ 
+};
+
+void EnableHMAC(void)
+{
+    unsigned long ulData;
+    	
+    /* init SCU */
+    *(unsigned long *) (0x1e6e2000) = 0x1688a8a8;
+    
+    ulData = *(volatile unsigned long *) (0x1e6e200c);
+    ulData &= 0xfdfff;
+    *(unsigned long *) (0x1e6e200c) = ulData;
+    udelay(100);
+    ulData = *(volatile unsigned long *) (0x1e6e2004);
+    ulData &= 0xfffef;
+    *(unsigned long *) (0x1e6e2004) = ulData;
+    
+}
+
+/* AES */
+void aes_enc_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
+{
+
+    unsigned long i, ulTemp, ulCommand;
+    unsigned char ch;
+    unsigned char *pjsrc, *pjdst, *pjcontext;
+    
+    ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
+                CRYPTO_AES | CRYPTO_ENCRYPTO | CRYPTO_SYNC_MODE_ASYNC;
+
+    switch (ctx->nr)
+    {
+    case 10:
+        ulCommand |= CRYPTO_AES128;
+        break;
+    case 12:
+        ulCommand |= CRYPTO_AES192;
+        break;    
+    case 14:
+        ulCommand |= CRYPTO_AES256;
+        break;    
+    }
+
+    switch (ulAESMode)
+    {
+    case CRYPTOMODE_ECB:
+        ulCommand |= CRYPTO_AES_ECB;
+        break;
+    case CRYPTOMODE_CBC:
+        ulCommand |= CRYPTO_AES_CBC;
+        break;
+    case CRYPTOMODE_CFB:
+        ulCommand |= CRYPTO_AES_CFB;
+        break;
+    case CRYPTOMODE_OFB:
+        ulCommand |= CRYPTO_AES_OFB;
+        break;
+    case CRYPTOMODE_CTR:
+        ulCommand |= CRYPTO_AES_CTR;
+        break;                
+    }
+
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
+    pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
+    	
+    /* Init HW */
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
+
+    /* Set source */
+    for (i=0; i< ulMsgLength; i++)
+    {
+    	ch = *(uint8 *)(input + i);    	
+    	*(uint8 *) (pjsrc + i) = ch;
+    }
+     
+    /* Set Context */
+    /* Set IV */
+    for (i=0; i<16; i++)
+    {
+        ch = *(uint8 *) (iv + i);
+    	*(uint8 *) (pjcontext + i) = ch;
+    }
+       
+    /* Set Expansion Key */   
+    for (i=0; i<(4*(ctx->nr+1)); i++)
+    {
+        ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
+    	*(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
+    }
+
+    /* fire cmd */
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
+    do {
+        ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
+    } while (ulTemp & CRYPTO_BUSY);	
+    
+    /* Output */
+    for (i=0; i<ulMsgLength; i++)
+    {
+        ch = *(uint8 *) (pjdst + i);        
+        *(uint8 *) (output + i) = ch;    
+    }
+    
+} /* aes_enc_ast3000 */
+
+
+void aes_dec_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
+{
+    unsigned long i, ulTemp, ulCommand;
+    unsigned char ch;
+    unsigned char *pjsrc, *pjdst, *pjcontext;
+    
+    ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
+                CRYPTO_AES | CRYPTO_DECRYPTO | CRYPTO_SYNC_MODE_ASYNC;
+
+    switch (ctx->nr)
+    {
+    case 10:
+        ulCommand |= CRYPTO_AES128;
+        break;
+    case 12:
+        ulCommand |= CRYPTO_AES192;
+        break;    
+    case 14:
+        ulCommand |= CRYPTO_AES256;
+        break;    
+    }
+
+    switch (ulAESMode)
+    {
+    case CRYPTOMODE_ECB:
+        ulCommand |= CRYPTO_AES_ECB;
+        break;
+    case CRYPTOMODE_CBC:
+        ulCommand |= CRYPTO_AES_CBC;
+        break;
+    case CRYPTOMODE_CFB:
+        ulCommand |= CRYPTO_AES_CFB;
+        break;
+    case CRYPTOMODE_OFB:
+        ulCommand |= CRYPTO_AES_OFB;
+        break;
+    case CRYPTOMODE_CTR:
+        ulCommand |= CRYPTO_AES_CTR;
+        break;                
+    }
+
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
+    pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
+	
+    /* Init HW */
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
+
+    /* Set source */
+    for (i=0; i< ulMsgLength; i++)
+    {
+    	ch = *(uint8 *)(input + i);    	
+    	*(uint8 *) (pjsrc + i) = ch;
+    }
+     
+    /* Set Context */
+    /* Set IV */
+    for (i=0; i<16; i++)
+    {
+        ch = *(uint8 *) (iv + i);
+    	*(uint8 *) (pjcontext + i) = ch;
+    }
+       
+    /* Set Expansion Key */   
+    for (i=0; i<(4*(ctx->nr+1)); i++)
+    {
+        ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
+    	*(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
+    }
+
+    /* fire cmd */
+    *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
+    do {
+        ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
+    } while (ulTemp & CRYPTO_BUSY);	
+    
+    /* Output */
+    for (i=0; i<ulMsgLength; i++)
+    {
+        ch = *(uint8 *) (pjdst + i);        
+        *(uint8 *) (output + i) = ch;    
+    }
+
+} /* aes_dec_ast3000 */
+
+void rc4_crypt_ast3000(uint8 *data, int ulMsgLength, uint8 *rc4_key, uint32 ulKeyLength)
+{
+    struct rc4_state s;
+    unsigned long i, ulTemp, ulCommand;
+    unsigned char ch;
+    unsigned char *pjsrc, *pjdst, *pjcontext;
+
+    ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
+                CRYPTO_RC4 | CRYPTO_SYNC_MODE_ASYNC;
+
+    rc4_setup( &s, rc4_key, ulKeyLength );
+
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
+    pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
+	
+    /* Init HW */
+    *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;	
+    *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;	
+    *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;	
+    *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;	
+          	
+
+    /* Set source */
+    for (i=0; i< ulMsgLength; i++)
+    {
+    	ch = *(uint8 *)(data + i);
+    	*(uint8 *) (pjsrc + i) = ch;
+    }
+     
+    /* Set Context */
+    /* Set i, j */
+    *(uint32 *) (pjcontext + 8) = 0x0001;	
+       
+    /* Set Expansion Key */   
+    for (i=0; i<(256/4); i++)
+    {
+       ulTemp = (s.m[i * 4] & 0xFF) + ((s.m[i * 4 + 1] & 0xFF) << 8) + ((s.m[i * 4 + 2] & 0xFF) << 16) + ((s.m[i * 4+ 3] & 0xFF) << 24);
+       *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;	
+    }
+
+    /* fire cmd */
+    *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;    
+    do {
+    	ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
+    } while (ulTemp & CRYPTO_BUSY);	
+
+    /* Output */
+    for (i=0; i<ulMsgLength; i++)
+    {
+        ch = *(volatile uint8 *) (pjdst + i);
+        *(uint8 *) (data + i) = ch;    
+    }
+
+} /* rc4_crypt_ast3000	*/
+
+/* Hash */
+void hash_ast3000(uint8 *msg, uint32 ulLength, unsigned char *output, uint32 ulHashMode)
+{
+   uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;
+   uint8 ch;
+   unsigned char *pjsrc, *pjdst;
+   
+   /* Get Info */
+   switch (ulHashMode)
+   {
+   case HASHMODE_MD5:
+        ulCommand = HASH_ALG_SELECT_MD5;
+        ulDigestLength = 16;
+       break;
+   case HASHMODE_SHA1:
+        ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
+        ulDigestLength = 20;
+       break;
+   case HASHMODE_SHA256:
+        ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
+        ulDigestLength = 32;
+       break;
+   case HASHMODE_SHA224:
+        ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
+        ulDigestLength = 28;
+       break;       	
+   }   	    
+
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
+
+    /* 16byte alignment */
+    ulMyMsgLength = m16byteAlignment(ulLength);
+   	
+   /* Init. HW */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;	
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;	
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;	
+        
+    /* write src */
+    for (i=0; i<ulLength; i++)
+    {
+    	ch = *(uint8 *)(msg+i);
+    	*(uint8 *) (pjsrc + i) = ch;
+    }    
+    for (i=ulLength; i<ulMyMsgLength; i++)
+        *(uint8 *) (pjsrc + i) = 0;
+        
+    /* fire cmd */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand;	
+    
+    /* get digest */
+    do {
+    	ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);    	
+    } while (ulTemp & HASH_BUSY);	
+    	
+    for (i=0; i<ulDigestLength; i++)
+    {
+        ch = *(volatile uint8 *) (pjdst + i);
+       *(uint8 *) (output + i) = ch;    
+    }        
+ 
+} /* hash_ast3000 */	
+
+/* HMAC */
+void hmackey_ast3000(uint8 *key, uint32 ulKeyLength, uint32 ulHashMode)
+{
+    uint32 i, ulBlkLength, ulDigestLength, ulTemp, ulCommand;
+    uint8 k0[64], sum[32];
+    uint8 ch;
+    unsigned char *pjsrc, *pjdst, *pjkey;
+
+   /* Get Info */
+   switch (ulHashMode)
+   {
+   case HASHMODE_MD5:
+        ulCommand = HASH_ALG_SELECT_MD5;
+        ulDigestLength = 16;
+       break;
+   case HASHMODE_SHA1:
+        ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
+        ulDigestLength = 20;
+       break;
+   case HASHMODE_SHA256:
+        ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
+        ulDigestLength = 32;
+       break;
+   case HASHMODE_SHA224:
+        ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
+        ulDigestLength = 28;
+       break;       	
+   }   	    
+   ulBlkLength = 64;				/* MD5, SHA1/256/224: 64bytes */
+
+    /* Init */
+    memset( (void *) k0, 0, 64);		/* reset to zero */
+    memset( (void *) sum, 0, 32);		/* reset to zero */
+
+    /* Get k0 */
+    if (ulKeyLength <= ulBlkLength)
+        memcpy( (void *) k0, (void *) key, ulKeyLength );       
+    else /* (ulKeyLength > ulBlkLength) */
+    {
+        hash_ast3000(key, ulKeyLength, sum, ulHashMode);
+        memcpy( (void *) k0, (void *) sum, ulDigestLength );                           
+    }    	
+
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
+    pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
+    
+    /* Calculate digest */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulBlkLength;
+        
+    /* write key to src */
+    for (i=0; i<ulBlkLength; i++)
+    {
+    	ch = *(uint8 *)(k0+i);
+        *(uint8 *) (pjsrc + i) = ch;
+    }    
+    
+    /* fire cmd for calculate */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_DIGEST_CAL_ENABLE;    
+    do {
+    	ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);    	
+    } while (ulTemp & HASH_BUSY);	
+         
+} /* hmackey_ast3000 */
+
+void hmac_ast3000(uint8 *key, uint32 ulKeyLength, uint8 *msg, uint32 ulMsgLength, uint32 ulHashMode, unsigned char *output)
+{
+    uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;;
+    uint8 ch;
+    unsigned char *pjsrc, *pjdst, *pjkey;
+
+    /* Calculate digest */
+   switch (ulHashMode)
+   {
+   case HASHMODE_MD5:
+        ulCommand = HASH_ALG_SELECT_MD5;
+        ulDigestLength = 16;
+       break;
+   case HASHMODE_SHA1:
+        ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
+        ulDigestLength = 20;
+       break;
+   case HASHMODE_SHA256:
+        ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
+        ulDigestLength = 32;
+       break;
+   case HASHMODE_SHA224:
+        ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
+        ulDigestLength = 28;
+       break;       	
+   }   	    
+ 
+    pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
+    pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
+    pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
+    
+    /* 16byte alignment */
+    ulMyMsgLength = m16byteAlignment(ulMsgLength);
+    		
+    /* Init. HW */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
+
+    /* write Text to src */
+    for (i=0; i<ulMsgLength; i++)
+    {
+    	ch = *(uint8 *)(msg+i);
+        *(uint8 *) (pjsrc + i) = ch;
+    }    
+    for (i=ulMsgLength; i<ulMyMsgLength; i++)
+        *(uint8 *) (pjsrc + i) = 0;
+    
+    /* fire cmd */
+    *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_ENABLE;        
+    do {
+    	ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);    	
+    } while (ulTemp & HASH_BUSY);
+
+    /* Output Digest */
+    for (i=0; i<ulDigestLength; i++)
+    {
+        ch = *(uint8 *) (pjdst + i);
+        *(uint8 *) (output + i) = ch;    
+    }
+
+} /* hmac_ast3000 */
+
+/* main hactest procedure */
+int do_hactest (void)
+{
+        unsigned long i, j, Flags = 0;
+	aes_test *pjaes_test;
+        aes_context aes_ctx;
+        unsigned char AES_Mode[8], aes_output[64];
+	unsigned long ulAESMsgLength;
+	
+	rc4_test *pjrc4_test;
+	unsigned char rc4_buf_sw[64], rc4_buf_hw[64];
+	unsigned long ulRC4KeyLength, ulRC4MsgLength;
+	
+	hash_test *pjhash_test;
+	unsigned char HASH_Mode[8], hash_out[64];
+
+	hmac_test *pjhmac_test;
+	unsigned char HMAC_Mode[8], hmac_out[64];
+
+	EnableHMAC();
+	
+	/* AES Test */
+	pjaes_test = aestest;
+	while (pjaes_test->aes_mode != 0xFF)
+	{
+
+            if (pjaes_test->aes_mode == CRYPTOMODE_CBC)
+                strcpy (AES_Mode, "CBC");
+            else if (pjaes_test->aes_mode == CRYPTOMODE_CFB)
+                strcpy (AES_Mode, "CFB");
+            else if (pjaes_test->aes_mode == CRYPTOMODE_OFB)
+                strcpy (AES_Mode, "OFB");
+            else if (pjaes_test->aes_mode == CRYPTOMODE_CTR)
+                strcpy (AES_Mode, "CTR");
+            else    
+                strcpy (AES_Mode, "ECB");
+
+            /* Get Msg. Length */
+            ulAESMsgLength = strlen(pjaes_test->plaintext);
+            j = ( (ulAESMsgLength + 15) >> 4) << 4;
+            for (i=ulAESMsgLength; i<j; i++)
+                pjaes_test->plaintext[i] = 0;
+            ulAESMsgLength = j;    
+                		
+            aes_set_key(&aes_ctx, pjaes_test->key, pjaes_test->key_length);
+            
+            /* Encryption Test */
+            aes_enc_ast3000(&aes_ctx, pjaes_test->plaintext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);	    
+	    if (strncmp(aes_output, pjaes_test->ciphertext, ulAESMsgLength))
+	    {
+	    	Flags |= FLAG_AESTEST_FAIL;	    	
+	        printf("[INFO] AES%d %s Mode Encryption Failed \n", pjaes_test->key_length, AES_Mode);
+	        printf("[DBG] Golden Data Dump .... \n");	        
+	        for (i=0; i< ulAESMsgLength; i++)
+	        {
+	            printf("%02x ", pjaes_test->ciphertext[i]);	        	
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }        
+	        printf("\n [DBG] Error Data Dump .... \n");
+	        for (i=0; i< ulAESMsgLength; i++)
+	        {
+	            printf("%02x ", aes_output[i]);	        	
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }
+	        printf("\n");	                
+	    }
+	    else
+	    {
+	    	/*
+	        printf("[INFO] AES%d %s Mode Encryption Passed \n", pjaes_test->key_length, AES_Mode);
+	        */
+	    }	
+
+            /* Decryption Test */
+            aes_dec_ast3000(&aes_ctx, pjaes_test->ciphertext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);	    
+	    if (strncmp(aes_output, pjaes_test->plaintext, ulAESMsgLength))
+	    {
+	    	Flags |= FLAG_AESTEST_FAIL;
+	        printf("[INFO] AES%d %s Mode Decryption Failed \n", pjaes_test->key_length, AES_Mode);	        
+	        printf("[DBG] Golden Data Dump .... \n");
+	        for (i=0; i< ulAESMsgLength; i++)
+	        {
+	            printf("%02x ", pjaes_test->plaintext[i]);	        	
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }        
+	        printf("\n [DBG] Error Data Dump .... \n");
+	        for (i=0; i< ulAESMsgLength; i++)
+	        {
+	            printf("%02x ", aes_output[i]);	        	
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }
+	        printf("\n");	                
+	    }
+	    else
+	    {
+	    	/*
+	        printf("[INFO] AES%d %s Mode Decryption Passed \n", pjaes_test->key_length, AES_Mode);
+	        */
+	    }	
+	    
+	    pjaes_test++;
+        } /* AES */
+
+	/* RC4 Test */
+	pjrc4_test = rc4test;
+	while ((pjrc4_test->key[0] != 0xff) && (pjrc4_test->data[0] != 0xff))
+	{
+
+            /* Get Info */
+            ulRC4KeyLength = strlen(pjrc4_test->key);
+            ulRC4MsgLength = strlen(pjrc4_test->data);
+            memcpy( (void *) rc4_buf_sw, (void *) pjrc4_test->data, ulRC4MsgLength );
+            memcpy( (void *) rc4_buf_hw, (void *) pjrc4_test->data, ulRC4MsgLength );                                       
+
+            /* Crypto */
+            rc4_crypt_sw(rc4_buf_sw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
+            rc4_crypt_ast3000(rc4_buf_hw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
+           
+	    if (strncmp(rc4_buf_hw, rc4_buf_sw, ulRC4MsgLength))
+	    {
+	    	Flags |= FLAG_RC4TEST_FAIL;	    	
+	        printf("[INFO] RC4 Encryption Failed \n");
+	        printf("[DBG] Golden Data Dump .... \n");
+	        for (i=0; i< ulRC4MsgLength; i++)
+	        {
+	            printf("%02x ", rc4_buf_sw[i]);
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }
+	        printf("\n [DBG] Error Data Dump .... \n");
+	        for (i=0; i< ulRC4MsgLength; i++)
+	        {
+	            printf("%02x ", rc4_buf_hw[i]);
+	            if (((i+1) % 8) == 0)
+	                printf("\n");        
+	        }
+	        printf("\n");	        
+	    }
+	    else
+	    {
+	    	/*
+	        printf("[INFO] RC4 Encryption Passed \n");
+	        */
+	    }	
+
+	    pjrc4_test++;
+	    
+        } /* RC4 */
+       
+	/* Hash Test */
+	pjhash_test = hashtest;
+	while (pjhash_test->hash_mode != 0xFF)
+	{
+
+            if (pjhash_test->hash_mode == HASHMODE_MD5)
+                strcpy (HASH_Mode, "MD5");
+            else if (pjhash_test->hash_mode == HASHMODE_SHA1)
+                strcpy (HASH_Mode, "SHA1");
+            else if (pjhash_test->hash_mode == HASHMODE_SHA256)
+                strcpy (HASH_Mode, "SHA256");
+            else if (pjhash_test->hash_mode == HASHMODE_SHA224)
+                strcpy (HASH_Mode, "SHA224");
+            
+            /* Hash */   		
+            hash_ast3000(pjhash_test->input, strlen(pjhash_test->input), hash_out, pjhash_test->hash_mode);            
+	    if (strncmp(hash_out, pjhash_test->digest, pjhash_test->digest_length))
+	    {
+	    	Flags |= FLAG_HASHTEST_FAIL;	    	
+	        printf("[INFO] HASH %s Failed \n", HASH_Mode);
+	        printf("[DBG] Golden Data Dump .... \n");	        
+	        for (i=0; i< pjhash_test->digest_length; i++)
+	        {
+	            printf("%02x ",pjhash_test->digest[i]);
+	            if (((i+1) % 8) == 0) 	
+	                printf("\n");        
+	        }        
+	        printf("\n [DBG] Error Data Dump .... \n");
+	        for (i=0; i< pjhash_test->digest_length; i++)
+	        {
+	            printf("%02x ",hash_out[i]);
+	            if (((i+1) % 8) == 0) 	
+	                printf("\n");        
+	        }
+	        printf("\n");
+	    }
+	    else
+	    {
+	    	/*
+	        printf("[INFO] HASH %s Passed \n", HASH_Mode);
+	        */
+	    }	
+
+            pjhash_test++;
+            
+        } /* Hash Test */
+
+	/* HMAC Test */
+	pjhmac_test = hmactest;
+	while (pjhmac_test->hash_mode != 0xFF)
+	{
+
+            if (pjhmac_test->hash_mode == HASHMODE_MD5)
+                strcpy (HMAC_Mode, "MD5");
+            else if (pjhmac_test->hash_mode == HASHMODE_SHA1)
+                strcpy (HMAC_Mode, "SHA1");
+            else if (pjhmac_test->hash_mode == HASHMODE_SHA256)
+                strcpy (HMAC_Mode, "SHA256");
+            else if (pjhmac_test->hash_mode == HASHMODE_SHA224)
+                strcpy (HMAC_Mode, "SHA224");
+            
+            /* HMAC */   		
+            hmackey_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->hash_mode);
+            hmac_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->input, strlen(pjhmac_test->input), pjhmac_test->hash_mode, hmac_out);            
+	    if (strncmp(hmac_out, pjhmac_test->digest, pjhmac_test->digest_length))
+	    {
+	    	Flags |= FLAG_HASHTEST_FAIL;	    	
+	        printf("[INFO] HMAC %s Failed \n", HMAC_Mode);
+	        printf("[DBG] Golden Data Dump .... \n");	        
+	        for (i=0; i< pjhmac_test->digest_length; i++)
+	        {
+	            printf("%02x ",pjhmac_test->digest[i]);
+	            if (((i+1) % 8) == 0) 	
+	                printf("\n");        
+	        }        
+	        printf("\n [DBG] Error Data Dump .... \n");
+	        for (i=0; i< pjhmac_test->digest_length; i++)
+	        {
+	            printf("%02x ",hmac_out[i]);
+	            if (((i+1) % 8) == 0) 	
+	                printf("\n");        
+	        }
+	        printf("\n");
+	    }
+	    else
+	    {
+	    	/*
+	        printf("[INFO] HMAC %s Passed \n", HMAC_Mode);
+	        */
+	    }	
+
+            pjhmac_test++;
+            
+        } /* HMAC Test */
+
+	return Flags;
+	
+}
+
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/hactest.h b/board/aspeed/ast2050/hactest.h
new file mode 100644
index 0000000..5f86b99
--- /dev/null
+++ b/board/aspeed/ast2050/hactest.h
@@ -0,0 +1,196 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Err Flags */
+#define FLAG_AESTEST_FAIL  		0x00000001
+#define FLAG_RC4TEST_FAIL  		0x00000002
+#define FLAG_HASHTEST_FAIL  		0x00000004
+
+/* Specific */
+/*
+#define DRAM_BASE			0x40000000
+#define	CRYPTO_SRC_BASE			(DRAM_BASE + 0x100000)
+#define	CRYPTO_DST_BASE			(DRAM_BASE + 0x200000)
+#define	CRYPTO_CONTEXT_BASE		(DRAM_BASE + 0x300000)
+
+#define	HASH_SRC_BASE			(DRAM_BASE + 0x400000)
+#define	HASH_DST_BASE			(DRAM_BASE + 0x500000)
+#define	HMAC_KEY_BASE			(DRAM_BASE + 0x600000)
+*/
+#define m08byteAlignment(x)		((x + 0x00000007) & 0xFFFFFFF8)
+#define m16byteAlignment(x)		((x + 0x0000000F) & 0xFFFFFFF0)
+#define m64byteAlignment(x)		((x + 0x0000003F) & 0xFFFFFFC0)
+
+#define CRYPTO_ALIGNMENT		16
+#define CRYPTO_MAX_SRC			(100+CRYPTO_ALIGNMENT)
+#define CRYPTO_MAX_DST			(100+CRYPTO_ALIGNMENT)
+#define CRYPTO_MAX_CONTEXT		(100+CRYPTO_ALIGNMENT)
+
+#define HASH_ALIGNMENT			16
+#define HMAC_KEY_ALIGNMENT	 	64
+#define HASH_MAX_SRC			(100+HASH_ALIGNMENT)
+#define HASH_MAX_DST			(32+HASH_ALIGNMENT)
+#define HMAC_MAX_KEY			(64+HMAC_KEY_ALIGNMENT)
+
+/* General */
+#define HAC_REG_BASE 			0x1e6e3000
+
+#define MAX_KEYLENGTH			100
+#define MAX_TEXTLENGTH			100
+#define MAX_AESTEXTLENGTH		256
+#define MAX_RC4TEXTLENGTH		256
+#define MAX_RC4KEYLENGTH		256
+
+#define CRYPTOMODE_ECB			0x00
+#define CRYPTOMODE_CBC			0x01
+#define CRYPTOMODE_CFB			0x02
+#define CRYPTOMODE_OFB			0x03
+#define CRYPTOMODE_CTR			0x04
+
+#define HASHMODE_MD5			0x00
+#define HASHMODE_SHA1			0x01
+#define HASHMODE_SHA256			0x02
+#define HASHMODE_SHA224			0x03
+
+#define MIXMODE_DISABLE                 0x00
+#define MIXMODE_CRYPTO                  0x02
+#define MIXMODE_HASH                    0x03
+
+#define REG_CRYPTO_SRC_BASE_OFFSET	0x00
+#define REG_CRYPTO_DST_BASE_OFFSET	0x04
+#define REG_CRYPTO_CONTEXT_BASE_OFFSET	0x08
+#define REG_CRYPTO_LEN_OFFSET		0x0C
+#define REG_CRYPTO_CMD_BASE_OFFSET	0x10
+//#define REG_CRYPTO_ENABLE_OFFSET	0x14
+#define REG_CRYPTO_STATUS_OFFSET	0x1C
+
+#define REG_HASH_SRC_BASE_OFFSET	0x20
+#define REG_HASH_DST_BASE_OFFSET	0x24
+#define REG_HASH_KEY_BASE_OFFSET	0x28
+#define REG_HASH_LEN_OFFSET		0x2C
+#define REG_HASH_CMD_OFFSET		0x30
+//#define REG_HASH_ENABLE_OFFSET		0x14
+#define REG_HASH_STATUS_OFFSET		0x1C
+
+#define HASH_BUSY			0x01
+#define CRYPTO_BUSY			0x02
+
+//#define ENABLE_HASH			0x01
+//#define DISABLE_HASH			0x00
+//#define ENABLE_CRYPTO			0x02
+//#define DISABLE_CRYPTO			0x00
+
+#define CRYPTO_SYNC_MODE_MASK		0x03
+#define CRYPTO_SYNC_MODE_ASYNC		0x00
+#define CRYPTO_SYNC_MODE_PASSIVE	0x02
+#define CRYPTO_SYNC_MODE_ACTIVE		0x03
+
+#define CRYPTO_AES128			0x00
+#define CRYPTO_AES192			0x04
+#define CRYPTO_AES256			0x08
+
+#define CRYPTO_AES_ECB			0x00
+#define CRYPTO_AES_CBC			0x10
+#define CRYPTO_AES_CFB			0x20
+#define CRYPTO_AES_OFB			0x30
+#define CRYPTO_AES_CTR			0x40
+
+#define CRYPTO_ENCRYPTO			0x80
+#define CRYPTO_DECRYPTO			0x00
+
+#define CRYPTO_AES			0x000
+#define CRYPTO_RC4			0x100
+
+#define CRYPTO_ENABLE_RW		0x000
+#define CRYPTO_ENABLE_CONTEXT_LOAD	0x000
+#define CRYPTO_ENABLE_CONTEXT_SAVE	0x000
+
+#define HASH_SYNC_MODE_MASK		0x03
+#define HASH_SYNC_MODE_ASYNC		0x00
+#define HASH_SYNC_MODE_PASSIVE		0x02
+#define HASH_SYNC_MODE_ACTIVE		0x03
+
+#define HASH_READ_SWAP_ENABLE		0x04
+#define HMAC_SWAP_CONTROL_ENABLE	0x08
+
+#define HASH_ALG_SELECT_MASK		0x70
+#define HASH_ALG_SELECT_MD5		0x00
+#define HASH_ALG_SELECT_SHA1		0x20
+#define HASH_ALG_SELECT_SHA224		0x40
+#define HASH_ALG_SELECT_SHA256		0x50
+
+#define HAC_ENABLE			0x80
+#define HAC_DIGEST_CAL_ENABLE		0x180
+#define HASH_INT_ENABLE			0x200
+
+/* AES */
+#ifndef uint8
+#define uint8  unsigned char
+#endif
+
+#ifndef uint32
+#define uint32 unsigned long int
+#endif
+
+typedef struct
+{
+    uint32 erk[64];     /* encryption round keys */
+    uint32 drk[64];     /* decryption round keys */
+    int nr;             /* number of rounds */
+}
+aes_context;
+
+typedef struct
+{
+    int	  aes_mode;
+    int	  key_length;
+	
+    uint8 key[32];	/* as iv in CTR mode */
+    uint8 plaintext[64];
+    uint8 ciphertext[64];
+    
+}
+aes_test;
+
+/* RC4 */
+typedef struct
+{
+    uint8 key[32];
+    uint8 data[64];
+}
+rc4_test;
+
+/* Hash */
+typedef struct
+{
+    int	  hash_mode;
+    int	  digest_length;
+	
+    uint8 input[64];
+    uint8 digest[64];
+    
+}
+hash_test;
+	
+/* HMAC */
+typedef struct
+{
+    int	  hash_mode;
+    int	  key_length;
+    int	  digest_length;
+
+    uint8 key[100];	
+    uint8 input[64];
+    uint8 digest[64];
+    
+}
+hmac_test;
diff --git a/board/aspeed/ast2050/hwreg.h b/board/aspeed/ast2050/hwreg.h
new file mode 100644
index 0000000..09e2af5
--- /dev/null
+++ b/board/aspeed/ast2050/hwreg.h
@@ -0,0 +1,214 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This file contains the AST2100 SOC Register locations
+ *
+ *  Copyright (C) 2005 American Megatrends Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+
+#define AST_SMC_BASE			0x16000000
+
+#define AST_MAC1_BASE			0x1E660000
+#define AST_MAC2_BASE			0x1E680000
+
+#define AST_GPIO_BASE			0x1E780000
+
+
+ /* -------------------------------------------------------------
+ *                  SDRAM Registers
+ * -------------------------------------------------------------
+ */
+#define AST_SDRAMC_BASE			0x1E6E0000
+
+#define SDRAM_PROTECTION_KEY_REG            (AST_SDRAMC_BASE + 0x00)
+#define SDRAM_CONFIG_REG                    (AST_SDRAMC_BASE + 0x04)
+#define SDRAM_GRAP_MEM_PROTECTION_REG       (AST_SDRAMC_BASE + 0x08)
+#define SDRAM_REFRESH_TIMING_REG            (AST_SDRAMC_BASE + 0x0C)
+#define SDRAM_NSPEED_REG1                   (AST_SDRAMC_BASE + 0x10)
+#define SDRAM_LSPEED_REG1                   (AST_SDRAMC_BASE + 0x14)
+#define SDRAM_NSPEED_REG2                   (AST_SDRAMC_BASE + 0x18)
+#define SDRAM_LSPEED_REG2                   (AST_SDRAMC_BASE + 0x1C)
+#define SDRAM_NSPEED_DELAY_CTRL_REG         (AST_SDRAMC_BASE + 0x20)
+#define SDRAM_LSPEED_DELAY_CTRL_REG         (AST_SDRAMC_BASE + 0x24)
+#define SDRAM_MODE_SET_CTRL_REG             (AST_SDRAMC_BASE + 0x28)
+#define SDRAM_MRS_EMRS2_MODE_SET_REG        (AST_SDRAMC_BASE + 0x2C)
+#define SDRAM_MRS_EMRS3_MODE_SET_REG        (AST_SDRAMC_BASE + 0x30)
+#define SDRAM_PWR_CTRL_REG                  (AST_SDRAMC_BASE + 0x34)
+#define SDRAM_PAGE_MISS_LATENCY_MASK_REG    (AST_SDRAMC_BASE + 0x38)
+#define SDRAM_PRIORITY_GROUP_SET_REG        (AST_SDRAMC_BASE + 0x3C)
+#define SDRAM_MAX_GRANT_LENGTH_REG1         (AST_SDRAMC_BASE + 0x40)
+#define SDRAM_MAX_GRANT_LENGTH_REG2         (AST_SDRAMC_BASE + 0x44)
+#define SDRAM_MAX_GRANT_LENGTH_REG3         (AST_SDRAMC_BASE + 0x48)
+#define SDRAM_ECC_CTRL_STATUS_REG           (AST_SDRAMC_BASE + 0x50)
+#define SDRAM_ECC_SEGMENT_EN_REG            (AST_SDRAMC_BASE + 0x54)
+#define SDRAM_ECC_SCRUB_REQ_MASK_CTRL_REG   (AST_SDRAMC_BASE + 0x58)
+#define SDRAM_ECC_ADDR_FIRST_ERR_REG        (AST_SDRAMC_BASE + 0x5C)
+#define SDRAM_IO_BUFF_MODE_REG              (AST_SDRAMC_BASE + 0x60)
+#define SDRAM_DLL_CTRL_REG1                 (AST_SDRAMC_BASE + 0x64)
+#define SDRAM_DLL_CTRL_REG2                 (AST_SDRAMC_BASE + 0x68)
+#define SDRAM_DLL_CTRL_REG3                 (AST_SDRAMC_BASE + 0x6C)
+#define SDRAM_TEST_CTRL_STATUS_REG          (AST_SDRAMC_BASE + 0x70)
+#define SDRAM_TEST_START_ADDR_LENGTH_REG    (AST_SDRAMC_BASE + 0x74)
+#define SDRAM_TEST_FAIL_DQ_BIT_REG          (AST_SDRAMC_BASE + 0x78)
+#define SDRAM_TEST_INIT_VALUE_REG           (AST_SDRAMC_BASE + 0x7C)
+#define AST2100_COMPATIBLE_SCU_PASSWORD     (AST_SDRAMC_BASE + 0x100)
+#define AST2100_COMPATIBLE_SCU_MPLL_PARA    (AST_SDRAMC_BASE + 0x120)
+
+/*-------------------------------------------------------------------
+ *				    SCU Registers
+ *--------------------------------------------------------------------
+ */
+#define AST_SCU_BASE			0x1E6E2000
+
+#define SCU_KEY_CONTROL_REG		(AST_SCU_BASE +  0x00)
+#define SCU_SYS_RESET_REG               (AST_SCU_BASE +  0x04)
+#define SCU_CLK_SELECT_REG              (AST_SCU_BASE +  0x08)
+#define SCU_CLK_STOP_REG                (AST_SCU_BASE +  0x0C)
+#define SCU_OSC_COUNT_CTRL_REG		(AST_SCU_BASE +  0x10)
+#define SCU_OSC_COUNT_VALUE_REG         (AST_SCU_BASE +  0x14)
+#define SCU_INTR_CRTL_VALUE_REG         (AST_SCU_BASE +  0x18)
+#define SCU_32CLK_ERR_CORRECT_REG       (AST_SCU_BASE +  0x1C)
+#define SCU_M_PLL_PARAM_REG             (AST_SCU_BASE +  0x20)
+#define SCU_H_PLL_PARAM_REG             (AST_SCU_BASE +  0x24)
+#define SCU_FREQ_CNTR_CTRL_RANGE_REG	(AST_SCU_BASE +  0x28)
+
+#define SCU_SOC_SCRATCH1_REG            (AST_SCU_BASE +  0x40)
+#define SCU_SOC_SCRATCH2_REG            (AST_SCU_BASE +  0x44)
+#define SCU_HW_STRAPPING_REG            (AST_SCU_BASE +  0x70)
+#define SCU_REV_ID_REG			(AST_SCU_BASE +  0x7c)
+
+/* -------------------------------------------------------------------
+ *  					Timer Registers
+ * -------------------------------------------------------------------
+ */
+#define AST_TIMER_BASE			0x1E782000
+
+#define TIMER1_COUNT_REG                (AST_TIMER_BASE + 0x00)
+#define TIMER1_RELOAD_REG               (AST_TIMER_BASE + 0x04)
+#define TIMER1_FIRST_MATCH_REG          (AST_TIMER_BASE + 0x08)
+#define TIMER1_SEC_MATCH_REG            (AST_TIMER_BASE + 0x0C)
+
+#define TIMER2_COUNT_REG                (AST_TIMER_BASE + 0x10)
+#define TIMER2_RELOAD_REG               (AST_TIMER_BASE + 0x14)
+#define TIMER2_FIRST_MATCH_REG          (AST_TIMER_BASE + 0x18)
+#define TIMER2_SEC_MATCH_REG            (AST_TIMER_BASE + 0x1C)
+
+#define TIMER3_COUNT_REG                (AST_TIMER_BASE + 0x20)
+#define TIMER3_RELOAD_REG               (AST_TIMER_BASE + 0x24)
+#define TIMER3_FIRST_MATCH_REG          (AST_TIMER_BASE + 0x28)
+#define TIMER3_SEC_MATCH_REG            (AST_TIMER_BASE + 0x2C)
+
+#define TIMER_CONTROL_REG               (AST_TIMER_BASE + 0x30)
+
+/* --------------------------------------------------------------------
+ *  						GPIO Registers
+ * --------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------
+ * 				 Interrupt Controller Register
+ * -----------------------------------------------------------------
+ */
+#define AST_IC_BASE			0x1E6C0000
+
+#define IRQ_STATUS_REG	                (AST_IC_BASE + 0x00)
+#define FIQ_STATUS_REG	                (AST_IC_BASE + 0x04)
+#define RAW_INT_STATUS_REG	            (AST_IC_BASE + 0x08)
+#define IRQ_SELECT_REG	                (AST_IC_BASE + 0x0C)
+#define IRQ_ENABLE_REG	                (AST_IC_BASE + 0x10)
+#define IRQ_CLEAR_REG					(AST_IC_BASE + 0x14)
+#define SOFT_INT_REG					(AST_IC_BASE + 0x18)
+#define SOFT_INT_CLEAR_REG				(AST_IC_BASE + 0x1C)
+#define PROTECT_ENABLE_REG				(AST_IC_BASE + 0x20)
+
+/*-------------------------------------------------------------
+ * 			  SSP Controllers Registers
+ *  -----------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------
+ *   I2C Controllers Register
+ *  ------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------
+ *   DMA Controllers Registers
+ *  ----------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------
+ *				 RTC Register Locations
+ *------------------------------------------------------------------*/
+
+
+/*------------------------------------------------------------------
+ *				 WDT Register Locations
+ *------------------------------------------------------------------*/
+#define AST_WDT_BASE			0x1E785000
+
+#define WDT_CNT_STATUS_REG  (AST_WDT_BASE + 0x00)
+#define WDT_RELOAD_REG		(AST_WDT_BASE + 0x04)
+#define WDT_CNT_RESTART_REG (AST_WDT_BASE + 0x08)
+#define WDT_CONTROL_REG		(AST_WDT_BASE + 0x0C)
+
+/*-------------------------------------------------------------
+ * 			  UART Registers
+ *  -----------------------------------------------------------
+ */
+
+#define AST_UART1_BASE			0x1E783000
+#define AST_UART2_BASE			0x1E784000
+
+#define UART1_REC_BUFF_REG		(AST_UART1_BASE + 0x00)
+#define UART1_TRANSMIT_HOLD_REG		(AST_UART1_BASE + 0x00)
+#define UART1_INT_EN_REG		(AST_UART1_BASE + 0x04)
+#define UART1_INT_IDENT_REG		(AST_UART1_BASE + 0x08)
+#define UART1_FIFO_CTRL_REG		(AST_UART1_BASE + 0x08)
+#define UART1_LINE_CTRL_REG		(AST_UART1_BASE + 0x0c)
+#define UART1_MODEM_CTRL_REG		(AST_UART1_BASE + 0x10)
+#define UART1_LINE_STS_REG		(AST_UART1_BASE + 0x14)
+#define UART1_MODEM_STS_REG		(AST_UART1_BASE + 0x18)
+#define UART1_SCRATCH_REG		(AST_UART1_BASE + 0x1c)
+#define UART1_DLL_REG			(AST_UART1_BASE + 0x00)
+#define UART1_DLH_REG			(AST_UART1_BASE + 0x04)
+
+#define UART2_REC_BUFF_REG		(AST_UART2_BASE + 0x00)
+#define UART2_TRANSMIT_HOLD_REG		(AST_UART2_BASE + 0x00)
+#define UART2_INT_EN_REG		(AST_UART2_BASE + 0x04)
+#define UART2_INT_IDENT_REG		(AST_UART2_BASE + 0x08)
+#define UART2_FIFO_CTRL_REG		(AST_UART2_BASE + 0x08)
+#define UART2_LINE_CTRL_REG		(AST_UART2_BASE + 0x0c)
+#define UART2_MODEM_CTRL_REG		(AST_UART2_BASE + 0x10)
+#define UART2_LINE_STS_REG		(AST_UART2_BASE + 0x14)
+#define UART2_MODEM_STS_REG		(AST_UART2_BASE + 0x18)
+#define UART2_SCRATCH_REG		(AST_UART2_BASE + 0x1c)
+#define UART2_DLL_REG			(AST_UART2_BASE + 0x00)
+#define UART2_DLH_REG			(AST_UART2_BASE + 0x04)
+
+/* -----------------------------------------------------------------
+ *      	         AHB Registers
+ * -----------------------------------------------------------------
+*/
+#define AST_AHBC_BASE			0x1E600000
+
+#define AHB_PROTECTION_KEY_REG          (AST_AHBC_BASE + 0x00)
+#define AHB_PRIORITY_CTRL_REG           (AST_AHBC_BASE + 0x80)
+#define AHB_INTERRUPT_CTRL_REG          (AST_AHBC_BASE + 0x88)
+#define AHB_ADDR_REMAP_REG              (AST_AHBC_BASE + 0x8C)
+\ No newline at end of file
diff --git a/board/aspeed/ast2050/mactest.c b/board/aspeed/ast2050/mactest.c
new file mode 100644
index 0000000..042e0d2
--- /dev/null
+++ b/board/aspeed/ast2050/mactest.c
@@ -0,0 +1,506 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * (C) Copyright 2007 ASPEED Software
+ * MAC Manufacture Test in ASPEED's SDK version 0.20.01
+ *
+ * Release History
+ * 1. First Release, river@20071130
+ * 2. Fix the endless loop when PHY is not ready, river@20071204
+ *
+ * Test items:
+ * 1. Support MARVELL PHY only in this version
+ * 2. MDC/MDIO
+ * 3. GMAC/Duplex TX/RX Full_Size, Packet_Length Test
+ * 4. 100M/Duplex TX/RX Full_Size, Packet_Length Test
+ *
+ *
+ *
+*/
+
+
+/*
+* Diagnostics support
+*/
+#include <common.h>
+#include <command.h>
+#include <post.h>
+#include <malloc.h>
+#include <net.h>
+#include "slt.h"
+
+#if ((CFG_CMD_SLT & CFG_CMD_MACTEST) && defined(CONFIG_SLT))
+#include "mactest.h"
+
+static int INL(u_long base, u_long addr)
+{
+	return le32_to_cpu(*(volatile u_long *)(addr + base));
+}
+
+static void OUTL(u_long base, int command, u_long addr)
+{
+	*(volatile u_long *)(addr + base) = cpu_to_le32(command);
+}
+
+
+static void SCU_MAC1_Enable (void)
+{
+	unsigned int SCU_Register;
+
+//MAC1 RESET/PHY_LINK in SCU
+        SCU_Register = INL(SCU_BASE, SCU_RESET_CONTROL_REG);
+	OUTL(SCU_BASE, SCU_Register & ~(0x800), SCU_RESET_CONTROL_REG);
+	
+}
+
+/*------------------------------------------------------------
+ . Reads a register from the MII Management serial interface
+ .-------------------------------------------------------------*/
+static u16 phy_read_register (u8 PHY_Register, u8 PHY_Address)
+{
+	u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1;
+	u16 Return_Data;
+
+	OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG);
+	do {
+		Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIRD);
+		Loop_Count++;
+		if (Loop_Count >= PHY_LOOP) {
+			PHY_Ready = 0;
+			break;
+		}
+	} while (Status == MIIRD);
+       
+	if (PHY_Ready == 0) {
+		printf ("PHY NOT REDAY\n");
+		return 0;
+	}
+	
+	udelay(5*1000);
+	Data = INL (MAC1_IO_BASE, PHYDATA_REG);
+	Return_Data = (Data >> 16);
+
+	return Return_Data;
+}
+
+static void phy_write_register (u8 PHY_Register, u8 PHY_Address, u16 PHY_Data)
+{
+	u32 Status = 0, Loop_Count = 0, PHY_Ready = 1;
+
+	OUTL(MAC1_IO_BASE, PHY_Data, PHYDATA_REG);
+	OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG);
+	do {
+		Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIWR);
+		Loop_Count++;
+		if (Loop_Count >= PHY_LOOP) {
+			PHY_Ready = 0;
+			break;
+		}
+	} while (Status == MIIWR);
+	if (PHY_Ready == 0) {
+		printf ("PHY NOT REDAY\n");
+	}
+}
+
+static int wait_link_resolve (void)
+{
+	int resolved_status, Loop_Count = 0, PHY_Ready = 1;
+
+        do {
+       		resolved_status = (phy_read_register (0x11, 0) & (PHY_RESOLVED_bit | PHY_LINK_bit));
+               	Loop_Count++;
+               	if (Loop_Count >= PHY_LOOP) {
+                   	PHY_Ready = 0;
+                    	printf ("PHY NOT READY\n");
+                    	break;
+                }
+        } while (resolved_status != (PHY_RESOLVED_bit | PHY_LINK_bit));
+        
+        return PHY_Ready;
+}
+
+static void set_phy_speed (int chip, int speed, int duplex)
+{
+	unsigned short data, status;
+
+
+	if (chip == PHYID_VENDOR_MARVELL) {
+		if ((speed == PHY_SPEED_1G) && (duplex == DUPLEX_FULL)) {
+//Manual Control
+			phy_write_register (18, 0, 0);
+			data = phy_read_register (9, 0);
+			phy_write_register (9, 0, data | 0x1800);
+//PHY Reset
+			phy_write_register (0, 0, 0x0140 | 0x8000);
+			do {
+				status = (phy_read_register (0, 0) & 0x8000); 
+			} while (status != 0);
+	
+//Force 1G
+			phy_write_register (29, 0, 0x07);
+			data = phy_read_register (30, 0);
+			phy_write_register (30, 0, data | 0x08);
+			phy_write_register (29, 0, 0x10);
+			data = phy_read_register (30, 0);
+			phy_write_register (30, 0, data | 0x02);
+			phy_write_register (29, 0, 0x12);
+			data = phy_read_register (30, 0);
+			phy_write_register (30, 0, data | 0x01);
+	
+			printf ("FORCE MARVELL PHY to 1G/DUPLEX DONE\n");
+		}
+		else if ((speed == PHY_SPEED_100M) && (duplex == DUPLEX_FULL)) {
+//PHY Reset
+			phy_write_register (0, 0, 0x2100 | 0x8000);
+			do {
+				status = (phy_read_register (0, 0) & 0x8000); 
+			} while (status != 0);
+	
+//Force 100M
+			data = phy_read_register (0, 0);
+			phy_write_register (0, 0, data | 0x4000 | 0x8000);
+			do {
+				status = (phy_read_register (0, 0) & 0x8000); 
+			} while (status != 0);
+			data = phy_read_register (0, 0);
+
+			printf ("FORCE MARVELL PHY to 100M/DUPLEX DONE\n");
+		}
+	}
+	else if ( (chip == PHYID_VENDOR_RTL8201E) || (chip == PHYID_VENDOR_BROADCOM) ){
+		/* basic setting */
+		data  = phy_read_register (0, 0);
+		data &= 0x7140;
+		data |= 0x4000;
+		if (speed == PHY_SPEED_100M)
+		    data |= 0x2000;
+                if (duplex == DUPLEX_FULL)		    
+                    data |= 0x0100;
+		phy_write_register (0, 0, data);
+
+                /* reset */
+		phy_write_register (0, 0, data | 0x8000);
+		do {
+			status = (phy_read_register (0, 0) & 0x8000); 
+		} while (status != 0);
+	        udelay(100*1000);
+		
+		/* basic setting */
+		phy_write_register (0, 0, data);
+
+                if (chip == PHYID_VENDOR_RTL8201E)
+		    printf ("FORCE RTL8201E PHY to 100M/DUPLEX DONE\n");		
+                else if (chip == PHYID_VENDOR_BROADCOM)
+		    printf ("FORCE Broadcom PHY to 100M/DUPLEX DONE\n");		
+		    
+	}	
+	
+}
+
+static void MAC1_reset (void)
+{
+    OUTL(MAC1_IO_BASE, SW_RST_bit, MACCR_REG);
+    for (; (INL(MAC1_IO_BASE, MACCR_REG ) & SW_RST_bit) != 0; ) {udelay(1000);}
+    OUTL(MAC1_IO_BASE, 0, IER_REG );
+}
+
+static int set_mac1_control_register (int Chip_ID)
+{
+	unsigned long	MAC_CR_Register = 0;
+	int    PHY_Ready = 1;
+	u16    PHY_Status, PHY_Speed, PHY_Duplex, Advertise, Link_Partner;
+
+	MAC_CR_Register = SPEED_100M_MODE_bit | RX_ALLADR_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
+
+	if ( (Chip_ID == PHYID_VENDOR_BROADCOM) || (Chip_ID == PHYID_VENDOR_RTL8201E)) {
+		Advertise = phy_read_register (0x04, 0);
+		Link_Partner = phy_read_register (0x05, 0);
+		Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
+		Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
+		if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
+			MAC_CR_Register |= SPEED_100M_MODE_bit;
+			MAC_CR_Register |= FULLDUP_bit;
+		}
+		else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
+			MAC_CR_Register |= SPEED_100M_MODE_bit;
+			MAC_CR_Register &= ~FULLDUP_bit;
+		}
+		else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
+			MAC_CR_Register &= ~SPEED_100M_MODE_bit;
+			MAC_CR_Register |= FULLDUP_bit;
+		}
+		else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
+			MAC_CR_Register &= ~SPEED_100M_MODE_bit;
+			MAC_CR_Register &= ~FULLDUP_bit;
+		}
+	}
+	else if (Chip_ID == PHYID_VENDOR_MARVELL) {
+
+		PHY_Ready = wait_link_resolve ();
+
+		if (PHY_Ready == 1) {
+			PHY_Status = phy_read_register (0x11, 0);
+			PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14;
+			PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13;
+
+			if (PHY_Speed == SPEED_1000M) {
+				MAC_CR_Register |= GMAC_MODE_bit;
+                	}
+			else {
+				MAC_CR_Register &= ~GMAC_MODE_bit;
+				if (PHY_Speed == SPEED_10M) {
+                        		MAC_CR_Register &= ~SPEED_100M_MODE_bit;
+                    		}
+                	}
+                	if (PHY_Duplex == DUPLEX_HALF) {
+				MAC_CR_Register &= ~FULLDUP_bit;
+			}
+		}
+	}
+	OUTL(MAC1_IO_BASE, MAC_CR_Register, MACCR_REG);
+
+	return PHY_Ready;
+}
+
+static void ring_buffer_alloc (void)
+{
+	unsigned int i, j;
+
+//Write data into TX buffer
+	for (i = 0; i < NUM_TX; i++) {
+		for (j = 0; j < TX_BUFF_SZ; j++) {
+			tx_buffer[i][j] = i * 4 + j;
+		}
+	}
+//Initialize RX buffer to 0
+	for (i = 0; i < NUM_RX; i++) {
+		for (j = 0; j < RX_BUFF_SZ; j++) {
+			rx_buffer[i][j] = 0;
+		}
+	}
+//Prepare descriptor
+	for (i = 0; i < NUM_RX; i++) {
+		rx_ring[i].status = cpu_to_le32(RXPKT_RDY + RX_BUFF_SZ);
+		rx_ring[i].buf = ((u32) &rx_buffer[i]);
+		rx_ring[i].reserved = 0;
+	}
+	for (i = 0; i < NUM_TX; i++) {
+		tx_ring[i].status = 0;
+		tx_ring[i].des1 = 0;
+		tx_ring[i].buf = ((u32) &tx_buffer[i]);
+		tx_ring[i].reserved = 0;
+	}
+
+	rx_ring[NUM_RX - 1].status |= cpu_to_le32(EDORR);
+	tx_ring[NUM_TX - 1].status |= cpu_to_le32(EDOTR);
+
+	OUTL(MAC1_IO_BASE, ((u32) &tx_ring), TXR_BADR_REG);
+	OUTL(MAC1_IO_BASE, ((u32) &rx_ring), RXR_BADR_REG);
+	
+	tx_new = 0;
+	rx_new = 0;
+}
+
+static int packet_test (void)
+{
+	unsigned int rx_status, length, i, Loop_Count = 0;
+
+	tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | TX_BUFF_SZ);
+	tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
+	OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
+
+//Compare result
+	do {
+		rx_status = rx_ring[rx_new].status;
+		Loop_Count++;
+	} while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
+	if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
+		/* There was an error.*/
+		printf("RX error status = 0x%08X\n", rx_status);
+		return PACKET_TEST_FAIL;
+	} else {
+		length = (rx_status & BYTE_COUNT_MASK);
+		for (i = 0; i < RX_BUFF_SZ / 4; i++) {
+			if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
+				printf ("ERROR at packet %d, address %x\n", rx_new, i);
+				printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
+				return PACKET_TEST_FAIL;
+			}
+		}
+	}
+    	tx_new = (tx_new + 1) % NUM_TX;
+	rx_new = (rx_new + 1) % NUM_RX;
+
+	return TEST_PASS;
+}
+
+static int packet_length_test (int packet_length)
+{
+	unsigned int rx_status, length, i, Loop_Count = 0;
+
+	tx_ring[tx_new].status &= (~(BYTE_COUNT_MASK));
+	tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | packet_length);
+	tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
+	OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
+
+//Compare result
+	do {
+		rx_status = rx_ring[rx_new].status;
+		Loop_Count++;
+	} while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
+	if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
+		/* There was an error.*/
+		printf("RX error status = 0x%08X\n", rx_status);
+		return PACKET_LENGTH_TEST_FAIL;
+	} else {
+		length = (rx_status & BYTE_COUNT_MASK) - 4;
+                if (length != packet_length) {
+			printf ("Received Length ERROR. Gold = %d, Fail = %d\n",packet_length, length);
+			printf ("rx_new = %d, tx_new = %d\n", rx_new, tx_new);
+			return PACKET_LENGTH_TEST_FAIL;
+                }
+		for (i = 0; i < length; i++) {
+		    if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
+		    	printf ("ERROR at packet %d, address %x\n", rx_new, i);
+		    	printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
+		    	return PACKET_LENGTH_TEST_FAIL;
+		    }
+		}
+	}
+	rx_ring[rx_new].status &= (~(RXPKT_STATUS));
+    	tx_new = (tx_new + 1) % NUM_TX;
+	rx_new = (rx_new + 1) % NUM_RX;
+
+	return TEST_PASS;
+}
+
+static int MAC1_init (int id)
+{
+	int phy_status = 0;
+
+	MAC1_reset ();
+	phy_status = set_mac1_control_register (id);
+       	ring_buffer_alloc ();
+       	
+       	return phy_status;
+}
+
+int do_mactest (void)
+{
+	unsigned int phy_id, i;
+	int test_result = 0, phy_status = 0;
+
+	SCU_MAC1_Enable();
+	phy_id = ((phy_read_register (0x02, 0) << 16) + phy_read_register (0x03, 0)) & PHYID_VENDOR_MASK;
+	if (phy_id == PHYID_VENDOR_MARVELL) {
+        	printf ("PHY DETECTED ------> MARVELL\n");
+
+        	set_phy_speed (phy_id, PHY_SPEED_1G, DUPLEX_FULL);
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+	        	for (i = 0; i < NUM_TX; i++) {
+				test_result |= packet_test ();
+				if (test_result != 0)
+					break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+        		for (i = 60; i < TX_BUFF_SZ; i++) {
+				test_result |= packet_length_test (i);
+				if (test_result != 0)
+					break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}
+        	set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+        		for (i = 0; i < NUM_TX; i++) {
+				test_result |= packet_test ();
+				if (test_result != 0)
+					break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}
+
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+        		for (i = 60; i < TX_BUFF_SZ; i++) {
+				test_result |= packet_length_test (i);
+        			if (test_result != 0)
+	        	    		break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}
+        }
+	else if ( (phy_id == PHYID_VENDOR_RTL8201E) || (phy_id == PHYID_VENDOR_BROADCOM) ){
+		
+        	if (phy_id == PHYID_VENDOR_RTL8201E)
+        	    printf ("PHY DETECTED ------> RTL 8201E \n");
+        	else if (phy_id == PHYID_VENDOR_BROADCOM)
+        	    printf ("PHY DETECTED ------> Broadcom \n");
+        	
+        	set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+        		for (i = 0; i < NUM_TX; i++) {
+				test_result |= packet_test ();
+				if (test_result != 0)
+					break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}
+
+        	if ((phy_status = MAC1_init (phy_id)) != 0) {
+        		for (i = 60; i < TX_BUFF_SZ; i++) {
+				test_result |= packet_length_test (i);
+        			if (test_result != 0)
+	        	    		break;
+        		}
+        	}
+		else if (phy_status == 0) {
+			printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
+			test_result = 3;
+			return	test_result;
+		}        	
+        }	
+          
+	if ((phy_status == 0) && (test_result & PACKET_TEST_FAIL)) {
+		printf ("Packet Test FAIL !\n");
+	}
+	else if ((phy_status == 0) && (test_result & PACKET_LENGTH_TEST_FAIL)) {
+		printf ("Packet Length Test FAIL !\n");
+	}
+
+	return test_result;
+	
+}
+
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/mactest.h b/board/aspeed/ast2050/mactest.h
new file mode 100644
index 0000000..15f00af
--- /dev/null
+++ b/board/aspeed/ast2050/mactest.h
@@ -0,0 +1,217 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* MACTest.h */
+
+// --------------------------------------------------------------------
+//              General Definition
+// --------------------------------------------------------------------
+#define MAC1_IO_BASE		0x1E660000
+#define PHY_LOOP		100000
+#define NUM_RX			48
+#define NUM_TX			48
+#define RX_BUFF_SZ		1514
+#define TX_BUFF_SZ		1514
+#define TOUT_LOOP		1000000
+#define ETH_ALEN		6
+#define POLL_DEMAND		1
+
+
+// --------------------------------------------------------------------
+//              MAC Register Index
+// --------------------------------------------------------------------
+#define ISR_REG			0x00				// interrups status register
+#define IER_REG			0x04				// interrupt maks register
+#define MAC_MADR_REG		0x08				// MAC address (Most significant)
+#define MAC_LADR_REG		0x0c				// MAC address (Least significant)
+#define MAHT0_REG		0x10				// Multicast Address Hash Table 0 register
+#define MAHT1_REG		0x14				// Multicast Address Hash Table 1 register
+#define TXPD_REG		0x18				// Transmit Poll Demand register
+#define RXPD_REG		0x1c				// Receive Poll Demand register
+#define TXR_BADR_REG		0x20				// Transmit Ring Base Address register
+#define RXR_BADR_REG		0x24				// Receive Ring Base Address register
+#define HPTXPD_REG		0x28
+#define HPTXR_BADR_REG		0x2c
+#define ITC_REG			0x30				// interrupt timer control register
+#define APTC_REG		0x34				// Automatic Polling Timer control register
+#define DBLAC_REG		0x38				// DMA Burst Length and Arbitration control register
+#define DMAFIFOS_REG		0x3c
+#define FEAR_REG		0x44
+#define TPAFCR_REG		0x48
+#define RBSR_REG		0x4c
+#define MACCR_REG		0x50				// MAC control register
+#define MACSR_REG		0x54				// MAC status register
+#define PHYCR_REG		0x60				// PHY control register
+#define PHYDATA_REG		0x64				// PHY Write Data register
+
+// --------------------------------------------------------------------
+//		PHYCR_REG
+// --------------------------------------------------------------------
+#define PHY_RE_AUTO_bit			(1UL<<9)
+#define PHY_READ_bit			(1UL<<26)
+#define PHY_WRITE_bit			(1UL<<27)
+// --------------------------------------------------------------------
+//		PHYCR_REG 
+// --------------------------------------------------------------------
+#define PHY_AUTO_OK_bit			(1UL<<5)
+// --------------------------------------------------------------------
+//		PHY INT_STAT_REG 
+// --------------------------------------------------------------------
+#define PHY_SPEED_CHG_bit		(1UL<<14)
+#define PHY_DUPLEX_CHG_bit		(1UL<<13)
+#define PHY_LINK_CHG_bit		(1UL<<10)
+#define PHY_AUTO_COMP_bit		(1UL<<11)
+// --------------------------------------------------------------------
+//		PHY SPE_STAT_REG 
+// --------------------------------------------------------------------
+#define PHY_RESOLVED_bit		(1UL<<11)
+#define PHY_LINK_bit			(1UL<<10)
+#define PHY_SPEED_mask			0xC000
+#define PHY_SPEED_10M			0x0
+#define PHY_SPEED_100M			0x1
+#define PHY_SPEED_1G			0x2
+#define PHY_DUPLEX_mask                 0x2000
+#define PHY_SPEED_DUPLEX_MASK           0x01E0
+#define PHY_100M_DUPLEX                 0x0100
+#define PHY_100M_HALF                   0x0080
+#define PHY_10M_DUPLEX                  0x0040
+#define PHY_10M_HALF                    0x0020
+#define LINK_STATUS                     0x04
+#define PHYID_VENDOR_MASK		0xfffffc00
+#define PHYID_VENDOR_MARVELL		0x01410c00
+#define PHYID_VENDOR_BROADCOM		0x00406000
+#define PHYID_VENDOR_RTL8201E		0x001cc800
+#define DUPLEX_FULL			0x01
+#define DUPLEX_HALF			0x00
+
+
+
+// --------------------------------------------------------------------
+//		MACCR_REG
+// --------------------------------------------------------------------
+
+#define SW_RST_bit		(1UL<<31)				// software reset/
+#define DIRPATH_bit		(1UL<<21)
+#define RX_IPCS_FAIL_bit	(1UL<<20)
+#define SPEED_100M_MODE_bit		(1UL<<19)
+#define RX_UDPCS_FAIL_bit	(1UL<<18)
+#define RX_BROADPKT_bit		(1UL<<17)				// Receiving broadcast packet
+#define RX_MULTIPKT_bit		(1UL<<16)				// receiving multicast packet
+#define RX_HT_EN_bit		(1UL<<15)
+#define RX_ALLADR_bit		(1UL<<14)				// not check incoming packet's destination address
+#define JUMBO_LF_bit		(1UL<<13)
+#define RX_RUNT_bit		(1UL<<12)				// Store incoming packet even its length is les than 64 byte
+#define CRC_CHK_bit		(1UL<<11)
+#define CRC_APD_bit		(1UL<<10)				// append crc to transmit packet
+#define GMAC_MODE_bit		(1UL<<9)
+#define FULLDUP_bit		(1UL<<8)				// full duplex
+#define ENRX_IN_HALFTX_bit	(1UL<<7)
+#define LOOP_EN_bit		(1UL<<6)				// Internal loop-back
+#define HPTXR_EN_bit		(1UL<<5)
+#define REMOVE_VLAN_bit		(1UL<<4)
+#define RXMAC_EN_bit		(1UL<<3)				// receiver enable
+#define TXMAC_EN_bit		(1UL<<2)				// transmitter enable
+#define RXDMA_EN_bit		(1UL<<1)				// enable DMA receiving channel
+#define TXDMA_EN_bit		(1UL<<0)				// enable DMA transmitting channel
+
+
+// --------------------------------------------------------------------
+//		SCU_REG
+// --------------------------------------------------------------------
+#define  SCU_BASE			0x1E6E2000
+#define  SCU_PROTECT_KEY_REG            0x0
+#define  SCU_PROT_KEY_MAGIC             0x1688a8a8
+#define  SCU_RESET_CONTROL_REG          0x04
+#define  SCU_RESET_MAC1                 (1u << 11)
+#define  SCU_RESET_MAC2                 (1u << 12)
+#define  SCU_HARDWARE_TRAPPING_REG      0x70
+#define  SCU_HT_MAC_INTF_LSBIT          6
+#define  SCU_HT_MAC_INTERFACE           (0x7u << SCU_HT_MAC_INTF_LSBIT)
+#define  MAC_INTF_SINGLE_PORT_MODES     (1u<<0/*GMII*/ | 1u<<3/*MII_ONLY*/ | 1u<<4/*RMII_ONLY*/)
+#define  SCU_HT_MAC_GMII                0x0u
+// MII and MII mode
+#define  SCU_HT_MAC_MII_MII             0x1u
+#define  SCU_HT_MAC_MII_ONLY            0x3u
+#define  SCU_HT_MAC_RMII_ONLY           0x4u
+#define  SCU_MULTIFUNCTION_PIN_REG      0x74
+#define  SCU_MFP_MAC2_PHYLINK           (1u << 26)
+#define  SCU_MFP_MAC1_PHYLINK           (1u << 25)
+#define  SCU_MFP_MAC2_MII_INTF          (1u << 21)
+#define  SCU_MFP_MAC2_MDC_MDIO          (1u << 20)
+#define  SCU_SILICON_REVISION_REG       0x7C
+
+//---------------------------------------------------
+//  PHY R/W Register Bit
+//---------------------------------------------------
+#define MIIWR                   (1UL<<27)
+#define MIIRD                   (1UL<<26)
+#define MDC_CYCTHR              0x34
+#define PHY_SPEED_MASK          0xC000
+#define PHY_DUPLEX_MASK         0x2000
+#define SPEED_1000M             0x02
+#define SPEED_100M              0x01
+#define SPEED_10M               0x00
+#define DUPLEX_FULL             0x01
+#define DUPLEX_HALF             0x00
+#define RESOLVED_BIT            0x800
+
+#define PHY_SPEED_DUPLEX_MASK   0x01E0
+#define PHY_100M_DUPLEX         0x0100
+#define PHY_100M_HALF           0x0080
+#define PHY_10M_DUPLEX          0x0040
+#define PHY_10M_HALF            0x0020
+
+//---------------------------------------------------
+// Descriptor bits.
+//---------------------------------------------------
+#define TXDMA_OWN	0x80000000	/* Own Bit */
+#define RXPKT_RDY       0x00000000      
+#define RXPKT_STATUS    0x80000000
+#define EDORR		0x40000000	/* Receive End Of Ring */
+#define LRS		0x10000000	/* Last Descriptor */
+#define RD_ES		0x00008000	/* Error Summary */
+#define EDOTR		0x40000000	/* Transmit End Of Ring */
+#define T_OWN		0x80000000	/* Own Bit */
+#define LTS		0x10000000	/* Last Segment */
+#define FTS		0x20000000	/* First Segment */
+#define CRC_ERR         0x00080000
+#define TD_ES		0x00008000	/* Error Summary */
+#define TD_SET		0x08000000	/* Setup Packet */
+#define RX_ERR          0x00040000
+#define FTL             0x00100000
+#define RUNT            0x00200000
+#define RX_ODD_NB       0x00400000
+#define BYTE_COUNT_MASK 0x00003FFF
+
+//---------------------------------------------------
+// SPEED/DUPLEX Parameters
+//---------------------------------------------------
+
+//---------------------------------------------------
+// Return Status
+//---------------------------------------------------
+#define TEST_PASS			0
+#define PACKET_TEST_FAIL		1
+#define PACKET_LENGTH_TEST_FAIL		2
+
+struct  mac_desc {
+	volatile s32 status;
+	u32 des1;
+	u32 reserved;
+	u32 buf;	
+};
+static struct mac_desc rx_ring[NUM_RX] __attribute__ ((aligned(32))); /* RX descriptor ring         */
+static struct mac_desc tx_ring[NUM_TX] __attribute__ ((aligned(32))); /* TX descriptor ring         */
+static int rx_new;                             /* RX descriptor ring pointer */
+static int tx_new;                             /* TX descriptor ring pointer */
+static volatile unsigned char rx_buffer[NUM_RX][RX_BUFF_SZ] __attribute__ ((aligned(32))); /* RX buffer         */
+static volatile unsigned char tx_buffer[NUM_TX][TX_BUFF_SZ] __attribute__ ((aligned(32))); /* TX buffer         */
diff --git a/board/aspeed/ast2050/mictest.c b/board/aspeed/ast2050/mictest.c
new file mode 100644
index 0000000..86cc9e4
--- /dev/null
+++ b/board/aspeed/ast2050/mictest.c
@@ -0,0 +1,148 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Diagnostics support
+ */
+#include <common.h>
+#include <command.h>
+#include <post.h>
+#include "slt.h"
+
+#if ((CFG_CMD_SLT & CFG_CMD_MICTEST) && defined(CONFIG_SLT))
+#include "mictest.h"
+
+static unsigned char ctrlbuf[MIC_MAX_CTRL];
+static unsigned char chksumbuf[MIC_MAX_CHKSUM];
+
+void vInitSCU(void)
+{
+    unsigned long ulData;
+
+    *(unsigned long *) (0x1e6e2000) = 0x1688A8A8;
+
+    udelay(100);
+
+    ulData = *(unsigned long *) (0x1e6e2004);
+    ulData &= 0xbffff;
+    *(unsigned long *) (0x1e6e2004) = ulData;
+         	
+}
+
+void vInitMIC(void)
+{
+    unsigned long i, j, ulPageNumber;
+    unsigned char *pjctrl, *pjsum;
+    
+    ulPageNumber = DRAMSIZE >> 12;	
+
+    pjctrl = (unsigned char *)(m16byteAlignment((unsigned long) ctrlbuf));
+    pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
+    
+    /* init ctrl buffer (2bits for one page) */
+    for (i=0; i< (ulPageNumber/4); i++)
+        *(unsigned char *) (pjctrl + i) = DEFAULT_CTRL;
+      
+    /* init chksum buf (4bytes for one page) */
+    for (i=0; i<ulPageNumber; i++)
+        *(unsigned long *) (pjsum + i*4) = DEFAULT_CHKSUM;
+    
+    *(unsigned long *) (MIC_BASE + MIC_CTRLBUFF_REG)   = (unsigned long) pjctrl;
+    *(unsigned long *) (MIC_BASE + MIC_CHKSUMBUF_REG)  = (unsigned long) pjsum;
+    *(unsigned long *) (MIC_BASE + MIC_RATECTRL_REG)   = (unsigned long) DEFAULT_RATE;
+    *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG) = MIC_ENABLE_MIC | (DRAMSIZE - 0x1000);
+	
+}
+
+void vDisableMIC(void)
+{
+    *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG)   = MIC_RESET_MIC;
+	
+}
+
+int do_chksum(void)
+{
+    unsigned long i, j, k, ulPageNumber;
+    int Status = 0;
+    unsigned short tmp;
+    volatile unsigned long sum1, sum2;
+    unsigned long goldensum, chksum;
+    unsigned long len, tlen;
+    unsigned char *pjsum;
+
+    ulPageNumber = DRAMSIZE >> 12;	
+    pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
+
+    /* start test */    
+    for (i=0; i<ulPageNumber; i++)
+    {
+    	
+    	sum1 = 0xffff, sum2 = 0xffff;
+    	len = 0x0800;
+    	j = 0;
+    	
+    	while (len)
+    	{
+    	    tlen = len > 360 ? 360 : len;
+    	    len -= tlen;
+    	    do {
+    	       tmp = *(unsigned short *) (DRAM_BASE + ((i << 12) + j));	
+               sum1 += (unsigned long) tmp;   	    	
+    	       sum2 += sum1;
+    	       j+=2;
+    	    } while (--tlen);
+    	    sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+    	    sum2 = (sum2 & 0xffff) + (sum2 >> 16);   	        	
+    	}
+    	
+    	sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+    	sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+    	
+    	goldensum = (sum2 << 16) | sum1;
+        k= 0;
+        do {
+            chksum = *(unsigned long *) (pjsum + i*4);
+            udelay(100);
+            k++;
+    	} while ((chksum == 0) && (k<1000));
+    	
+    	if (chksum != goldensum)
+    	{
+    	        Status = 1;	
+                printf("[FAIL] MIC Chksum Failed at Page %x \n", i);
+    	}
+
+    } /* end of i loop */
+		
+    return (Status);
+    	
+}
+
+int do_mictest (void)
+{
+        unsigned long Flags = 0;
+
+        vInitSCU();
+        vInitMIC();
+        
+        if (do_chksum())
+            Flags = 1;
+            
+        vDisableMIC();
+        
+	return Flags;
+	
+}
+
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/mictest.h b/board/aspeed/ast2050/mictest.h
new file mode 100644
index 0000000..bc6fcae
--- /dev/null
+++ b/board/aspeed/ast2050/mictest.h
@@ -0,0 +1,57 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Macro */
+#define m08byteAlignment(x)		((x + 0x00000007) & 0xFFFFFFF8)
+#define m16byteAlignment(x)		((x + 0x0000000F) & 0xFFFFFFF0)
+#define m64byteAlignment(x)		((x + 0x0000003F) & 0xFFFFFFC0)
+
+/* Options */
+#define MIC_TEST_PAGE		32
+#define DRAMSIZE		(MIC_TEST_PAGE * 0x1000)
+#define MIC_MAX_CTRL		(MIC_TEST_PAGE / 4 + 16)
+#define MIC_MAX_CHKSUM		(MIC_TEST_PAGE * 4 + 16)
+
+/* Default Setting */
+#define DEFAULT_RATE		0x00000000
+#define DEFAULT_CTRL		0xFF
+#define DEFAULT_CHKSUM		0x00000000
+#define DEFAULT_WRITEBACK	0x08880000
+
+/* Reg. Definition */
+#define DRAM_BASE		0x40000000
+#define MIC_BASE		0x1e640000
+#define MIC_CTRLBUFF_REG	0x00
+#define MIC_CHKSUMBUF_REG	0x04
+#define MIC_RATECTRL_REG	0x08
+#define MIC_ENGINECTRL_REG	0x0C
+#define MIC_STOPPAGE_REG	0x10
+#define MIC_STATUS_REG		0x14
+#define MIC_STATUS1_REG		0x18
+#define MIC_STATUS2_REG		0x1C
+
+#define MIC_RESET_MIC		0x00000000
+#define MIC_ENABLE_MIC		0x10000000
+#define MIC_MAXPAGE_MASK	0x0FFFF000
+#define MIC_WRITEBACK_MASK	0xFFFF0000
+#define MIC_STOPPAGE_MASK	0x0000FFFF
+#define MIC_PAGEERROR		0x40000000
+#define MIC_PAGE1ERROR		0x10000000
+#define MIC_PAGE2ERROR		0x20000000
+#define MIC_INTMASK		0x00060000
+#define MIC_ERRPAGENO_MASK	0x0000FFFF
+
+#define MIC_CTRL_MASK		0x03
+#define MIC_CTRL_SKIP		0x00
+#define MIC_CTRL_CHK1		0x01
+#define MIC_CTRL_CHK2		0x02
+#define MIC_CTRL_CHK3		0x03
diff --git a/board/aspeed/ast2050/pci.c b/board/aspeed/ast2050/pci.c
new file mode 100644
index 0000000..b9c8cbb
--- /dev/null
+++ b/board/aspeed/ast2050/pci.c
@@ -0,0 +1,245 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_PCI
+
+#define PCI_CSR_BASE		0x60000000
+#define ASPEED_PCI_IO_BASE	0x00000000
+#define ASPEED_PCI_IO_SIZE	0x00010000
+#define ASPEED_PCI_MEM_BASE	0x68000000
+#define ASPEED_PCI_MEM_SIZE	0x18000000
+
+#define CSR_CRP_CMD_OFFSET	0x00
+#define CSR_CRP_WRITE_OFFSET    0x04
+#define CSR_CRP_READ_OFFSET	0x08
+#define CSR_PCI_ADDR_OFFSET	0x0C
+#define CSR_PCI_CMD_OFFSET	0x10
+#define CSR_PCI_WRITE_OFFSET	0x14
+#define CSR_PCI_READ_OFFSET	0x18
+#define CSR_PCI_STATUS_OFFSET	0x1C
+
+#define CRP_ADDR_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_CRP_CMD_OFFSET)
+#define CRP_WRITE_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_CRP_WRITE_OFFSET)
+#define CRP_READ_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_CRP_READ_OFFSET)
+#define PCI_ADDR_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_ADDR_OFFSET)
+#define PCI_CMD_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_CMD_OFFSET)
+#define PCI_WRITE_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_WRITE_OFFSET)
+#define PCI_READ_REG		(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_READ_OFFSET)
+
+#define PCI_CMD_READ		0x0A
+#define PCI_CMD_WRITE		0x0B
+
+#define RESET_PCI_STATUS        *(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) = 0x01
+#define CHK_PCI_STATUS          (*(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) & 0x03)
+
+static int pci_config_access (u8 access_type, u32 dev, u32 reg, u32 * data)
+{
+	u32 bus;
+	u32 device;
+	u32 function;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+	function = (dev & 0x0700);
+
+	if (bus == 0) {
+		// Type 0 Configuration 		
+		*PCI_ADDR_REG = (u32) (1UL << device | function | (reg & 0xfc));
+	} else {
+		// Type 1 Configuration 
+		*PCI_ADDR_REG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+        RESET_PCI_STATUS;
+        
+	if (access_type == PCI_CMD_WRITE) {
+		*PCI_CMD_REG = (ulong) PCI_CMD_WRITE;
+		*PCI_WRITE_REG = *data;
+	} else {
+		*PCI_CMD_REG = (ulong) PCI_CMD_READ;		
+		*data = *PCI_READ_REG;
+	}
+            
+	return (CHK_PCI_STATUS);
+}
+
+static int aspeed_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
+		*val = 0;
+		return -1;
+	}	
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int aspeed_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
+		*val = 0;
+		return -1;
+	} 		
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int aspeed_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (pci_config_access (PCI_CMD_READ, dev, reg, &data))	{
+		*val = 0;
+		return -1;
+	}		
+
+	*val = data;
+
+	return (0);
+}
+
+static int aspeed_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int aspeed_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int aspeed_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+/*
+ *	Initialize PCIU
+ */
+aspeed_pciu_init ()
+{
+
+    unsigned long reg;
+
+    /* Reset PCI Host */
+    reg = *((volatile ulong*) 0x1e6e2004);
+    *((volatile ulong*) 0x1e6e2004) = reg | 0x00280000;
+
+    reg = *((volatile ulong*) 0x1e6e2074);		/* REQ2 */    
+    *((volatile ulong*) 0x1e6e2074) = reg | 0x00000010;
+
+    *((volatile ulong*) 0x1e6e2008) |= 0x00080000;        
+    reg = *((volatile ulong*) 0x1e6e200c); 
+    *((volatile ulong*) 0x1e6e200c) = reg & 0xfff7ffff;
+    udelay(1); 
+    *((volatile ulong*) 0x1e6e2004) &= 0xfff7ffff;
+                 
+    /* Initial PCI Host */
+    RESET_PCI_STATUS;
+	
+    *CRP_ADDR_REG = ((ulong)(PCI_CMD_READ) << 16) | 0x04;
+    reg = *CRP_READ_REG;
+    
+    *CRP_ADDR_REG = ((ulong)(PCI_CMD_WRITE) << 16) | 0x04;
+    *CRP_WRITE_REG = reg | 0x07;
+   
+}
+
+/*
+ *	Initialize Module
+ */
+
+void aspeed_init_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	aspeed_pciu_init ();			/* Initialize PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 1,
+			ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_SIZE, PCI_REGION_IO);
+
+	hose->region_count = 2;
+
+	hose->read_byte   = aspeed_pci_read_config_byte;
+	hose->read_word   = aspeed_pci_read_config_word;
+	hose->read_dword  = aspeed_pci_read_config_dword;
+	hose->write_byte  = aspeed_pci_write_config_byte;
+	hose->write_word  = aspeed_pci_write_config_word;
+	hose->write_dword = aspeed_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}
+#endif /* CONFIG_PCI */
+
diff --git a/board/aspeed/ast2050/platform.S b/board/aspeed/ast2050/platform.S
new file mode 100644
index 0000000..05e356c
--- /dev/null
+++ b/board/aspeed/ast2050/platform.S
@@ -0,0 +1,603 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * Board specific setup info
+ *
+ ******************************************************************************
+ * ASPEED Technology Inc.
+ * AST2050 DDR2 SDRAM controller initialization and calibration sequence
+ *
+ * Audrey Pearson <apearson@raptorengineeringinc.com>
+ * modified from DDR3/DDR2 ctrlr init and calib from
+ * Gary Hsu, <gary_hsu@aspeedtech.com>
+ *
+ * Release date: 2014.12.29 formal release for SDK0.60
+ *
+ * Optional define variable
+ * 1. UART5 message output   //
+ *    CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ ******************************************************************************
+ */
+
+#include <config.h>
+#include <version.h>
+#include "hwreg.h"
+/******************************************************************************
+ Calibration Macro Start
+ Usable registers:
+  r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11
+ ******************************************************************************/
+/* PATTERN_TABLE,
+   init_delay_timer,
+   check_delay_timer,
+   clear_delay_timer,
+   are for DRAM calibration */
+
+PATTERN_TABLE:
+    .word   0xff00ff00
+    .word   0xcc33cc33
+    .word   0xaa55aa55
+    .word   0x88778877
+    .word   0x92cc4d6e       @ 5
+    .word   0x543d3cde
+    .word   0xf1e843c7
+    .word   0x7c61d253
+    .word   0x00000000       @ 8
+
+    .macro init_delay_timer
+    ldr r0, =0x1e782024                          @ Set Timer3 Reload
+    str r2, [r0]
+
+    ldr r0, =0x1e6c0038                          @ Clear Timer3 ISR
+    ldr r1, =0x00040000
+    str r1, [r0]
+
+    ldr r0, =TIMER_CONTROL_REG                          @ Enable Timer3
+    ldr r1, [r0]
+    mov r2, #7
+    orr r1, r1, r2, lsl #8
+    str r1, [r0]
+
+    ldr r0, =0x1e6c0008                          @ Check ISR for Timer3 timeout
+    .endm
+
+    .macro check_delay_timer
+    ldr r1, [r0]
+    bic r1, r1, #0xFFFBFFFF
+    mov r2, r1, lsr #18
+    cmp r2, #0x01
+    .endm
+
+    .macro clear_delay_timer
+    ldr r0, =TIMER_CONTROL_REG                          @ Disable Timer3
+    ldr r1, [r0]
+    bic r1, r1, #0x00000F00
+    str r1, [r0]
+
+    ldr r0, =0x1e6c0038                          @ Clear Timer3 ISR
+    ldr r1, =0x00040000
+    str r1, [r0]
+    .endm
+
+/******************************************************************************
+ Calibration Macro End
+ ******************************************************************************/
+LPC_Patch:                                       @ load to SRAM base 0x1e720400
+    str   r1, [r0]
+    str   r3, [r2]
+    bic   r1, r1, #0xFF
+LPC_Patch_S1:
+    subs  r5, r5, #0x01
+    moveq pc, r8
+    ldr   r3, [r2]
+    tst   r3, #0x01
+    movne pc, r8
+    mov   pc, r7
+LPC_Patch_S2:                                    @ load to SRAM base 0x1e720480
+    str   r1, [r0]
+    mov   pc, r9
+LPC_Patch_E:
+
+.globl lowlevel_init
+lowlevel_init:
+
+init_dram:
+    /* save lr (link register, holds return addr for fcn call) */
+    mov r4, lr
+/* Test - DRAM initial timer */
+    ldr r0, =0x1e782044
+    ldr r1, =0xFFFFFFFF
+    str r1, [r0]
+
+    ldr r0, =TIMER_CONTROL_REG
+    ldr r1, [r0]
+    bic r1, r1, #0x0000F000
+    str r1, [r0]
+    mov r2, #3
+    orr r1, r1, r2, lsl #12
+    str r1, [r0]
+/* Test - DRAM initial timer */
+
+    /*Set Scratch register Bit 7 before initialize*/
+    ldr r0, =AST_SCU_BASE        /* 1E6E:2000 */
+    ldr r1, =0x1688a8a8
+    str r1, [r0]
+
+    ldr r0, =SCU_SOC_SCRATCH1_REG   /* 1E6E:2040 */
+    ldr r1, [r0]
+    orr r1, r1, #0x80
+    str r1, [r0]
+
+    /* Check Scratch Register Bit 6 */
+    ldr r0, =SCU_SOC_SCRATCH1_REG   /* 1E6E:2040 */
+    ldr r1, [r0]
+    bic r1, r1, #0xFFFFFFBF
+    mov r2, r1, lsr #6
+    cmp r2, #0x01
+    beq reg_lock				@ exit
+
+    ldr r2, =0x033103F1                          @ load PLL parameter for 24Mhz CLKIN (396:324)
+    ldr r0, =SCU_REV_ID_REG                          @ Check Revision ID
+    ldr r1, [r0]
+    mov r1, r1, lsr #8
+    cmp r1, #0x02
+    beq set_MPLL                                 @ match AST2050/AST1100
+
+set_MPLL:
+    ldr r0, =SCU_M_PLL_PARAM_REG            @ 1E6E:2020 M-PLL (DDR SDRAM) Frequency
+    ldr r1, =0x00004c81			@ 200 MHz
+    str r1, [r0]
+
+/* Debug - UART console message */
+    ldr r0, =UART2_LINE_CTRL_REG		@ 0x1e78400c
+    mov r1, #0x83
+    str r1, [r0]
+
+    ldr r0, =SCU_FREQ_CNTR_CTRL_RANGE_REG	@ 0x1e6e202c
+    ldr r2, [r0]
+    mov r2, r2, lsr #12
+    tst r2, #0x01
+    ldr r0, =UART2_REC_BUFF_REG			@ 0x1e784000
+    moveq r1, #0x0D                              @ Baudrate 115200
+    movne r1, #0x01                              @ Baudrate 115200, div13
+#if defined(CONFIG_DRAM_UART_38400)
+    moveq r1, #0x27                              @ Baudrate 38400
+    movne r1, #0x03                              @ Baudrate 38400 , div13
+#endif
+    str r1, [r0]
+
+    ldr r0, =UART2_INT_EN_REG			@ 0x1e784004
+    mov r1, #0x00
+    str r1, [r0]
+
+    ldr r0, =UART2_LINE_CTRL_REG		@ 0x1e78400c
+    mov r1, #0x03
+    str r1, [r0]
+
+    ldr r0, =UART2_INT_IDENT_REG		@ 0x1e784008
+    mov r1, #0x07
+    str r1, [r0]
+
+    ldr r0, =UART2_REC_BUFF_REG			@ 0x1e784000
+    mov r1, #0x0D                                @ '\r'
+    str r1, [r0]
+    mov r1, #0x0A                                @ '\n'
+    str r1, [r0]
+    mov r1, #0x44                                @ 'D'
+    str r1, [r0]
+    mov r1, #0x52                                @ 'R'
+    str r1, [r0]
+    mov r1, #0x41                                @ 'A'
+    str r1, [r0]
+    mov r1, #0x4D                                @ 'M'
+    str r1, [r0]
+    mov r1, #0x20                                @ ' '
+    str r1, [r0]
+    mov r1, #0x49                                @ 'I'
+    str r1, [r0]
+    mov r1, #0x6E                                @ 'n'
+    str r1, [r0]
+    mov r1, #0x69                                @ 'i'
+    str r1, [r0]
+    mov r1, #0x74                                @ 't'
+    str r1, [r0]
+    mov r1, #0x2D                                @ '-'
+    str r1, [r0]
+    mov r1, #0x44                                @ 'D'
+    str r1, [r0]
+    mov r1, #0x44                                @ 'D'
+    str r1, [r0]
+    mov r1, #0x52                                @ 'R'
+    str r1, [r0]
+    mov r1, #0x0D                                @ '\r'
+    str r1, [r0]
+    mov r1, #0x0A                                @ '\n'
+    str r1, [r0]
+/* Debug - UART console message */
+
+    /* Delay about 100us */
+    ldr r2, =0x00000100
+delay0:
+    nop
+    nop
+    subs r2, r2, #1          /* until source end addreee [r2]    */
+    bne delay0
+
+
+/******************************************************************************
+ Init DRAM
+ ******************************************************************************/
+    ldr r0, =SCU_KEY_CONTROL_REG
+    ldr r1, =0x1688A8A8				@ Unlock SCU registers
+    str r1, [r0]
+
+    ldr r0, =SCU_KEY_CONTROL_REG
+    ldr r1, [r0]
+    cmp r1, #0x01
+    bne SCU_regs_locked				@ Still locked. Display error and terminate
+    b SCU_regs_unlocked				@ otherwise continue
+
+    /* ERROR MESSAGES */
+SCU_regs_locked:
+    /* Debug - UART console message */
+    ldr r0, =UART2_REC_BUFF_REG			@ 0x1e784000
+    mov r1, #0x53				@ 'S'
+    str r1, [r0]
+    mov r1, #0x43				@ 'C'
+    str r1, [r0]
+    mov r1, #0x55				@ 'U'
+    str r1, [r0]
+    mov r1, #0x20				@ ' '
+    str r1, [r0]
+    mov r1, #0x4c				@ 'L'
+    str r1, [r0]
+    mov r1, #0x4f				@ 'O'
+    str r1, [r0]
+    mov r1, #0x43				@ 'C'
+    str r1, [r0]
+    mov r1, #0x4b				@ 'K'
+    str r1, [r0]
+    mov r1, #0x45				@ 'E'
+    str r1, [r0]
+    mov r1, #0x44				@ 'D'
+    str r1, [r0]
+    mov r1, #0x0D				@ '\r'
+    str r1, [r0]
+    mov r1, #0x0A				@ '\n'
+    str r1, [r0]
+    /* Debug - UART console message */
+    b reg_lock					@terminate
+.LTORG
+
+SCU_regs_unlocked:				@ continue
+    ldr r0, =SCU_SOC_SCRATCH1_REG		@ SCU40
+    ldr r1, =0x5a000080				@ Set Linux boot key and indicate firmware will initialize DRAM
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PROTECTION_KEY_REG
+    ldr r1, =0xfc600309				@ Unlock SDRAM registers
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PROTECTION_KEY_REG
+    ldr r1, [r0]
+    cmp r1, #0x01
+    bne SDRAM_regs_locked				@ Still locked. Display error and terminate
+    b SDRAM_regs_unlocked				@ otherwise continue
+
+
+SDRAM_regs_locked:
+    /* Debug - UART console message */
+    ldr r0, =UART2_REC_BUFF_REG			@ 0x1e784000
+    mov r1, #0x53				@ 'S'
+    str r1, [r0]
+    mov r1, #0x44				@ 'D'
+    str r1, [r0]
+    mov r1, #0x52				@ 'R'
+    str r1, [r0]
+    mov r1, #0x41				@ 'A'
+    str r1, [r0]
+    mov r1, #0x4d				@ 'M'
+    str r1, [r0]
+    mov r1, #0x20				@ ' '
+    str r1, [r0]
+    mov r1, #0x4c				@ 'L'
+    str r1, [r0]
+    mov r1, #0x4f				@ 'O'
+    str r1, [r0]
+    mov r1, #0x43				@ 'C'
+    str r1, [r0]
+    mov r1, #0x4b				@ 'K'
+    str r1, [r0]
+    mov r1, #0x45				@ 'E'
+    str r1, [r0]
+    mov r1, #0x44				@ 'D'
+    str r1, [r0]
+    mov r1, #0x0D				@ '\r'
+    str r1, [r0]
+    mov r1, #0x0A				@ '\n'
+    str r1, [r0]
+    /* Debug - UART console message */
+    b reg_lock					@terminate
+.LTORG
+
+SDRAM_regs_unlocked:				@continue
+    ldr r0, =SCU_KEY_CONTROL_REG
+    ldr r1, =0x1688a8a8			@ unlock scu registers (again, apparently?)
+    str r1, [r0]
+
+    ldr r0, =SCU_M_PLL_PARAM_REG	@ 0x1e6e:2020 (SCU20)
+    ldr r1, =0x000041f0			@ MPLL params: output denumerator=0b0000; output divider=1; numerator=0b001111; post divider=div by 2 
+    str r1, [r0]
+
+    /* Delay about 400us */
+    ldr r2, =0x00000400
+delay1:
+    nop
+    nop
+    subs r2, r2, #1          /* until source end addreee [r2]    */
+    bne delay1
+
+    ldr r0, =SDRAM_PROTECTION_KEY_REG
+    ldr r1, =0xfc600309		@ unlock sdram registers
+    str r1, [r0]
+
+    ldr r0, =SDRAM_DLL_CTRL_REG3		@ DLL ctrl reg #3
+    ldr r1, =0x00909090
+    str r1, [r0]
+
+    ldr r0, =SDRAM_DLL_CTRL_REG1		@ DLL ctrl reg #1
+    ldr r1, =0x00050000
+    str r1, [r0]
+
+
+    ldr r0, =SCU_HW_STRAPPING_REG     		@ SCU70 bits 3:2 - VGA memory size selection
+    ldr r1, [r0]
+    ldr r2, =0x0000000c
+    and	r1, r1, r2
+    mov	r2, r1, lsl #2
+
+    ldr r0, =SDRAM_CONFIG_REG               @ MCR04 - Config register
+#ifdef CONFIG_1G_DDRII
+    ldr r1, =0x00000d89
+#endif
+#ifdef CONFIG_512M_DDRII
+    ldr r1, =0x00000585
+#endif
+    orr r1, r1, r2
+    str r1, [r0]
+
+    ldr r0, =SDRAM_GRAP_MEM_PROTECTION_REG  	@ 1E6E:0008  MCR8: Graphics memory protection reg
+    ldr r1, =0x0011030f
+    str r1, [r0]
+
+    ldr r0, =SDRAM_NSPEED_REG1              @ 1E6E:0010  @ MCR10: Normal Speed AC Timing Register #1
+    ldr r1, =0x22201725
+    str r1, [r0]
+
+    ldr r0, =SDRAM_NSPEED_REG2              @ 1E6E:0018	@ MCR18: Normal Speed AC Timing Register #2
+    ldr r1, =0x1e29011a
+    str r1, [r0]
+
+    ldr r0, =SDRAM_NSPEED_DELAY_CTRL_REG    @ 1E6E:0020	@ MCR20: Normal Speed Delay Control Register
+    ldr r1, =0x00c82222
+    str r1, [r0]
+
+    ldr r0, =SDRAM_LSPEED_REG1              @ 1E6E:0014 @ MCR14: Low Speed AC Timing Register #1
+    ldr r1, =0x22201725
+    str r1, [r0]
+
+    ldr r0, =SDRAM_LSPEED_REG2              @ 1E6E:001c @ MCR1c: Low Speed AC Timing Register #2
+    ldr r1, =0x1e29011a
+    str r1, [r0]
+
+    ldr r0, =SDRAM_LSPEED_DELAY_CTRL_REG    @ 1E6E:0024 @ MCR24: Low Speed Delay Control Register
+    ldr r1, =0x00c82222
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PAGE_MISS_LATENCY_MASK_REG	@ 1E6E:0038 @ MCR38: Page Miss Latency Mask Register
+    ldr r1, =0xffffff82
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PRIORITY_GROUP_SET_REG	@ 1E6E:003C @ MCR3C: Priority Group Setting Register
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MAX_GRANT_LENGTH_REG1    @ 1E6E:0040 @ MCR40: Maximum Grant Length Register #1
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MAX_GRANT_LENGTH_REG2    @ 1E6E:0044	@ MCR44: Maximum Grant Length Register #2
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MAX_GRANT_LENGTH_REG3    @ 1E6E:0048 @ MCR48: Maximum Grant Length Register #3
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =0x1e6e004c	@ 1E6E:004c @ MCR4C 
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_ECC_CTRL_STATUS_REG	@ 1E6E:0050 @ MCR50: 
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_ECC_SEGMENT_EN_REG	@ 1E6E:0054 @ MCR54: 
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_ECC_SCRUB_REQ_MASK_CTRL_REG	@ 1E6E:0058 @ MCR58: 
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_ECC_ADDR_FIRST_ERR_REG	@ 1E6E:005C @ MCR5C: 
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_IO_BUFF_MODE_REG         @ 1E6E:0060 @ MCR60: IO Buffer Mode Register
+    ldr r1, =0x032aa02a
+    str r1, [r0]
+
+    ldr r0, =SDRAM_DLL_CTRL_REG1            @ 1E6E:0064 @ MCR64: DLL Control Register #1
+    ldr r1, =0x002d3000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_DLL_CTRL_REG2            @ 1E6E:0068 @ MCR68: DLL Control Register #2
+    ldr r1, =0x02020202
+    str r1, [r0]
+
+    ldr r0, =SDRAM_TEST_CTRL_STATUS_REG     @ 1E6E:0070 @ MCR70: Testing Control/Status Register
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_TEST_START_ADDR_LENGTH_REG   @ 1E6E:0074 @ MCR74: Testing Start Address and Length Register
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_TEST_FAIL_DQ_BIT_REG     @ 1E6E:0078 @ MCR78: Testing Fail DQ Bit Register
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_TEST_INIT_VALUE_REG      @ 1E6E:007C @ MCR7C: Test Initial Value Register
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PWR_CTRL_REG             @ 1E6E:0034 @ MCR34: Power Control Register
+    ldr r1, =0x00000001
+    str r1, [r0]
+
+    ldr r2, =0x00000400
+delay2:
+    nop
+    nop
+    subs r2, r2, #1          /* until source end addreee [r2]    */
+    bne delay2
+
+    ldr r0, =SDRAM_MRS_EMRS2_MODE_SET_REG		@ MCR2c: MRS/EMRS2 Mode Setting Register
+    ldr r1, =0x00000732
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MRS_EMRS3_MODE_SET_REG		@ MCR30: EMRS/EMRS3 Mode Setting Register
+    ldr r1, =0x00000040
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000005
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000007
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000003
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000001
+    str r1, [r0]
+
+    ldr r0, =SDRAM_REFRESH_TIMING_REG		@ MCR0C: Refresh Timing Register
+    ldr r1, =0x00005a08
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MRS_EMRS2_MODE_SET_REG		@ MCR2C: MRS/EMRS2 Mode Setting Register
+    ldr r1, =0x00000632
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000001
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MRS_EMRS3_MODE_SET_REG		@ MCR30: EMRS/EMRS3 Mode Setting Register
+    ldr r1, =0x000003c0
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000003
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MRS_EMRS3_MODE_SET_REG		@ MCR30: EMRS/EMRS3 Mode Setting Register
+    ldr r1, =0x00000040
+    str r1, [r0]
+
+    ldr r0, =SDRAM_MODE_SET_CTRL_REG		@ MCR28: Mode Setting Control Register
+    ldr r1, =0x00000003
+    str r1, [r0]
+
+    ldr r0, =SDRAM_REFRESH_TIMING_REG		@ MCR0C: Refresh Timing Register
+    ldr r1, =0x00005a21
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PWR_CTRL_REG			@ MCR34: Power Control Register
+    ldr r1, =0x00007c03
+    str r1, [r0]
+
+    ldr r0, =AST2100_COMPATIBLE_SCU_MPLL_PARA	@ MCR120: AST2000 Backward compatible SCU MPLL Parameter
+    ldr r1, =0x00004c41
+    str r1, [r0]
+
+@ end
+
+    b set_scratch					@ set success flag and terminate
+.LTORG
+
+/******************************************************************************
+ End DRAM Init
+ ******************************************************************************/
+
+set_scratch:
+    /*Set Scratch register Bit 6 after ddr initial finished */
+    ldr r0, =SCU_SOC_SCRATCH1_REG		@ SCU40
+    ldr r1, [r0]
+    orr r1, r1, #0x40
+    str r1, [r0]
+
+    /* Debug - UART console message */
+    ldr r0, =UART2_REC_BUFF_REG			 @ 0x1e784000
+    mov r1, #0x2e                                @ '.'
+    str r1, [r0]
+    mov r1, #0x2e                                @ '.'
+    str r1, [r0]
+    mov r1, #0x2e                                @ '.'
+    str r1, [r0]
+    mov r1, #0x44                                @ 'D'
+    str r1, [r0]
+    mov r1, #0x6F                                @ 'o'
+    str r1, [r0]
+    mov r1, #0x6E                                @ 'n'
+    str r1, [r0]
+    mov r1, #0x65                                @ 'e'
+    str r1, [r0]
+    mov r1, #0x0D                                @ '\r'
+    str r1, [r0]
+    mov r1, #0x0A                                @ '\n'
+    str r1, [r0]
+    /* Debug - UART console message */
+
+reg_lock:
+    /* Lock SCU and SDRAM registers */
+    ldr r0, =SCU_KEY_CONTROL_REG
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    ldr r0, =SDRAM_PROTECTION_KEY_REG
+    ldr r1, =0x00000000
+    str r1, [r0]
+
+    /* Return to caller */
+    /* restore lr */
+    mov lr, r4
+
+    /* back to arch calling code */
+    mov pc, lr
diff --git a/board/aspeed/ast2050/rc4.c b/board/aspeed/ast2050/rc4.c
new file mode 100644
index 0000000..2458381
--- /dev/null
+++ b/board/aspeed/ast2050/rc4.c
@@ -0,0 +1,70 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+struct rc4_state
+{
+    int x, y, m[256];
+};
+
+void rc4_setup( struct rc4_state *s, unsigned char *key,  int length )
+{
+    int i, j, k, *m, a;
+
+    s->x = 0;
+    s->y = 0;
+    m = s->m;
+
+    for( i = 0; i < 256; i++ )
+    {
+        m[i] = i;
+    }
+
+    j = k = 0;
+
+    for( i = 0; i < 256; i++ )
+    {
+        a = m[i];
+        j = (unsigned char) ( j + a + key[k] );
+        m[i] = m[j]; m[j] = a;
+        if( ++k >= length ) k = 0;
+    }
+}
+
+void rc4_crypt( struct rc4_state *s, unsigned char *data, int length )
+{ 
+    int i, x, y, *m, a, b;
+
+    x = s->x;
+    y = s->y;
+    m = s->m;
+
+    for( i = 0; i < length; i++ )
+    {
+        x = (unsigned char) ( x + 1 ); a = m[x];
+        y = (unsigned char) ( y + a );
+        m[x] = b = m[y];
+        m[y] = a;
+        data[i] ^= m[(unsigned char) ( a + b )];
+    }
+
+    s->x = x;
+    s->y = y;
+}
+
+void rc4_crypt_sw(unsigned char *data, int ulMsgLength, unsigned char *rc4_key, unsigned long ulKeyLength )
+{
+    struct rc4_state s;
+    
+    rc4_setup( &s, rc4_key, ulKeyLength );
+                                    
+    rc4_crypt( &s, data, ulMsgLength );    
+}
diff --git a/board/aspeed/ast2050/regtest.c b/board/aspeed/ast2050/regtest.c
new file mode 100644
index 0000000..1475b3b
--- /dev/null
+++ b/board/aspeed/ast2050/regtest.c
@@ -0,0 +1,93 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Diagnostics support
+ */
+#include <common.h>
+#include <command.h>
+#include <post.h>
+#include "slt.h"
+
+#if ((CFG_CMD_SLT & CFG_CMD_REGTEST) && defined(CONFIG_SLT))
+#include "regtest.h"
+
+int do_regtest (void)
+{
+	_SOCRegTestInfo	*pjSOCRegInfo;
+	_SOCRegTestTbl *pjRegTable;
+	unsigned long ulRegBase;
+        unsigned long ulIndex, ulBack, ulAND, ulMask, ulData, ulTemp;
+        unsigned long Flags = 0;
+	
+	/* unlock reg */
+        *(unsigned long *) (0x1e600000) = 0xaeed1a03;	/* AHBC */
+        *(unsigned long *) (0x1e6e0000) = 0xfc600309;	/* MMC */
+        *(unsigned long *) (0x1e6e2000) = 0x1688a8a8;	/* SCU */
+
+        /* SCU */
+
+        /* do test */	
+        pjSOCRegInfo = SOCRegTestInfo;
+        while (strcmp(pjSOCRegInfo->jName, "END"))
+        {
+            /* Reg. Test Start */
+            ulRegBase = pjSOCRegInfo->ulRegOffset;
+            pjRegTable = pjSOCRegInfo->pjTblIndex;
+            
+            while (pjRegTable->ulIndex != 0xFFFFFFFF)
+            {
+                ulIndex = ulRegBase + pjRegTable->ulIndex;	
+
+                ulBack = *(unsigned long *) (ulIndex);
+
+                ulMask  = pjRegTable->ulMask;
+                ulAND  = ~pjRegTable->ulMask;
+       	        	    	
+                ulData  = 0xFFFFFFFF & pjRegTable->ulMask;
+                *(unsigned long *) (ulIndex) = ulData;                
+                ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
+                if (ulData != ulTemp)
+                {
+                    Flags |= pjSOCRegInfo->ulFlags;
+                    printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
+                }
+                
+                ulData  = 0x00000000 & pjRegTable->ulMask;
+                *(unsigned long *) (ulIndex) = ulData;                
+                ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
+                if (ulData != ulTemp)
+                {
+                    Flags |= pjSOCRegInfo->ulFlags;
+                    printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
+                }
+                             
+                *(unsigned long *) (ulIndex) = ulBack;
+       
+                pjRegTable++;
+          	
+           } /* Individual Reg. Test */
+
+           if (Flags & pjSOCRegInfo->ulFlags)
+               printf("[INFO] RegTest: %s Failed \n", pjSOCRegInfo->jName);
+           
+           pjSOCRegInfo++;
+           
+        } /* Reg. Test */
+
+	return Flags;
+	
+}
+
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/regtest.h b/board/aspeed/ast2050/regtest.h
new file mode 100644
index 0000000..5d15ab5
--- /dev/null
+++ b/board/aspeed/ast2050/regtest.h
@@ -0,0 +1,257 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+typedef struct {
+    unsigned long ulIndex;
+    unsigned long ulMask;
+} _SOCRegTestTbl;
+
+typedef struct {
+    unsigned char jName[10];
+    unsigned long ulRegOffset;
+    _SOCRegTestTbl *pjTblIndex;
+    unsigned long ulFlags;
+} _SOCRegTestInfo;
+
+_SOCRegTestTbl SMCRegTestTbl[] = {
+    {0x00000000, 0x00001FF3},
+    {0x00000004, 0xFFFFFFFF},
+    {0x00000008, 0x0FFF17FF},
+    {0x0000000C, 0xFFFFFFFF},
+    {0x00000010, 0xFF5FFFF3},
+    {0x00000018, 0x0FFFFFFF},
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl AHBCRegTestTbl[] = {
+    {0x00000080, 0x0000FFFE},        	
+    {0x00000088, 0x01000000},
+    {0x0000008c, 0x00000031},	
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl MICRegTestTbl[] = {
+/*	
+    {0x00000000, 0x0FFFFFF8},
+    {0x00000004, 0x0FFFFFF8},
+    {0x00000008, 0x0000FFFF},
+    {0x0000000C, 0x0FFFF000},
+    {0x00000010, 0xFFFFFFFF},
+*/
+    {0xFFFFFFFF, 0xFFFFFFFF},
+};
+
+_SOCRegTestTbl MAC1RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl MAC2RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl USB2RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl VICRegTestTbl[] = {
+    {0x0000000C, 0xFFFFFFFF},
+    {0x00000024, 0xFFFFFFFF},
+    {0x00000028, 0xFFFFFFFF},
+    {0x0000002C, 0xFFFFFFFF},
+    {0xFFFFFFFF, 0xFFFFFFFF},
+};
+
+_SOCRegTestTbl MMCRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl USB11RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl SCURegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl HASERegTestTbl[] = {
+    {0x00000000, 0x0FFFFFF8},
+    {0x00000004, 0x0FFFFFF8},
+    {0x00000008, 0x0FFFFFF8},
+    {0x0000000C, 0x0FFFFFF8},
+    //{0x00000010, 0x00001FFF},
+    {0x00000020, 0x0FFFFFF8},
+    {0x00000024, 0x0FFFFFF8},
+    {0x00000028, 0x0FFFFFc0},
+    {0x0000002C, 0x0FFFFFFF},
+    //{0x00000030, 0x000003FF},
+    {0xFFFFFFFF, 0xFFFFFFFF},
+};
+
+_SOCRegTestTbl I2SRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl CRTRegTestTbl[] = {
+/*	
+    {0x00000000, 0x001F3703},
+    {0x00000004, 0x0000FFC1},
+*/    
+    {0x00000010, 0x0FFF0FFF},
+    {0x00000014, 0x0FFF0FFF},
+    {0x00000018, 0x07FF07FF},
+    {0x0000001C, 0x07FF07FF},
+    {0x00000020, 0x0FFFFFF8},
+    {0x00000024, 0x07FF3FF8},
+/*    
+    {0x00000028, 0x003F003F},
+    {0x00000030, 0x003F003F},
+    {0x00000034, 0x0FFF0FFF},
+    {0x00000038, 0x0FFFFFF8},
+*/    
+    {0x00000040, 0x0FFF0FFF},
+    {0x00000044, 0x07FF07FF},
+    {0x00000048, 0x0FFFFFF8},
+    {0x0000004C, 0x00FF07F8},
+    {0x00000050, 0x000F0F0F},
+/*    
+    {0x00000060, 0x001F3703},
+    {0x00000064, 0x0000FFC1},
+*/    
+    {0x00000070, 0x0FFF0FFF},
+    {0x00000074, 0x0FFF0FFF},
+    {0x00000078, 0x07FF07FF},
+    {0x0000007C, 0x07FF07FF},
+    {0x00000080, 0x0FFFFFF8},
+    {0x00000084, 0x07FF3FF8},
+/*    
+    {0x00000088, 0x003F003F},
+    {0x00000090, 0x003F003F},
+    {0x00000094, 0x0FFF0FFF},
+    {0x00000098, 0x0FFFFFF8},
+*/    
+    {0x000000A0, 0x0FFF0FFF},
+    {0x000000A4, 0x07FF07FF},
+    {0x000000A8, 0x0FFFFFF8},
+    {0x000000AC, 0x00FF07F8},
+    {0x000000B0, 0x000F0F0F},
+    {0xFFFFFFFF, 0xFFFFFFFF},
+};
+
+_SOCRegTestTbl VIDEORegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl A2PRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl MDMARegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl M2DRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl GPIORegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl RTCRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl TIMERRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl UART1RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl UART2RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl WDTRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl PWMRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl VUART1RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl VUART2RegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl LPCRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl I2CRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl PECIRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl PCIARegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+_SOCRegTestTbl PCIRegTestTbl[] = {
+    {0xFFFFFFFF, 0xFFFFFFFF},        	
+};
+
+
+/* Test List */
+_SOCRegTestInfo SOCRegTestInfo[] = {
+    /* Test Name, Reg. Offset,      Test Table, Error Code  */
+    {   "SMCREG", 0x16000000,    SMCRegTestTbl, 0x00000001},
+    {  "AHBCREG", 0x1e600000,   AHBCRegTestTbl, 0x00000002},
+    {   "MICREG", 0x1e640000,    MICRegTestTbl, 0x00000004},
+    {  "MAC1REG", 0x1e660000,   MAC1RegTestTbl, 0x00000008},
+    {  "MAC2REG", 0x1e680000,   MAC2RegTestTbl, 0x00000010},
+    {  "USB2REG", 0x1e6a0000,   USB2RegTestTbl, 0x00000020},
+    {   "VICREG", 0x1e6c0000,    VICRegTestTbl, 0x00000040},
+    {   "MMCREG", 0x1e6e0000,    MMCRegTestTbl, 0x00000080},
+    { "USB11REG", 0x1e6e1000,  USB11RegTestTbl, 0x00000100},
+    {   "SCUREG", 0x1e6e2000,    SCURegTestTbl, 0x00000200},
+    {  "HASEREG", 0x1e6e3000,   HASERegTestTbl, 0x00000400},
+    {   "I2SREG", 0x1e6e5000,    I2SRegTestTbl, 0x00000800},
+    {   "CRTREG", 0x1e6e6000,    CRTRegTestTbl, 0x00001000},
+    { "VIDEOREG", 0x1e700000,  VIDEORegTestTbl, 0x00002000},
+    {   "A2PREG", 0x1e720000,    A2PRegTestTbl, 0x00004000},
+    {  "MDMAREG", 0x1e740000,   MDMARegTestTbl, 0x00008000},
+    {    "2DREG", 0x1e760000,    M2DRegTestTbl, 0x00010000},
+    {  "GPIOREG", 0x1e780000,   GPIORegTestTbl, 0x00020000},
+    {   "RTCREG", 0x1e781000,    RTCRegTestTbl, 0x00040000},
+    { "TIMERREG", 0x1e782000,  TIMERRegTestTbl, 0x00080000},
+    { "UART1REG", 0x1e783000,  UART1RegTestTbl, 0x00100000},
+    { "UART2REG", 0x1e784000,  UART2RegTestTbl, 0x00200000},
+    {   "WDTREG", 0x1e785000,    WDTRegTestTbl, 0x00400000},
+    {   "PWMREG", 0x1e786000,    PWMRegTestTbl, 0x00800000},
+    {"VUART1REG", 0x1e787000, VUART1RegTestTbl, 0x01000000},
+    {"VUART2REG", 0x1e788000, VUART2RegTestTbl, 0x02000000},
+    {   "LPCREG", 0x1e789000,    LPCRegTestTbl, 0x04000000},
+    {   "I2CREG", 0x1e78A000,    I2CRegTestTbl, 0x08000000},
+    {  "PECIREG", 0x1e78B000,   PECIRegTestTbl, 0x10000000},
+    {  "PCIAREG", 0x1e78C000,   PCIARegTestTbl, 0x20000000},
+    {   "PCIREG", 0x60000000,    PCIRegTestTbl, 0x40000000},        
+    {      "END", 0xffffffff,             NULL, 0xffffffff}
+};
diff --git a/board/aspeed/ast2050/slt.c b/board/aspeed/ast2050/slt.c
new file mode 100644
index 0000000..ac45a0a
--- /dev/null
+++ b/board/aspeed/ast2050/slt.c
@@ -0,0 +1,107 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Diagnostics support
+ */
+#include <common.h>
+#include <command.h>
+#include <post.h>
+#include "slt.h"
+
+#if defined (CONFIG_SLT)
+
+int do_slt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+    int flags = 0;
+    int loop  = 1;
+	
+    if (argc > 1) {
+        loop = simple_strtoul(argv[1], NULL, 10);
+    }
+	
+    do {
+
+do_slt_start:
+	/* Reg. Test */
+#if (CFG_CMD_SLT & CFG_CMD_REGTEST)
+	if (do_regtest())
+	{
+	    flags |= FLAG_REGTEST_FAIL;	
+            printf("[INFO] RegTest Failed \n");
+	}    
+	else
+            printf("[INFO] RegTest Passed \n");
+#endif
+#if (CFG_CMD_SLT & CFG_CMD_MACTEST)
+	if (do_mactest())
+	{
+	    flags |= FLAG_MACTEST_FAIL;	
+            printf("[INFO] MACTest Failed \n");
+	}    
+	else
+            printf("[INFO] MACTest Passed \n");
+#endif
+#if (CFG_CMD_SLT & CFG_CMD_VIDEOTEST)
+	if (do_videotest())
+	{
+	    flags |= FLAG_VIDEOTEST_FAIL;	
+            printf("[INFO] VideoTest Failed \n");
+	}    
+	else
+            printf("[INFO] VideoTest Passed \n");
+#endif
+#if (CFG_CMD_SLT & CFG_CMD_HACTEST)
+	if (do_hactest())
+	{
+	    flags |= FLAG_HACTEST_FAIL;	
+            printf("[INFO] HACTest Failed \n");
+	}    
+	else
+            printf("[INFO] HACTest Passed \n");
+#endif
+#if (CFG_CMD_SLT & CFG_CMD_MICTEST)
+	if (do_mictest())
+	{
+	    flags |= FLAG_MICTEST_FAIL;	
+            printf("[INFO] MICTest Failed \n");
+	}    
+	else
+            printf("[INFO] MICTest Passed \n");
+#endif
+	
+	/* Summary */
+	if (flags)
+            printf ("[INFO] SLT Test Failed!! \n");
+        else
+            printf ("[INFO] SLT Test Passed!! \n");    
+       
+        if (loop == 0)			/* infinite */
+            goto do_slt_start;
+        else
+            loop--;    
+            
+    } while (loop);
+
+    return 0;
+}
+/***************************************************/
+
+U_BOOT_CMD(
+	slt,	CONFIG_SYS_MAXARGS,	0,	do_slt,
+	"slt - slt test program \n",
+	NULL
+);
+
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/slt.h b/board/aspeed/ast2050/slt.h
new file mode 100644
index 0000000..800c75f
--- /dev/null
+++ b/board/aspeed/ast2050/slt.h
@@ -0,0 +1,31 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define CFG_CMD_REGTEST		0x00000001
+#define CFG_CMD_MACTEST		0x00000002
+#define CFG_CMD_VIDEOTEST	0x00000004
+#define CFG_CMD_HACTEST		0x00000008
+#define CFG_CMD_MICTEST		0x00000010
+#define CFG_CMD_OSDTEST		0x00000020
+#define CFG_CMD_2DTEST  	0x00000040
+#define CFG_CMD_HWCTEST  	0x00000080
+
+#define FLAG_REGTEST_FAIL  	0x00000001
+#define FLAG_MACTEST_FAIL  	0x00000002
+#define FLAG_VIDEOTEST_FAIL  	0x00000004
+#define FLAG_HACTEST_FAIL  	0x00000008
+#define FLAG_MICTEST_FAIL  	0x00000010
+#define FLAG_OSDTEST_FAIL  	0x00000020
+#define FLAG_2DTEST_FAIL  	0x00000040
+#define FLAG_HWCTEST_FAIL  	0x00000080
+
+
diff --git a/board/aspeed/ast2050/type.h b/board/aspeed/ast2050/type.h
new file mode 100644
index 0000000..dc761c0
--- /dev/null
+++ b/board/aspeed/ast2050/type.h
@@ -0,0 +1,118 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _TYPE_H_
+#define _TYPE_H_
+
+	typedef unsigned char               BOOL;
+	typedef unsigned char               UINT8;
+	typedef unsigned short              UINT16;
+	typedef unsigned int                UINT32;
+
+	#define  FLONG                    unsigned long
+	#define  BYTE                     unsigned char
+	#define  INT                      int
+	#define  VOID                     void
+	#define  BOOLEAN                  unsigned short
+	#define  ULONG                    unsigned long
+	#define  USHORT                   unsigned short
+	#define  UCHAR                    unsigned char
+	#define  CHAR                     char
+	#define  LONG                     long
+	#define  PUCHAR                   UCHAR *
+	#define  PULONG                   ULONG *
+
+	#define  FAIL                     1
+
+	#define  intfunc      int386
+
+	#define  outdwport         outpd
+	#define  indwport          inpd
+	#define  outport           outp
+	#define  inport            inp
+
+	//#define     NULL    ((void *)0)
+	#define     FALSE   0
+	#define     TRUE    1
+
+	#define ReadMemoryBYTE(baseaddress,offset)        *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset))
+	#define ReadMemoryLong(baseaddress,offset)        *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
+	#define ReadMemoryShort(baseaddress,offset)       *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))
+	#define WriteMemoryBYTE(baseaddress,offset,data)  *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
+	#define WriteMemoryLong(baseaddress,offset,data)  *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
+	#define WriteMemoryShort(baseaddress,offset,data) *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))=(USHORT)(data)
+	#define WriteMemoryLongWithANDData(baseaddress, offset, anddata, data)  *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(anddata) | (ULONG)(data)
+
+	#define WriteMemoryLongWithMASK(baseaddress, offset, data, mask) \
+	*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(volatile ULONG *)(((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(~(mask))) | ((ULONG)(data) & (ULONG)(mask))
+
+	#define ReadMemoryLongHost(baseaddress,offset)        *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
+	#define WriteMemoryLongHost(baseaddress,offset,data)  *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
+	#define WriteMemoryBYTEHost(baseaddress,offset,data)  *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)    
+#define WriteMemoryLongWithMASKHost(baseaddress, offset, data, mask)  *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
+    
+	#define ReadMemoryLongClient(baseaddress,offset)        *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
+	#define WriteMemoryLongClient(baseaddress,offset,data)  *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
+	#define WriteMemoryBYTEClient(baseaddress,offset,data)  *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)    
+#define WriteMemoryLongWithMASKClient(baseaddress, offset, data, mask)  *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
+
+#ifdef BUF_GLOBALS
+#define BUF_EXT
+#else
+#define BUF_EXT extern
+#endif
+
+BUF_EXT ULONG    g_CAPTURE_VIDEO1_BUF1_ADDR; /* VIDEO1_BUF_1_ADDR*/ 
+BUF_EXT ULONG    g_CAPTURE_VIDEO1_BUF2_ADDR; /* VIDEO1_BUF_2_ADDR*/
+BUF_EXT ULONG    g_VIDEO1_COMPRESS_BUF_ADDR; /* Encode destination address */
+BUF_EXT ULONG    g_VIDEO1_CRC_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO1_FLAG_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO1_RC4_BUF_ADDR;
+
+
+BUF_EXT ULONG    g_CAPTURE_VIDEO2_BUF1_ADDR; 
+BUF_EXT ULONG    g_CAPTURE_VIDEO2_BUF2_ADDR; 
+BUF_EXT ULONG    g_VIDEO2_COMPRESS_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO2_CRC_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO2_FLAG_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO2_RC4_BUF_ADDR;
+
+BUF_EXT ULONG    g_VIDEO1_DECODE_BUF_1_ADDR;
+BUF_EXT ULONG    g_VIDEO1_DECODE_BUF_2_ADDR;
+BUF_EXT ULONG    g_VIDEO1_DECOMPRESS_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO1_DECODE_RC4_BUF_ADDR;
+
+BUF_EXT ULONG    g_VIDEO2_DECODE_BUF_1_ADDR;
+BUF_EXT ULONG    g_VIDEO2_DECODE_BUF_2_ADDR;
+BUF_EXT ULONG    g_VIDEO2_DECOMPRESS_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEO2_DECODE_RC4_BUF_ADDR;
+
+BUF_EXT ULONG    g_CAPTURE_VIDEOM_BUF1_ADDR; 
+BUF_EXT ULONG    g_CAPTURE_VIDEOM_BUF2_ADDR; 
+BUF_EXT ULONG    g_VIDEOM_COMPRESS_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEOM_FLAG_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEOM_RC4_BUF_ADDR;
+
+BUF_EXT ULONG    g_VIDEOM_DECODE_BUF_1_ADDR;
+BUF_EXT ULONG    g_VIDEOM_DECODE_BUF_2_ADDR;
+BUF_EXT ULONG    g_VIDEOM_DECOMPRESS_BUF_ADDR;
+BUF_EXT ULONG    g_VIDEOM_DECODE_RC4_BUF_ADDR;
+
+#ifdef WIN_GLOBALS
+#define WIN_EXT
+#else
+#define WIN_EXT extern
+#endif
+
+WIN_EXT USHORT	g_DefWidth, g_DefHeight;
+   
+#endif
diff --git a/board/aspeed/ast2050/vdef.h b/board/aspeed/ast2050/vdef.h
new file mode 100644
index 0000000..91d24a3
--- /dev/null
+++ b/board/aspeed/ast2050/vdef.h
@@ -0,0 +1,508 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _VDEF_H_
+#define _VDEF_H_
+
+#define		VIDEO1		0
+#define		VIDEO1_ON	0x01
+#define		VIDEO2		1
+#define		VIDEO2_ON	0x02
+
+#define		VIDEOM_ON	0x04
+#define		VIDEOM		2
+
+#define		CRT_1		0
+#define		CRT_1_ON	0x01
+#define		CRT_2		1
+#define		CRT_2_ON	0x02
+
+#define		SINGLE_CODEC_SINGLE_CAPTURE	0
+#define		AUTO_CODEC_SINGLE_CAPTURE	2
+#define		AUTO_CODEC_AUTO_CAPTURE		3
+
+#define		MAC1_BASE		0x1E660000
+#define		APB_BRIDGE_1_BASE	0x1E6E0000
+#define		VIDEO_REG_BASE		0x1E700000
+#define		APB_BRIDGE_2_BASE	0x1E780000
+
+#define		DRAM_INIT_BASE		0x1E6E0000	/* SDRAM Memory Controller - MCR base addr */
+
+#define		SDRAM_PROTECT_REG	0x00
+#define		SDRAM_WRITE_DISABLE	0
+#define		SDRAM_WRITE_ENABLE	1
+
+/* System Control Unit (SCU) */
+#define		SCU_BASE		0x1E6E0000	/* base + offset = 0x1e6e2000 */
+#define		SCU_OFFSET		0x2000
+
+/* Vector Interrupt Controller (VIC) */
+#define		VIC_BASE		0x1E6C0000
+#define		VIDEO_INT_BIT		7		//did not find in ast2050 ds
+
+#define		IRQ_STATUS_REG		0x00
+#define		RAW_INT_STATUS_REG	0x08
+#define		INT_SEL_REG		0x0C
+#define		FIQ_INT			1
+#define		IRQ_INT			0
+#define		INT_EN_REG		0x10
+#define		INT_EN_CLEAR_REG	0x14
+#define		INT_SOFT_REG		0x18
+#define		INT_SOFT_CLEAR_REG	0x1C
+#define		INT_SENSE_REG		0x24
+#define		LEVEL_SENSE		1
+#define		EDGE_SENSE		0
+#define		INT_EVENT_REG		0x2C
+#define		HIGH_LEVEL_SENSE	1
+#define		LOW_LEVEL_SENSE		0
+
+#define		SCU_HW_TRAPPING_REG	x70 + SCU_OFFSET
+//---not sure about these, couldn't find in ast2050 datasheet
+#define		CLIENT_MODE_EN_BIT	18
+#define		CLIENT_MODE_EN_MASK	0x00040000
+#define		BE_HOST_CHIP		0
+#define		BE_CLIENT_CHIP		1
+
+#define		SCU_ULOCK_KEY		0x1688A8A8
+
+#define		SCU_PROTECT_REG		0x00 + SCU_OFFSET
+#define		SCU_WRITE_DISABLE	0
+#define		SCU_WRITE_ENABLE	1
+
+#define		SCU_CONTROL_REG		0x04 + SCU_OFFSET
+#define		VIDEO_ENGINE_RESET		0x00000040
+#define		VIDEO_ENGINE_RESET_BIT		6
+#define		VIDEO_ENGINE_RESET_MASK		0x00000040
+#define		VIDEO_RESET_EN	      		1
+#define		VIDEO_RESET_OFF	     		0
+
+#define		SCU_CLOCK_SELECTION_REG	     0x08 + SCU_OFFSET
+#define		PORTA_CLOCK_DELAY_MASK		7 << 8	//Video port A output clock selection
+#define		PORTA_CLOCK_INV_DELAY_1NS	5 << 8	//Clock inversed and delay ~ 2ns
+#define		PORTA_CLOCK_INV_DELAY_2NS	6 << 8	//Clock inversed and delay ~ 3ns
+/* Port B does not exist in AST2050*/
+// #define		PORTB_CLOCK_DELAY_MASK		7 << 12	//Video port B output clock delay
+// #define		PORTB_CLOCK_INV_DELAY_1NS	5 << 12	//Clock inversed and delay ~ 3ns
+// #define		PORTB_CLOCK_INV_DELAY_2NS	6 << 12	//Clock inversed and delay ~ 3ns
+// #define		PORTB_CLOCK_SEL			1 << 15 //Video port B clock selection
+// #define		PORTB_FROM_D1CLK		0 << 15
+// #define		PORTB_FROM_D2CLK		1 << 15
+#define		ECLK_CLK_SEL_MASK		(3 << 2)
+#define		ECLK_FROM_HPLL			(1 << 2)
+
+/*D2CLK does not exist in AST2050*/
+// #define		D2CLK_CLOCK_SELECTION		0x00020000 
+// #define		D2CLK_CLOCK_SELECTION_BIT	17
+// #define		D2CLK_CLOCK_SELECTION_MASK	0x00060000
+
+#define		NORMAL_CRT1			0
+#define		V1CLK_VIDEO1			2
+#define		V1CLK_VIDEO2			3
+
+#define		SCU_CLOCK_STOP_REG	0x0C + SCU_OFFSET
+#define		EN_ECLK			0 << 0	//Enable ECLK (For Video Engine)
+#define		STOP_ECLK_BIT		0
+#define		STOP_ECLK_MASK		1 << 0
+#define		EN_V1CLK		0 << 3  //Enable V1CLK (For Video Capture #1)
+#define		STOP_V1CLK_BIT		3
+#define		STOP_V1CLK_MASK		1 << 3
+#define		EN_D1CLK		0 << 5 //Enable D1CLK (For VGA)
+#define		STOP_D1CLK_BIT		5
+#define		STOP_D1CLK_MASK		1 << 5
+// #define		EN_D2CLK		0 << 11 //Stop D2CLK (For CRT2)
+// #define		STOP_D2CLK		(1 << 11)
+// #define		STOP_D2CLK_BIT		11
+// #define		STOP_D2CLK_MASK		1 << 11
+// #define		EN_V2CLK		0 << 12 //Stop V2CLK (For Video Capture #2)
+// #define		STOP_V2CLK_BIT		12
+// #define		STOP_V2CLK_MASK		1 << 12
+#define		STOP_HACE_BIT		13
+#define		EN_HACE			(0 << 13)
+#define		STOP_HACE_MASK		(1 << 13)
+// #define		EN_I2SCLK		0 << 18
+// #define		STOP_I2SCLK_MASK	1 << 18
+
+#define		SCU_PIN_CTRL1_REG	0x74 + SCU_OFFSET
+#define		I2C_5_PIN_EN		1 << 12	//Enable I2C #5 PIN
+#define		I2C_5_PIN_OFF		0 << 12	//Disable I2C #5 PIN
+#define		I2C_5_PIN_MASK		1 << 12
+#define		VGA_PIN_OFF		0 << 15 //Enable VGA pins
+#define		VGA_PIN_MASK		1 << 15
+#define		VIDEO_PORTA_EN		1 << 16 //Enable Video port A control pins
+#define		VIDEO_PORTA_MASK	1 << 16
+// #define		VIDEO_PORTB_EN		1 << 17 //pin 17 Reserved, must keep @ value "0"
+// #define		VIDEO_PORTB_MASK	1 << 17
+#define		VIDEO_VP1_EN		1 << 22 //Enable VP[11:0]
+#define		VIDEO_VP1_MASK		1 << 22 
+#define		VIDEO_VP2_EN		1 << 23 //Enable VP[23:12]
+#define		VIDEO_VP2_MASK		1 << 23
+// #define		I2S_PIN_EN		1 << 29 //pin 29 Reserved, must keep @ value "0"
+// #define		I2S_PIN_MASK		1 << 29
+
+#define		SCU_PIN_CTRL2_REG		0x78 + SCU_OFFSET
+#define		VIDEO_PORTA_SINGLE_EDGE_MASK	1 << 0
+#define		VIDEO_PORTA_SINGLE_EDGE		1 << 0	//Enable Video port A single mode
+#define		VIDEO_PORTA_DUAL_EDGE		0 << 0
+// #define		VIDEO_PORTB_SINGLE_EDGE_MASK	1 << 1
+// #define		VIDEO_PORTB_DUAL_EDGE		0 << 1
+// #define		VIDEO_PORTB_SINGLE_EDGE		1 << 1	//Enable Video port B single mode
+
+#define		SCU_M_PLL_PARAM_REG	0x20 + SCU_OFFSET
+
+#define		DRAM_BASE		0x40000000
+
+#define		INPUT_BITCOUNT_YUV444	4
+#define		INPUT_BITCOUNT_YUV420	2
+
+/* HW comment value */
+//PASSWORD
+#define		VIDEO_UNLOCK_KEY	0x1A038AA8
+#define		SCU_UNLOCK_KEY		0x1688A8A8
+#define		SDRAM_UNLOCK_KEY	0xFC600309
+
+
+//#define	SAMPLE_RATE		 12000000.0
+#ifdef OSC_NEW
+#define	SAMPLE_RATE	24576000.0
+#else
+#define	SAMPLE_RATE	24000000.0
+#endif
+
+#define		MODEDETECTION_VERTICAL_STABLE_MAXIMUM		0x4
+#define		MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM		0x4
+#define		MODEDETECTION_VERTICAL_STABLE_THRESHOLD		0x4
+#define		MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD	0x8
+
+#define		MODEDETECTION_EDGE_PIXEL_THRES_DIGITAL		2
+#define		MODEDETECTION_EDGE_PIXEL_THRES_ANALOGE		0x0A
+
+#define		MODEDETECTION_OK		0
+#define		MODEDETECTION_ERROR		1
+#define		JUDGE_MODE_ERROR		2
+
+//I2C Loop Count
+#define    LOOP_COUNT		1000
+#define    CAN_NOT_FIND_DEVICE	1
+#define    SET_I2C_DONE		0
+#define	   I2C_BASE		0xA000
+#define    AC_TIMING		0x77743355
+
+//I2C channel and Devices
+#define		I2C_VIDEO1_EEPROM	0x2
+#define		I2C_VIDEO2_EEPROM	0x5
+#define		I2C_VIDEO2_9883		0x4
+/*
+ULONG    CAPTURE1_ADDRESS =		     0x1000000;
+ULONG    CAPTURE2_ADDRESS =		     0x3000000;
+ULONG    PASS1_ENCODE_SOURCE_ADDRESS =	  0x1000000;
+ULONG    PASS1_ENCODE_DESTINATION_ADDRESS =     0x2000000;
+ULONG    Buffer1_DECODE_SOURCE_ADDRESS =	0x1000000;
+ULONG    Buffer2_DECODE_SOURCE_ADDRESS =	0x1400000;
+ULONG    PASS1_DECODE_DESTINATION_ADDRESS =     0x600000;
+ULONG    CAPTURE_2ND_ADDRESS =		  0x1800000;
+ULONG    PASS1_2ND_ENCODE_SOURCE_ADDRESS =      0x1800000;
+ULONG    PASS1_2ND_ENCODE_DESTINATION_ADDRESS = 0x2800000;
+ULONG    PASS1_2ND_DECODE_SOURCE_ADDRESS =      0x1000000;
+ULONG    PASS1_2ND_DECODE_DESTINATION_ADDRESS = 0x600000;
+ULONG    PASS2_ENCODE_SOURCE_ADDRESS =	  0x000000;
+ULONG    PASS2_ENCODE_DESTINATION_ADDRESS =     0xC00000;
+ULONG    PASS2_DECODE_SOURCE_ADDRESS =	  0xC00000;
+ULONG    PASS2_DECODE_DESTINATION_ADDRESS =     0x600000;
+ULNG    PASS2_DECODE_REFERENCE_ADDRESS =       0x600000;
+*/
+
+typedef struct _CTL_REG_G {
+    ULONG   CompressMode:1;
+    ULONG   SkipEmptyFrame:1;
+    ULONG   MemBurstLen:2;
+    ULONG   LineBufEn:2;
+    ULONG   Unused:26;
+} CTL_REG_G;
+
+
+typedef union _U_CTL_G {
+    ULONG       Value;
+    CTL_REG_G   CtlReg;
+} U_CTL_G;
+
+typedef struct _MODE_DETECTION_PARAM_REG {
+    ULONG   Unused1:8;
+    ULONG   EdgePixelThres:8;
+    ULONG   VerStableMax:4;
+    ULONG   HorStableMax:4;
+    ULONG   VerDiffMax:4;
+    ULONG   HorDiffMax:4;
+} MODE_DETECTION_PARAM_REG;
+
+typedef struct _CRC_PRI_PARAM_REG {
+    ULONG   Enable:1;
+    ULONG   HighBitOnly:1;
+    ULONG   SkipCountMax:6;
+    ULONG   PolyLow:8;
+    ULONG   PolyHigh:16;
+} CRC_PRI_PARAM_REG;
+
+typedef union _U_CRC_PRI_PARAM {
+    ULONG	       Value;
+    CRC_PRI_PARAM_REG   CRCPriParam;
+} U_CRC_PRI_PARAM;
+
+typedef struct _CRC_SEC_PARAM_REG {
+    ULONG   Unused1:8;
+    ULONG   PolyLow:8;
+    ULONG   PolyHigh:16;
+} CRC_SEC_PARAM_REG;
+
+typedef union _U_CRC_SEC_PARAM {
+    ULONG	       Value;
+    CRC_SEC_PARAM_REG   CRCSecParam;
+} U_CRC_SEC_PARAM;
+
+typedef struct _GENERAL_INFO {
+    BYTE		EnableVideoM;
+    BYTE		CenterMode;
+	BYTE				RC4NoResetFrame;
+	BYTE				RC4TestMode;
+    U_CTL_G	     uCtlReg;
+    U_CRC_PRI_PARAM     uCRCPriParam;
+    U_CRC_SEC_PARAM     uCRCSecParam;
+} GENERAL_INFO, *PGENERAL_INFO;
+
+typedef struct _SEQ_CTL_REG {
+    ULONG   Unused1:1;
+    ULONG   Unused2:1;
+    ULONG   Unused3:1;
+    ULONG   CaptureAutoMode:1;
+    ULONG   Unused4:1;
+    ULONG   CodecAutoMode:1;
+    ULONG   Unused5:1;
+    ULONG   WatchDog:1;
+    ULONG   CRTSel:1;
+    ULONG   AntiTearing:1;
+    ULONG   DataType:2;
+    ULONG   Unused6:20;
+} SEQ_CTL_REG;
+
+typedef union _U_SEQ_CTL {
+    ULONG	       Value;
+    SEQ_CTL_REG   SeqCtlReg;
+} U_SEQ_CTL;
+
+typedef struct _CTL_REG {
+    ULONG   SrcHsync:1;
+    ULONG   SrcVsync:1;
+    ULONG   ExtSrc:1;
+    ULONG   AnalongExtSrc:1;
+    ULONG   IntTimingGen:1;
+    ULONG   IntDataFrom:1;
+    ULONG   WriteFmt:2;
+    ULONG   VGACursor:1;
+    ULONG   LinearMode:1;
+    ULONG   ClockDelay:2;
+    ULONG   CCIR656Src:1;
+    ULONG   PortClock:1;
+    ULONG   ExtPort:1;	
+    ULONG   Unused1:1;
+    ULONG   FrameRate:8;
+    ULONG   Unused2:8;
+} CTL_REG;
+
+typedef union _U_CTL {
+    ULONG       Value;
+    CTL_REG     CtlReg;
+} U_CTL_REG;
+
+typedef struct _TIMING_GEN_SETTING_H {
+    ULONG   HDEEnd:13;
+    ULONG   Unused1:3;
+    ULONG   HDEStart:13;
+    ULONG   Unused2:3;
+} TIMING_GEN_SETTING_H;
+
+typedef struct _TIMING_GEN_SETTING_V {
+    ULONG   VDEEnd:13;
+    ULONG   Unused1:3;
+    ULONG   VDEStart:13;
+    ULONG   Unused2:3;
+} TIMING_GEN_SETTING_V;
+
+typedef struct _BCD_CTL_REG {
+    ULONG   Enable:1;
+    ULONG   Unused1:15;
+    ULONG   Tolerance:8;
+    ULONG   Unused2:8;
+} BCD_CTL_REG;
+
+typedef union _U_BCD_CTL {
+    ULONG	   Value;
+    BCD_CTL_REG     BCDCtlReg;
+} U_BCD_CTL;
+
+typedef struct _COMPRESS_WINDOW_REG {
+    ULONG   VerLine:13;
+    ULONG   Unused1:3;
+    ULONG   HorPixel:13;
+    ULONG   Unused2:3;
+} COMPRESS_WINDOW_REG;
+
+typedef struct _STREAM_BUF_SIZE {
+    ULONG   PacketSize:3;
+    ULONG   RingBufNum:2;
+    ULONG   Unused1:11;
+    ULONG   SkipHighMBThres:7;
+    ULONG   SkipTestMode:2;
+    ULONG   Unused2:7;
+} STREAM_BUF_SIZE;
+
+typedef union _U_STREAM_BUF {
+    ULONG	       Value;
+    STREAM_BUF_SIZE     StreamBufSize;
+} U_STREAM_BUF;
+
+
+typedef struct _COMPRESS_CTL_REG {
+    ULONG   JPEGOnly:1; /* True: Jpeg Only mode(Disable VQ), False:Jpeg and VQ mix mode */
+    ULONG   En4VQ:1; /* True: 1, 2, 4 color mode, False: 1,2 color mode */
+    ULONG   CodecMode:1; /* High and best Quantization encoding/decoding setting*/
+    ULONG   DualQuality:1;
+    ULONG   EnBest:1;
+    ULONG   EnRC4:1;
+    ULONG   NorChromaDCTTable:5;
+    ULONG   NorLumaDCTTable:5;
+    ULONG   EnHigh:1;
+    ULONG   TestCtl:2;
+    ULONG   UVFmt:1;
+    ULONG   HufTable:2;
+    ULONG   AlterValue1:5;
+    ULONG   AlterValue2:5;
+} COMPRESS_CTL_REG;
+
+typedef union _U_COMPRESS_CTL {
+    ULONG	       Value;
+    COMPRESS_CTL_REG    CompressCtlReg;
+} U_COMPRESS_CTL;
+
+typedef struct _QUANTI_TABLE_LOW_REG {
+    ULONG   ChromaTable:5;
+    ULONG   LumaTable:5;
+    ULONG   Unused1:22;
+} QUANTI_TABLE_LOW_REG;
+
+typedef union _U_CQUANTI_TABLE_LOW {
+    ULONG		   Value;
+    QUANTI_TABLE_LOW_REG    QTableLowReg;
+} U_QUANTI_TABLE_LOW;
+
+typedef struct _QUANTI_VALUE_REG {
+    ULONG   High:15;
+	ULONG	Unused1:1;
+    ULONG   Best:15;
+    ULONG   Unused2:1;
+} QUANTI_VALUE_REG;
+
+typedef union _U_QUANTI_VALUE {
+    ULONG	       Value;
+    QUANTI_VALUE_REG    QValueReg;
+} U_QUANTI_VALUE;
+
+typedef struct _BSD_PARAM_REG {
+    ULONG   HighThres:8;
+    ULONG   LowThres:8;
+    ULONG   HighCount:6;
+    ULONG   Unused1:2;
+    ULONG   LowCount:6;
+    ULONG   Unused2:2;
+} BSD_PARAM_REG;
+
+typedef union _U_BSD_PARAM {
+    ULONG	   Value;
+    BSD_PARAM_REG   BSDParamReg;
+} U_BSD_PARAM;
+
+typedef struct _VIDEO_INFO {
+    BYTE      ExtADCAct;    /* read from modection register */
+	BYTE	  EnableRC4;
+    BYTE      DownScalingMethod;
+    USHORT    AnalogDifferentialThreshold; /* BCD tolerance */
+    USHORT    DigitalDifferentialThreshold; /* BCD tolerance */
+    USHORT    DstWidth;
+    USHORT    DstHeight;
+    USHORT    SrcWidth;
+    USHORT    SrcHeight;
+    BYTE      HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
+    BYTE      HighChromaTable;
+    BYTE      HighDeQuantiValue;
+    BYTE      BestDequantiValue;
+    U_SEQ_CTL	       uSeqCtlReg;
+    U_CTL_REG	       uCtlReg;
+    U_BCD_CTL	       uBCDCtlReg;
+    U_STREAM_BUF	    uStreamBufSize;
+    U_COMPRESS_CTL	  uCompressCtlReg;
+    U_QUANTI_TABLE_LOW      uQTableLowReg;
+    U_QUANTI_VALUE	  uQValueReg;
+    U_BSD_PARAM	     uBSDParamReg;
+} VIDEO_INFO, *PVIDEO_INFO ;
+
+typedef struct _VIDEOM_SEQ_CTL_REG {
+    ULONG   Unused1:1;  //Bit 0
+    ULONG   Unused2:1;	//Bit 1
+    ULONG   Unused3:1;		//Bit 2
+    ULONG   StreamMode:1;	//Bit 3
+    ULONG   Unused4:1;	//Bit 4
+    ULONG   CodecAutoMode:1;	//Bit 5
+	ULONG	Unused6:1;	//Bit 6
+    ULONG   Unused7:1;	//Bit 7
+    ULONG   SrcSel:1;	//Bit 8
+    ULONG   Unused9:1;	//Bit 9
+    ULONG   DataType:2;  //Bit[11:10]
+    ULONG   Unused12:20;
+} VIDEOM_SEQ_CTL_REG;
+
+typedef union _U_VIDEOM_SEQ_CTL {
+    ULONG					Value;
+    VIDEOM_SEQ_CTL_REG		SeqCtlReg;
+} U_VIDEOM_SEQ_CTL;
+
+typedef struct _VIDEOM_INFO {
+    BYTE      DownScalingMethod;
+    USHORT    AnalogDifferentialThreshold; /* BCD tolerance */
+    USHORT    DigitalDifferentialThreshold; /* BCD tolerance */
+    USHORT    DstWidth;
+    USHORT    DstHeight;
+    USHORT    SrcWidth;
+    USHORT    SrcHeight;
+    BYTE      HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
+    BYTE      HighChromaTable;
+    BYTE      HighDeQuantiValue;
+    BYTE      BestDequantiValue;
+    BYTE      PacketSize;   //the same as video1 & video2
+    BYTE      RingBufNum;
+	BYTE	  EnableRC4;
+    U_VIDEOM_SEQ_CTL	uSeqCtlReg;
+    U_BCD_CTL	       uBCDCtlReg;
+    U_COMPRESS_CTL	  uCompressCtlReg;
+    U_QUANTI_TABLE_LOW      uQTableLowReg;
+    U_QUANTI_VALUE	  uQValueReg;
+    U_BSD_PARAM	     uBSDParamReg;
+} VIDEOM_INFO, *PVIDEOM_INFO ;
+
+typedef struct _VIDEO_MODE_INFO
+{
+    USHORT    X;
+    USHORT    Y;
+    USHORT    ColorDepth;
+    USHORT    RefreshRate;
+    BYTE      ModeIndex;
+} VIDEO_MODE_INFO, *PVIDEO_MODE_INFO;
+
+#endif
+
diff --git a/board/aspeed/ast2050/vesa.h b/board/aspeed/ast2050/vesa.h
new file mode 100644
index 0000000..5f74d45
--- /dev/null
+++ b/board/aspeed/ast2050/vesa.h
@@ -0,0 +1,165 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _VESA_H_
+#define _VESA_H_
+
+typedef enum 
+{
+	VCLK25_175	= 0x00,
+	VCLK28_322	= 0x01,
+	VCLK31_5	= 0x02,
+	VCLK31_574	= 0x03,
+	VCLK32_76	= 0x04,
+	VCLK33_154	= 0x05,
+	VCLK36		= 0x06,
+	VCLK40		= 0x07,
+	VCLK45_978	= 0x08,
+	VCLK49_5	= 0x09,
+	VCLK50		= 0x0A,
+	VCLK52_95	= 0x0B,
+	VCLK56_25	= 0x0C,
+	VCLK65		= 0x0D,
+	VCLK74_48	= 0x0E,
+	VCLK75		= 0x0F,
+	VCLK78_75	= 0x10,
+	VCLK79_373	= 0x11,
+	VCLK81_624	= 0x12,
+	VCLK83_462	= 0x13,
+	VCLK84_715	= 0x14,
+	VCLK94_5	= 0x15,
+	VCLK106_5	= 0x16,
+	VCLK108		= 0x17,
+	VCLK119		= 0x18,
+	VCLK135		= 0x19,
+	VCLK136_358 = 0x1A,
+	VCLK146_25	= 0x1B,
+	VCLK154		= 0x1C,
+	VCLK157_5	= 0x1D,
+	VCLK162		= 0x1E
+} ePIXEL_CLOCK;
+
+typedef struct {
+    USHORT    HorizontalTotal;
+    USHORT    VerticalTotal;
+    USHORT    HorizontalActive;
+    USHORT    VerticalActive;
+    BYTE      RefreshRate;
+    double    HorizontalFrequency;
+    USHORT    HSyncTime;
+    USHORT    HBackPorch;
+    USHORT    VSyncTime;
+    USHORT    VBackPorch;
+    USHORT    HLeftBorder;
+    USHORT    HRightBorder;
+    USHORT    VBottomBorder;
+    USHORT	  VTopBorder;
+	USHORT	  PixelClock;
+	BOOL	  HorPolarity;
+	BOOL	  VerPolarity;
+    BYTE      ADCIndex1;
+    BYTE      ADCIndex2;
+    BYTE      ADCIndex3;
+    BYTE      ADCIndex5;
+    BYTE      ADCIndex6;
+    BYTE      ADCIndex7;
+    BYTE      ADCIndex8;
+    BYTE      ADCIndex9;
+    BYTE      ADCIndexA;
+    BYTE      ADCIndexF;
+    BYTE      ADCIndex15;
+    int       HorizontalShift;
+    int       VerticalShift;
+} VESA_MODE;
+
+#define HOR_POSITIVE 0
+#define HOR_NEGATIVE 1
+#define VER_POSITIVE 0
+#define VER_NEGATIVE 1
+
+#ifdef VESA_GLOBALS
+
+//  Note: Modified for modes which have border issue
+VESA_MODE vModeTable[] = {
+////////////////////////// 60Hz mode
+// 720x480 done
+  {1056, 497,  720,  480,  60, 29.900, 88,  104, 3, 13, 0, 0, 0, 0,	VCLK31_574,  HOR_NEGATIVE, VER_NEGATIVE, 0x41,	0xF0, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	2},
+// 848x480 done                                                                               
+  {1064, 517,  848,  480,  60, 31.160, 88,  91,  3, 26, 0, 0, 0, 0,	VCLK33_154,  HOR_NEGATIVE, VER_NEGATIVE, 0x42,	0x70, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	2},
+  {800,  525,  640,  480,  60, 31.469, 96,  40,  2, 25, 1, 1, 8, 8,	VCLK25_175,  HOR_NEGATIVE, VER_NEGATIVE, 0x31,	0xF0, 0x48, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	2},
+// 720x576                                                                                    
+  {912,  597,  720,  576,  60, 35.920, 72,  88,  3, 17, 0, 0, 0, 0,	VCLK32_76,   HOR_NEGATIVE, VER_NEGATIVE, 0x38,	0xF0, 0x48, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	2},
+// 960x600 GTF done                                                                           
+  {1232, 622,  960,  600,  60, 37.320, 96,  136, 3, 18, 0, 0, 0, 0,	VCLK45_978,  HOR_NEGATIVE, VER_NEGATIVE, 0x4C,	0xF0, 0x60, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1056, 628,  800,  600,  60, 37.879, 128, 88,  4, 23, 0, 0, 0, 0,	VCLK40,	     HOR_POSITIVE, VER_POSITIVE, 0x41,	0xF0, 0x60, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+// 1088x612 GTF done                                                                          
+  {1392, 634,  1088, 612,  60, 38.04,  112, 152, 3, 18, 0, 0, 0, 0,	VCLK52_95,   HOR_NEGATIVE, VER_NEGATIVE, 0x56,	0xF0, 0x60, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1280x720 GTF done                                                                          
+  {1664, 746,  1280, 720,  60, 44.760, 136, 192, 3, 22, 0, 0, 0, 0,	VCLK74_48,   HOR_NEGATIVE, VER_NEGATIVE, 0x67,	0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1360x768 GTF done                                                                          
+  {1776, 795,  1360, 768,  60, 47.700, 144, 208, 3, 23, 0, 0, 0, 0,	VCLK84_715,  HOR_NEGATIVE, VER_NEGATIVE, 0x6E,	0xF0, 0xA8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60, 0x5E, 0xFE,  7, 1},
+// 1280x768 done                                                                              
+  {1664, 798,  1280, 768,  60, 47.700, 128, 184, 7, 20, 0, 0, 0, 0,	VCLK79_373,  HOR_NEGATIVE, VER_NEGATIVE, 0x67,	0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE,  7, 1},
+  {1344, 806,  1024, 768,  60, 48.363, 136, 160, 6, 29, 0, 0, 0, 0,	VCLK65,	     HOR_NEGATIVE, VER_NEGATIVE, 0x53,	0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	7},
+// 1280x800 GTF done                                                                          
+  {1680, 828,  1280, 800,  60, 49.680, 136, 200, 3, 24, 0, 0, 0, 0,	VCLK83_462,  HOR_NEGATIVE, VER_NEGATIVE, 0x68,	0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1152x864 GTF done                                                                          
+  {1520, 895,  1152, 864,  60, 53.700, 120, 184, 3, 27, 0, 0, 0, 0,	VCLK81_624,  HOR_NEGATIVE, VER_NEGATIVE, 0x5E,	0xF0, 0xA8, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1600x900 GTF done                                                                          
+  {2128, 932,  1600, 900,  60, 55.920, 168, 264, 3, 28, 0, 0, 0, 0,	VCLK119,	 HOR_NEGATIVE, VER_NEGATIVE, 0x84,	0xF0, 0xA8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1440X900 CVT done                                                                          
+  {1904, 933,  1440, 900,  60, 55.935, 152, 232, 6,	25,	0, 0, 0, 0,	VCLK106_5,   HOR_NEGATIVE, VER_POSITIVE, 0x76,	0xF0, 0xA8, 0x05, 0x20, 0x96, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+  {1800, 1000, 1280, 960,  60, 60.000, 112, 312, 3, 36, 0, 0, 0, 0,	VCLK108,	 HOR_POSITIVE, VER_POSITIVE, 0x70,	0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
+// 1600x1024 GTF done                                                                            
+  {2144, 1060, 1600, 1024, 60, 63.600, 168, 272, 3, 32, 0, 0, 0, 0,	VCLK136_358, HOR_NEGATIVE, VER_NEGATIVE, 0x85,	0xF0, 0xE8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1688, 1066, 1280, 1024, 60, 63.981, 112, 248, 3, 38, 0, 0, 0, 0,	VCLK108,	 HOR_POSITIVE, VER_POSITIVE, 0x69,	0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+// 1680X1050 CVT done Reduced Blanking                                                          
+  {1840, 1080, 1680, 1050, 60, 64.674, 32,  80,	 6,	21,	0, 0, 0, 0,	VCLK119,	 HOR_POSITIVE, VER_NEGATIVE, 0x72,	0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+// 1920X1200 CVT done Reduced Blanking                           
+  {2080, 1235, 1920, 1200, 60, 74.038, 32,  80,  6, 26, 0, 0, 0, 0, VCLK154,     HOR_POSITIVE, VER_NEGATIVE, 0x81,	0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  //{2160,           1250,           1600,           1200, 60,75.000,           192,        304,         3,          46,          0,            0,             0,              0,			VCLK162,		HOR_POSITIVE,	VER_POSITIVE},
+  {2160, 1248, 1600, 1200, 60, 75.000, 192, 304, 3, 46, 0, 0, 0, 0,	VCLK162,	 HOR_POSITIVE, VER_POSITIVE, 0x86,	0xF0, 0xE8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+                                                              
+//////////////////////  Not 60Hz mode                                                                                                                  
+  {900,  449,  720,  400,  70, 31.469, 108, 45,  2, 25, 1, 1, 8, 8,	0,			 HOR_NEGATIVE, VER_NEGATIVE, 0x38,	0x30, 0x48, 0x05, 0x20, 0x6C, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	1},
+  {832,  520,  640,  480,  72, 37.861, 40,  120, 3, 20, 1, 1, 8, 8,	0,			 HOR_NEGATIVE, VER_NEGATIVE, 0x33,	0xF0, 0x48, 0x05, 0x20, 0x28, 0x60, 0x60, 0x60,	0x5E, 0xFE,  6,	3},
+  {840,  500,  640,  480,  75, 37.500, 64,  120, 3, 16, 0, 0, 0, 0,	0,			 HOR_NEGATIVE, VER_NEGATIVE, 0x34,	0x70, 0x48, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	3},                                         
+  {832,  509,  640,  480,  85, 43.269, 56,  80,  3, 25, 0, 0, 0, 0,	0,			 HOR_NEGATIVE, VER_NEGATIVE, 0x33,	0xF0, 0x48, 0x05, 0x20, 0x38, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	3},
+  {1024, 625,  800,  600,  56, 35.156, 72,  128, 2, 22, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x3F,	0xF0, 0x60, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1040, 666,  800,  600,  72, 48.077, 120, 64,  6, 23, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x40,	0xF0, 0x60, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1056, 625,  800,  600,  75, 46.875, 80,  160, 3, 21, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x41,	0xF0, 0x60, 0x05, 0x20, 0x50, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1048, 631,  800,  600,  85, 53.674, 64,  152, 3, 27, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x41,	0x70, 0x60, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1328, 806,  1024, 768,  70, 56.476, 136, 144, 6, 29, 0, 0, 0, 0,	0,			 HOR_NEGATIVE, VER_NEGATIVE, 0x52,	0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	7},
+  {1312, 800,  1024, 768,  75, 60.023, 96,  176, 3, 28, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x51,	0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	1},
+  {1376, 808,  1024, 768,  85, 68.677, 96,  208, 3, 36, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x55,	0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	1},
+  {1600, 900,  1152, 864,  75, 67.500, 128, 256, 3, 32, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x63,	0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1728, 1011, 1280, 960,  85, 85.938, 160, 224, 3, 47, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x6B,	0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1688, 1066, 1280, 1024, 75, 79.976, 144, 248, 3, 38, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x69,	0x70, 0xE8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {1728, 1072, 1280, 1024, 85, 91.146, 160, 224, 3, 44, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x6B,	0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {2160, 1250, 1600, 1200, 65, 81.250, 192, 304, 3, 46, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x86,	0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {2160, 1250, 1600, 1200, 70, 87.500, 192, 304, 3, 46, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x86,	0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {2160, 1250, 1600, 1200, 75, 93.750, 192, 304, 3, 46, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x86,	0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0},
+  {2160, 1250, 1600, 1200, 85, 106.250,192, 304, 3, 46, 0, 0, 0, 0,	0,			 HOR_POSITIVE, VER_POSITIVE, 0x86,	0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60,	0x5E, 0xFE, -1,	0}
+};
+
+USHORT  ModeNumberCount = sizeof (vModeTable) / sizeof (VESA_MODE);
+USHORT  Mode60HZCount = 21;
+
+#else  /* NOT VESA_GLOBALS */
+extern VESA_MODE vModeTable[];
+extern USHORT  ModeNumberCount;
+extern USHORT  Mode60HZCount;
+#endif
+
+#endif /* _VESA_H_ */
+
+
diff --git a/board/aspeed/ast2050/vfun.c b/board/aspeed/ast2050/vfun.c
new file mode 100644
index 0000000..d652a93
--- /dev/null
+++ b/board/aspeed/ast2050/vfun.c
@@ -0,0 +1,545 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define BUF_GLOBALS
+#include "type.h"
+#include "vdef.h"
+#include "vreg.h"
+#include "crt.h"
+#include "vfun.h"
+
+ULONG UnlockSCURegHost(ULONG   MMIOBase, ULONG Key)
+{
+    WriteMemoryLongHost(SCU_BASE, SCU_PROTECT_REG, Key);
+    return ReadMemoryLongHost(SCU_BASE,SCU_PROTECT_REG);
+}
+
+void ResetVideoHost(void)
+{
+	WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_EN << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
+	WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_OFF << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
+}
+
+void StartModeDetectionTriggerHost(ULONG   MMIOBase, ULONG offset)
+{
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
+}
+
+BOOL ReadVideoInterruptHost(ULONG   MMIOBase, ULONG value)
+{
+    return ((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_READ_REG) & value) ? TRUE : FALSE);
+}
+
+ULONG UnlockVideoRegHost(ULONG   MMIOBase, ULONG Key)
+{
+    WriteMemoryLongHost(VIDEO_REG_BASE, KEY_CONTROL_REG, Key);
+    return ReadMemoryLongHost(VIDEO_REG_BASE,KEY_CONTROL_REG);
+}
+
+void StartVideoCaptureTriggerHost(ULONG   MMIOBase, ULONG offset)
+{
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CAPTURE_TRIGGER);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CAPTURE_TRIGGER, VIDEO_CAPTURE_TRIGGER);
+}
+
+void StartVideoCodecTriggerHost(ULONG   MMIOBase, ULONG offset)
+{
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CODEC_TRIGGER);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
+}
+
+void StopModeDetectionTriggerHost(ULONG   MMIOBase, ULONG offset)
+{
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
+}
+
+void ClearVideoInterruptHost(ULONG   MMIOBase, ULONG value)
+{
+    //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value, value);
+	WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value);
+}
+
+/* UnLock SCU Host and Reset Engine */
+BOOL CheckOnStartHost(void)
+{
+    int i=0, dwValue=0;
+    
+    do
+    {
+	dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
+	i++;
+    }
+    while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
+
+    //Clear SCU Reset Register
+    WriteMemoryLongHost(SCU_BASE, SCU_CONTROL_REG, 0);
+
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK), (STOP_ECLK_MASK | STOP_V1CLK_MASK));
+
+#if	defined(CONFIG_AST2300)
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x00000020, 0x00000030);	//enable 24bits
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fff00, 0x000fff00);	//enable video multi-pins    
+#else	//AST2100 
+    //WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_PORTB_EN | VIDEO_VP1_EN | VIDEO_VP2_EN) , 
+    //							(VIDEO_PORTA_MASK | VIDEO_PORTB_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_SINGLE_EDGE) , 
+	      						     (VIDEO_PORTA_SINGLE_EDGE_MASK));
+#endif	      						     
+
+    ResetVideoHost();
+
+    return TRUE;
+}
+
+BOOL CheckOnStartClient(void)
+{
+	int i=0, dwValue=0;
+    
+	do
+	{
+		dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
+		i++;
+	}
+	while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
+
+	//Clear SCU Reset Register
+	WriteMemoryLongClient(SCU_BASE, SCU_CONTROL_REG, 0);
+
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK | EN_D1CLK ), 
+								  (STOP_ECLK_MASK | STOP_D1CLK_MASK ));
+
+	//WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, PORTB_FROM_D2CLK | PORTB_CLOCK_INV_DELAY_3NS | PORTA_CLOCK_INV_DELAY_3NS, PORTB_CLOCK_SEL | PORTB_CLOCK_DELAY_MASK | PORTA_CLOCK_DELAY_MASK);
+	//A1EVA
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, (PORTA_CLOCK_INV_DELAY_1NS), (PORTA_CLOCK_DELAY_MASK));
+	WriteMemoryLongWithMASKClient(SCU_BASE, 0x202C, (0x03<<9), (0x03<<9));
+
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_VP1_EN | VIDEO_VP2_EN), 
+								  (VIDEO_PORTA_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
+
+#if CONFIG_AST3000
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, VIDEO_PORTA_DUAL_EDGE, VIDEO_PORTA_SINGLE_EDGE_MASK));
+#else
+	//2100 is single edge
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, VIDEO_PORTA_SINGLE_EDGE, VIDEO_PORTA_SINGLE_EDGE_MASK);
+#endif
+
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_D1CLK ), (STOP_D1CLK_MASK));
+	WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, VGA_PIN_OFF, VGA_PIN_MASK);
+
+    //ResetVideoHost();
+
+	return TRUE;
+}
+
+ULONG  InitializeVideoEngineHost (ULONG                MMIOBase,
+                               int                  nVideo,
+							   BOOL					HorPolarity,
+							   BOOL					VerPolarity)
+{
+    //ULONG   temp, temp1, temp2; 
+    ULONG   dwRegOffset = nVideo * 0x100;
+    ULONG   dwValue;
+//    int     i;
+
+
+    /* General Video Control */
+    //LineBufEn 0
+    //dwValue = (COMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT) | DELAY_VSYNC_EN;
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
+    //Video Data Truncation Register
+	WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
+
+	//D2CLK clock must config according to video's line buffer (D2CLK DOES NOT EXIST IN AST2050)
+	if (VIDEO1 == nVideo)
+	    dwValue = LINE_BUFFER_VIDEO1;
+//     else
+//         dwValue = LINE_BUFFER_VIDEO2;
+//     
+// 	//D2CLK clock must config according to video's line buffer
+// 	switch (dwValue)
+// 	{
+// 	case LINE_BUFFER_OFF:
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, NORMAL_CRT1, D2CLK_CLOCK_SELECTION_MASK);
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, STOP_D2CLK, STOP_D2CLK_MASK);
+// 		break;
+// 	case LINE_BUFFER_VIDEO1:
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO1 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
+// 		break;
+// 	case LINE_BUFFER_VIDEO2:
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO2 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
+// 		WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
+// 		break;
+// 	case LINE_BUFFER_VIDEOM:
+// 		//If select this option, it will config at videoM INIT
+// 		break;
+// 	default:
+// 		break;
+// 	}
+
+    dwValue = 0;
+    //VR30 now is capture window in the compression
+    dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
+    g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue);        
+
+    dwValue = 0;
+    //VR34 now is destionation window in the compression
+	dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
+	g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
+
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue);        
+
+    //BitCOUNT according compress data format
+    dwValue = YUV444_MODE;
+	if (YUV444_MODE == dwValue)
+		WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
+	else
+		WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
+              
+    //  CRC
+    //Disable
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
+    
+    /* Sequence Control register */
+	//Oonly Encoder need to set
+	/* Engine Sequence Contol Register */
+	dwValue = (WATCH_DOG_EN << WATCH_DOG_ENABLE_BIT) |
+	            VIDEO_CAPTURE_AUTO_MODE |
+	            VIDEO_CODEC_AUTO_MODE;
+    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
+    
+    /* Control register */
+	dwValue = (HOR_NEGATIVE == HorPolarity) ? NO_INVERSE_POL : INVERSE_POL;
+	dwValue = (((VER_NEGATIVE == VerPolarity) ? NO_INVERSE_POL : INVERSE_POL) << VIDEO_VSYNC_POLARITY_BIT) | dwValue;
+    
+	/* HW Recommand*/
+	//dwValue = (TILE_MODE << 9) | dwValue;
+	dwValue = (EXTERNAL_VGA_SOURCE << EXTERNAL_SOURCE_BIT) | dwValue;
+    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
+        
+    /* BCD register */
+    //NO BCD
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
+
+    /* Stream Buffer Size register */
+    dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
+                (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
+                (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
+    /* the same with Video1, Video2, and VideoM*/
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
+
+    /* Comression control register */
+    dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
+                (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
+                (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
+                (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
+                (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
+                (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
+   
+    //Video2 have same value as video1
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
+
+    /* JPEG Quantization Table register */
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
+    
+    /* Quantization value register */
+    //Video2 have same value as video1
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
+
+    //Video BSD Parameter Register
+    //Video2 have same value as video1
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
+
+    //no scale
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_REG,  0x10001000);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER0_REG, 0x00200000);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER1_REG, 0x00200000);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER2_REG, 0x00200000);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER3_REG, 0x00200000);
+    return TRUE;
+}
+
+ULONG  InitializeVideoEngineClient (ULONG                MMIOBase,
+                               int                  nVideo)
+{
+    //ULONG   temp, temp1, temp2; 
+    ULONG   dwRegOffset = nVideo * 0x100;
+    ULONG   dwValue;
+    int     i;
+
+
+    /* General Video Control */
+    //LineBufEn 0
+    dwValue = (DECOMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
+    //Video Data Truncation Register
+	WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
+
+    //VR30 now is capture window in the compression
+    dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
+    g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue, CAPTURE_VER_LINE_MASK | CAPTURE_HOR_PIXEL_MASK);        
+
+    //VR34 now is destionation window in the compression
+	dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
+	g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
+
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue, COMPRESS_VER_LINE_MASK | COMPRESS_HOR_PIXEL_MASK);        
+
+    //BitCOUNT according compress data format
+    dwValue = YUV444_MODE;
+	if (YUV444_MODE == dwValue)
+		WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
+	else
+		WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
+              
+    //  CRC
+    //Disable
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
+    
+    /* Sequence Control register */
+	//Oonly Encoder need to set
+	/* Engine Sequence Contol Register */
+    dwValue = VIDEO_CAPTURE_AUTO_MODE |
+        VIDEO_CODEC_AUTO_MODE;
+    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
+    
+    /* Control register */
+	/* HW Recommand*/
+	dwValue = (TILE_MODE << 9); 	
+    
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
+        
+    /* BCD register */
+    //NO BCD
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
+
+    /* Stream Buffer Size register */
+    dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
+                (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
+                (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
+    /* the same with Video1, Video2, and VideoM*/
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
+        
+
+    /* Comression control register */
+    dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
+                (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
+                (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
+                (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
+                (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
+                (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
+   
+    //Video2 have same value as video1
+    if (VIDEO1 == nVideo)
+    {
+        WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
+    }
+    else
+    {
+        WriteMemoryLongHost(VIDEO_REG_BASE, VIDEOM_COMPRESS_CONTROL_REG, dwValue);
+    }
+
+    /* JPEG Quantization Table register */
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
+    
+    /* Quantization value register */
+    //Video2 have same value as video1
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
+
+    //Video BSD Parameter Register
+    //Video2 have same value as video1
+    dwValue = 0;
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
+
+    return TRUE;
+}
+
+BYTE  GetI2CRegClient(ULONG  MMIOBase, 
+				 BYTE DeviceSelect, 
+				 BYTE DeviceAddress, 
+				 BYTE RegisterIndex)
+{
+    BYTE    Data;
+    ULONG   Status;
+
+//  Reset
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
+//  Set AC Timing and Speed
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
+//  Lower Speed
+//    WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Enable Master Mode
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
+//  Enable Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
+//  BYTE I2C Mode
+//  Start and Send Device Address
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
+//  Wait TX ACK
+    do {
+        Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
+    } while (Status != 1);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Send Device Register Index
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
+//  Wait Tx ACK
+    do {
+        Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
+    } while (Status != 1);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Start, Send Device Address + 1(Read Mode), Receive Data
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress + 1);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x1B);
+//  Wait Rx Done
+    do {
+        Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x04) >> 2;
+    } while (Status != 1);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+
+//  Enable STOP Interrupt
+    WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
+//  Issue STOP Command
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
+//  Wait STOP
+    do {
+        Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
+    } while (Status != 1);
+//  Disable STOP Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Read Received Data
+    Data = (BYTE)((ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20) & 0xFF00) >> 8);
+
+    return    Data;
+}
+
+ULONG  SetI2CRegClient(ULONG  MMIOBase, 
+                 BYTE   DeviceSelect, 
+                 BYTE   DeviceAddress, 
+                 BYTE   RegisterIndex, 
+                 BYTE   RegisterValue)
+{
+    ULONG   Status; 
+	ULONG   Count = 0;
+
+//  Reset
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
+//  Set Speed
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
+//  Lower Speed
+//    WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Enable Master Mode
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
+//  Enable Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
+//  BYTE I2C Mode
+//  Start and Send Device Address
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
+//  Wait Tx ACK
+    do {
+        Count++;
+        Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
+
+		if (2 == Status)
+		{
+			//Clear Interrupt
+			WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+			//Re-Send Start and Send Device Address while NACK return
+			WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
+			WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
+		}
+		//else
+		{
+			if (Count > LOOP_COUNT) {
+				return CAN_NOT_FIND_DEVICE;
+			}
+		}
+    } while (Status != 1);
+    Count = 0;
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Send Device Register Index
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
+//  Wait Tx ACK
+    do {
+        Count++;
+        Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
+        if (Count > LOOP_COUNT) {
+            return CAN_NOT_FIND_DEVICE;
+        }
+    } while (Status != 1);
+    Count = 0;
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Send Device Register Value and Stop
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterValue);
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
+//  Wait Tx ACK
+    do {
+        Count++;
+        Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
+        if (Count > LOOP_COUNT) {
+            return CAN_NOT_FIND_DEVICE;
+        }
+    } while (Status != 1);
+    Count = 0;
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+//  Enable STOP Interrupt
+    WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
+//  Issue STOP Command
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
+//  Wait STOP
+    do {
+        Count++;
+        Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
+        if (Count > LOOP_COUNT) {
+            return CAN_NOT_FIND_DEVICE;
+        }
+    } while (Status != 1);
+//  Disable STOP Interrupt
+    WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0, 0x10);
+//  Clear Interrupt
+    WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
+
+    return SET_I2C_DONE;
+}
diff --git a/board/aspeed/ast2050/vfun.h b/board/aspeed/ast2050/vfun.h
new file mode 100644
index 0000000..2f7f382
--- /dev/null
+++ b/board/aspeed/ast2050/vfun.h
@@ -0,0 +1,81 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _VFUN_H_
+#define _VFUN_H_
+
+//#define vBufAlign(x)		    ((x + 0x0000007F) & 0xFFFFFF80) //128 byte alignment
+#define vBufAlign(x)		    ((x + 0x000003FF) & 0xFFFFFC00) //128 byte alignment
+#define vBufAlign2(x)		    ((x + 0x0000FFFF) & 0xFFFF0000) //128 byte alignment
+#define v16byteAlign(x)		    ((x + 0x0000000F) & 0xFFFFFFF0)
+#define vBuf_ALIGNMENT			128
+
+#define HOST_TOTAL_SIZE         0x8000000   /* 128M */
+#define STATION_TOTAL_SIZE      0xF800000   /* 120M */
+
+#define VIDEO_SOURCE_SIZE       0x200000    /* 800X600X4 = 0x1D4C00 */
+#define VIDEO_MAX_STREAM_SIZE   0x400000    /* 32X128K = 0x400000 */
+#define VIDEO_FLAG_SIZE         0x5000      /* 1920X1200/128 = 0x4650*/ 
+#define VIDEO_CRC_SIZE          0x50000     /* 1920/64X1200X8 = 0x46500*/
+
+#define VIDEO1_EN_TOTAL_SIZE    (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE+VIDEO_CRC_SIZE) /* 0x1655000 =  about 23M*/
+#define VIDEO2_EN_TOTAL_SIZE    VIDEO1_EN_TOTAL_SIZE
+//#define VIDEOM_EN_TOTAL_SIZE    (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE) /* 0x1605000 = about 22.7M */
+//#define VIDEO_HOST_SIZE         (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE + VIDEOM_EN_TOTAL_SIZE) /* 0x69922816 = about 70M */
+#define VIDEO_HOST_SIZE         (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE) /* NOT NEED VIDEOM */
+
+#define VIDEO1_EN_BASE          0x100000
+#define VIDEO2_EN_BASE          (VIDEO1_EN_BASE + VIDEO1_EN_TOTAL_SIZE)
+#define VIDEOM_EN_BASE          (VIDEO2_EN_BASE + VIDEO2_EN_TOTAL_SIZE)
+
+#define VIDEO1_DE_TOTAL_SIZE    (VIDEO_MAX_STREAM_SIZE + VIDEO_SOURCE_SIZE) /* 0xD00000 = 13M*/
+#define VIDEO2_DE_TOTAL_SIZE    (VIDEO1_DE_TOTAL_SIZE)
+#define VIDEO_STATION_SIZE      (VIDEO1_DE_TOTAL_SIZE + VIDEO2_DE_TOTAL_SIZE) /* 26M */
+
+#define VIDEO1_DE_BASE          VIDEO_HOST_SIZE
+#define VIDEO2_DE_BASE          (VIDEO1_DE_BASE + VIDEO1_DE_TOTAL_SIZE)
+#define VIDEO_ALL_SIZE          (VIDEO_HOST_SIZE + VIDEO_STATION_SIZE) //Host and Station
+
+#define OutdwmBankModeHost(offset,data)         WriteMemoryLongHost(DRAM_BASE,offset,data)
+#define IndwmBankModeHost(offset)               ReadMemoryLongHost(DRAM_BASE,offset)      
+
+ULONG UnlockVideoRegHost(ULONG   MMIOBase, ULONG Key);
+BOOL CheckOnStartHost(void);
+BOOL CheckOnStartClient(void);
+void StartVideoCaptureTriggerHost(ULONG   MMIOBase, ULONG offset);
+void StartVideoCaptureTriggerHost(ULONG   MMIOBase, ULONG offset);
+void StartVideoCodecTriggerHost(ULONG   MMIOBase, ULONG offset);
+ULONG UnlockSCURegHost(ULONG   MMIOBase, ULONG Key);
+ULONG UnlockSCURegHost(ULONG   MMIOBase, ULONG Key);
+void StartModeDetectionTriggerHost(ULONG   MMIOBase, ULONG offset);
+void ClearVideoInterruptHost(ULONG   MMIOBase, ULONG value);
+BOOL ReadVideoInterruptHost(ULONG   MMIOBase, ULONG value);
+void StopModeDetectionTriggerHost(ULONG   MMIOBase, ULONG offset);
+void ResetVideoHost(void);
+ULONG  InitializeVideoEngineHost (ULONG                MMIOBase,
+                               int                  nVideo,
+							   BOOL					HorPolarity,
+				  BOOL					VerPolarity);
+ULONG  InitializeVideoEngineClient (ULONG                MMIOBase,
+				    int                  nVideo);
+BYTE  GetI2CRegClient(ULONG  MMIOBase, 
+				 BYTE DeviceSelect, 
+				 BYTE DeviceAddress, 
+				 BYTE RegisterIndex);
+
+ULONG  SetI2CRegClient(ULONG  MMIOBase, 
+                 BYTE   DeviceSelect, 
+                 BYTE   DeviceAddress, 
+                 BYTE   RegisterIndex, 
+				 BYTE   RegisterValue);
+#endif //_VFUN_H_
+
diff --git a/board/aspeed/ast2050/vgahw.h b/board/aspeed/ast2050/vgahw.h
new file mode 100644
index 0000000..43dd017
--- /dev/null
+++ b/board/aspeed/ast2050/vgahw.h
@@ -0,0 +1,177 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/******************************************************************************
+ * Mode Stuff
+ ******************************************************************************/
+/* Default Settings */
+#define CRT_LOW_THRESHOLD_VALUE         0x12
+#define CRT_HIGH_THRESHOLD_VALUE        0x1E
+
+/* Output Selection */
+#define CRT1				0x00
+#define CRT2				0x01
+#define DVI1				0x10
+#define DVI2				0x11
+#define LVDS1				0x20
+#define LVDS2				0x21
+
+/* Mode Limitation */
+#define MAX_HResolution		1600
+#define MAX_VResolution		1200
+ 
+/* Std. Table Index Definition */
+#define TextModeIndex 		0
+#define EGAModeIndex 		1
+#define VGAModeIndex 		2
+#define HiCModeIndex 		3
+#define TrueCModeIndex 		4
+
+/* DCLK Index */
+#define VCLK25_175     		0x00
+#define VCLK28_322     		0x01
+#define VCLK31_5       		0x02
+#define VCLK36         		0x03
+#define VCLK40         		0x04
+#define VCLK49_5       		0x05
+#define VCLK50         		0x06
+#define VCLK56_25      		0x07
+#define VCLK65		 	0x08
+#define VCLK75	        	0x09
+#define VCLK78_75      		0x0A
+#define VCLK94_5       		0x0B
+#define VCLK108        		0x0C
+#define VCLK135        		0x0D
+#define VCLK157_5      		0x0E
+#define VCLK162        		0x0F
+#define VCLK119        		0x10
+
+/* Flags Definition */
+#define Charx8Dot               0x00000001
+#define HalfDCLK                0x00000002
+#define DoubleScanMode          0x00000004
+#define LineCompareOff          0x00000008
+#define SyncPP                  0x00000000
+#define SyncPN                  0x00000040
+#define SyncNP                  0x00000080
+#define SyncNN                  0x000000C0
+#define HBorder                 0x00000020
+#define VBorder                 0x00000010
+#define COLORINDEX		0x00000000
+#define MONOINDEX		0x00000100
+
+/* DAC Definition */
+#define DAC_NUM_TEXT		64
+#define DAC_NUM_EGA		64
+#define DAC_NUM_VGA		256
+
+/* AST3000 Reg. Definition */
+#define	AST3000_VGAREG_BASE	0x1e6e6000
+#define AST3000_VGA1_CTLREG	0x00
+#define AST3000_VGA1_CTLREG2	0x04
+#define AST3000_VGA1_STATUSREG	0x08 
+#define AST3000_VGA1_PLL	0x0C
+#define AST3000_VGA1_HTREG	0x10
+#define AST3000_VGA1_HRREG	0x14
+#define AST3000_VGA1_VTREG	0x18
+#define AST3000_VGA1_VRREG	0x1C
+#define AST3000_VGA1_STARTADDR	0x20
+#define AST3000_VGA1_OFFSETREG	0x24
+#define AST3000_VGA1_THRESHOLD	0x28
+#define AST3000_HWC1_OFFSET     0x30
+#define AST3000_HWC1_XY		0x34
+#define AST3000_HWC1_PBase      0x38
+#define AST3000_OSD1_H          0x40
+#define AST3000_OSD1_V          0x44
+#define AST3000_OSD1_PBase      0x48
+#define AST3000_OSD1_Offset     0x4C
+#define AST3000_OSD1_THRESHOLD  0x50
+
+#define AST3000_VGA2_CTLREG	0x60
+#define AST3000_VGA2_CTLREG2	0x64
+#define AST3000_VGA2_STATUSREG	0x68 
+#define AST3000_VGA2_PLL	0x6C
+#define AST3000_VGA2_HTREG	0x70
+#define AST3000_VGA2_HRREG	0x74
+#define AST3000_VGA2_VTREG	0x78
+#define AST3000_VGA2_VRREG	0x7C
+#define AST3000_VGA2_STARTADDR	0x80
+#define AST3000_VGA2_OFFSETREG	0x84
+#define AST3000_VGA2_THRESHOLD	0x88
+#define AST3000_HWC2_OFFSET     0x90
+#define AST3000_HWC2_XY		0x94
+#define AST3000_HWC2_PBase      0x98
+#define AST3000_OSD2_H          0xA0
+#define AST3000_OSD2_V          0xA4
+#define AST3000_OSD2_PBase      0xA8
+#define AST3000_OSD2_Offset     0xAC
+#define AST3000_OSD2_THRESHOLD  0xB0
+
+/* Data Structure */
+typedef struct {
+    UCHAR ModeName[20];
+    USHORT usModeIndex;
+    USHORT usModeID;
+    USHORT usColorIndex;
+    USHORT usRefreshRateIndex;
+    USHORT usWidth;
+    USHORT usHeight;
+    USHORT usBitsPerPlane;
+    USHORT usRefreshRate;    
+} ModeInfoStruct;
+
+typedef struct {
+	
+    UCHAR MISC;	
+    UCHAR SEQ[4];
+    UCHAR CRTC[25];
+    UCHAR AR[20];	    
+    UCHAR GR[9];
+    
+} VBIOS_STDTABLE_STRUCT, *PVBIOS_STDTABLE_STRUCT;
+
+typedef struct {
+	
+    ULONG HT;
+    ULONG HDE;
+    ULONG HFP;
+    ULONG HSYNC;
+    ULONG VT;
+    ULONG VDE;
+    ULONG VFP;
+    ULONG VSYNC;
+    ULONG DCLKIndex;        
+    ULONG Flags;
+
+    ULONG ulRefreshRate;
+    ULONG ulRefreshRateIndex;
+    ULONG ulModeID;
+        
+} VBIOS_ENHTABLE_STRUCT, *PVBIOS_ENHTABLE_STRUCT;
+
+typedef struct {
+    UCHAR Param1;
+    UCHAR Param2;
+    UCHAR Param3;	
+} VBIOS_DCLK_INFO, *PVBIOS_DCLK_INFO;
+
+typedef struct {
+    UCHAR DACR;
+    UCHAR DACG;
+    UCHAR DACB;	
+} VBIOS_DAC_INFO, *PVBIOS_DAC_INFO;
+
+typedef struct {
+    PVBIOS_STDTABLE_STRUCT pStdTableEntry;
+    PVBIOS_ENHTABLE_STRUCT pEnhTableEntry;
+    	
+} VBIOS_MODE_INFO, *PVBIOS_MODE_INFO;
diff --git a/board/aspeed/ast2050/vhace.c b/board/aspeed/ast2050/vhace.c
new file mode 100644
index 0000000..59166f4
--- /dev/null
+++ b/board/aspeed/ast2050/vhace.c
@@ -0,0 +1,68 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define HASH_GLOBALS
+#include "type.h"
+#include "vdef.h"
+#include "vhace.h"
+#include "vfun.h"
+
+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode)
+{
+	ULONG i, ulTemp, ulCommand, ulDigestLength=0;
+	ULONG ulValue;
+   
+	/* Get Info */
+	switch (ulHashMode)
+	{
+	case VHASHMODE_MD5:
+		ulCommand = VHASH_ALG_SELECT_MD5;
+		ulDigestLength = 16;
+		break;
+	case VHASHMODE_SHA1:
+		ulCommand = VHASH_ALG_SELECT_SHA1;
+		ulDigestLength = 20;
+		break;
+	case VHASHMODE_SHA256:
+		ulCommand = VHASH_ALG_SELECT_SHA256;
+		ulDigestLength = 32;
+		break;
+	case VHASHMODE_SHA224:
+		ulCommand = VHASH_ALG_SELECT_SHA224;
+		ulDigestLength = 28;
+		break;       	
+	}
+   	
+	/* Init. HW */
+	WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_SRC_BASE_OFFSET, g_HashSrcBuffer);
+	WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_DST_BASE_OFFSET, g_HashDstBuffer);
+	WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_LEN_OFFSET, ulLength);
+        
+    /* write src */
+	//already fill in g_VIDEO1_COMPRESS_BUF_ADDR
+
+    /* fire cmd */
+	WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_CMD_OFFSET, ulCommand);
+    
+    /* get digest */
+    do {
+    	ulTemp = ReadMemoryLongHost(VHAC_REG_BASE, VREG_HASH_STATUS_OFFSET);
+    } while (ulTemp & VHASH_BUSY);	
+    	
+    for (i=0; i<ulDigestLength/4; i++)
+    {
+                ulValue = *(((ULONG *)g_HashDstBuffer) + i); 
+
+		//output is ULONG pointer
+		*(output + i) = ulValue;    
+    }        
+}
diff --git a/board/aspeed/ast2050/vhace.h b/board/aspeed/ast2050/vhace.h
new file mode 100644
index 0000000..885515e
--- /dev/null
+++ b/board/aspeed/ast2050/vhace.h
@@ -0,0 +1,60 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _VHACE_H_
+#define _VHACE_H_
+
+#define VHASHMODE_MD5			0x00
+#define VHASHMODE_SHA1			0x01
+#define VHASHMODE_SHA256			0x02
+#define VHASHMODE_SHA224			0x03
+
+#define VHASH_ALG_SELECT_MASK		0x70
+#define VHASH_ALG_SELECT_MD5			0x00
+#define VHASH_ALG_SELECT_SHA1		0x20
+#define VHASH_ALG_SELECT_SHA224		0x40
+#define VHASH_ALG_SELECT_SHA256		0x50
+
+#define VHASH_BUSY			0x01
+
+#define VHAC_REG_BASE 			0x1e6e0000
+#define	VHAC_REG_OFFSET			0x3000
+
+#define VREG_HASH_SRC_BASE_OFFSET	(0x20+VHAC_REG_OFFSET)
+#define VREG_HASH_DST_BASE_OFFSET	(0x24+VHAC_REG_OFFSET)
+#define VREG_HASH_KEY_BASE_OFFSET	(0x28+VHAC_REG_OFFSET)
+#define VREG_HASH_LEN_OFFSET			(0x2C+VHAC_REG_OFFSET)
+#define VREG_HASH_CMD_OFFSET			(0x30+VHAC_REG_OFFSET)
+
+#define VREG_HASH_STATUS_OFFSET		(0x1C+VHAC_REG_OFFSET)
+
+typedef struct
+{
+	int HashMode;
+	int DigestLen;
+} HASH_METHOD;
+
+
+#ifdef HASH_GLOBALS
+#define HASH_EXT
+#else
+#define HASH_EXT extern
+#endif
+
+HASH_EXT HASH_METHOD	g_HashMethod;
+HASH_EXT BYTE			g_DigestBuf[32];
+HASH_EXT ULONG			g_HashSrcBuffer;
+HASH_EXT ULONG			g_HashDstBuffer;
+
+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode);
+#endif
+
diff --git a/board/aspeed/ast2050/videotest.c b/board/aspeed/ast2050/videotest.c
new file mode 100644
index 0000000..f0ccf66
--- /dev/null
+++ b/board/aspeed/ast2050/videotest.c
@@ -0,0 +1,781 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Diagnostics support
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <post.h>
+
+#include "slt.h"
+#define WIN_GLOBALS
+#include "type.h"
+#include "vreg.h"
+#define VESA_GLOBALS
+#include "vesa.h"
+#include "vfun.h"
+#include "vdef.h"
+#include "vhace.h"
+#include "crt.h"
+#include "videotest.h"
+
+#define VHASH_ALIGNMENT			16
+#define VHASH_MAX_DST			(32+VHASH_ALIGNMENT)
+
+
+#if ((CFG_CMD_SLT & CFG_CMD_VIDEOTEST) && defined(CONFIG_SLT))
+#include "videotest.h"
+
+#define RAND_MAX 32767 //2^16-1
+
+ULONG randSeed = 1;
+
+void srand(ULONG seed)
+{
+  randSeed = seed;
+}
+
+int rand(void)
+{
+  randSeed = randSeed * 214013 + 2531011;
+  return (int)(randSeed >> 17); //32 -15 = 17
+}
+
+//static unsigned char CaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE], CaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE], Video1CompressBufAddr[CRYPTO_MAX_CONTEXT];
+ULONG pCaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo1CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo1FlagBufAddr[VIDEO_FLAG_SIZE];
+ULONG pCaptureVideo2Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo2Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo2CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo2FlagBufAddr[VIDEO_FLAG_SIZE];
+
+ULONG pVHashDstBuffer[VHASH_MAX_DST/4];
+
+ULONG pVideo1DecAddr[VIDEO_SOURCE_SIZE/4];
+ULONG pCrt1Addr[VIDEO_SOURCE_SIZE/4];
+//ULONG pCap1Addr[VIDEO_SOURCE_SIZE/4];
+
+BOOL AllocateEncodeBufHost(ULONG MMIOBase, int nVideo)
+{
+    //ULONG     Addr;
+    //ULONG     dwRegOffset = nVideo * 0x100;
+
+    if (VIDEO1 == nVideo)
+    {
+        
+        //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
+        //pCaptureVideo1Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
+
+        g_CAPTURE_VIDEO1_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf1Addr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_CAPTURE_VIDEO1_BUF1_ADDR, BUF_1_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
+        //pCaptureVideo1Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
+
+        g_CAPTURE_VIDEO1_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf2Addr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_CAPTURE_VIDEO1_BUF2_ADDR, BUF_2_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
+        //pVideo1CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
+        g_VIDEO1_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo1CompressBufAddr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
+        //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
+        //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
+        
+
+        //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth  / 128 (/64*4/8));
+        //pVideo1FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
+        g_VIDEO1_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo1FlagBufAddr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_FLAG_BUF_ADDR_REG, g_VIDEO1_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
+    }
+    else if (VIDEO2 == nVideo)
+    {
+        //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
+        //pCaptureVideo2Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
+        g_CAPTURE_VIDEO2_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf1Addr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_1_ADDR_REG, g_CAPTURE_VIDEO2_BUF1_ADDR, BUF_1_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
+        //pCaptureVideo2Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
+        g_CAPTURE_VIDEO2_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf2Addr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_2_ADDR_REG, g_CAPTURE_VIDEO2_BUF2_ADDR, BUF_2_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
+        //pVideo2CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
+        g_VIDEO2_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo2CompressBufAddr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_COMPRESS_BUF_ADDR_REG, g_VIDEO2_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
+        
+        //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
+        //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
+        //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
+        
+
+        //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth  / 128 (/64*4/8));
+        //pVideo2FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
+        g_VIDEO2_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo2FlagBufAddr);
+        WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_FLAG_BUF_ADDR_REG, g_VIDEO2_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
+    }
+  
+}
+
+/********************************************************/
+/* 1. product random data to encode                     */
+/* 2. use hash to verify encode function                */
+/* 3. use encode stream to decompress original data     */
+/********************************************************/
+int CodecTest(void)
+{
+    int	  num, i=0, j=0;
+    ULONG ulTemp = 0, ulTemp2;
+    int   dwValue;
+    ULONG ulHWWp;
+    ULONG ulHWPt;
+
+    //max size
+    ULONG tArray[32/4];
+    
+    //mode detection
+    BOOL	bExternal = TRUE;
+    BOOL	bAnalog = TRUE;
+    ULONG	Status;	    
+
+#if defined(CONFIG_AST2300)
+    ULONG ulHashSha1[5]  = {0x3f0c2ad6,0xc8eb7074,0xa9929352,0xfcd5b8b0,0x76fa8461};
+    ULONG aHashDecode[5] = {0xb23b62bb,0xd22a602b,0x113038a0,0x7217c6ab,0xcb156f06};
+#else
+    ULONG ulHashSha1[5] = {0x2a19e99f,0x99b1bb2d,0x9ac82862,0x49205e43,0x6bc4b4d7};
+    ULONG aHashDecode[5] = {0x2907a827,0xaf337079,0x47817f1f,0xb0b7cd68,0x8d33bd2};
+#endif
+
+    //Load pattern to src1 & src2 buffer
+    srand(1);
+
+    //Total size : DefWidth*DeHeight*4
+    //rand function: 16 bits one time is equal to 2 bytes
+    //OutdwmBankMode: 32 bits one time is equal to 4 bytes
+    for (i=0; i<g_DefWidth*g_DefHeight*2; i++)
+    {
+	if (i%2)
+	{
+	    ulTemp2 = rand();
+	    ulTemp = (ulTemp2 << 16) | ulTemp;
+	    //WriteMemoryLongHost(DRAM_BASE, g_CAPTURE_VIDEO1_BUF1_ADDR + ((i-1)/2)*4, ulTemp);
+	    *(((ULONG *)g_CAPTURE_VIDEO1_BUF1_ADDR) + (i-1)/2) = ulTemp;
+	    ulTemp = 0;
+	}
+	else
+	{
+	    ulTemp = rand();
+	}
+    }
+
+    /* init encoder engine */
+    InitializeVideoEngineHost (0,
+			       VIDEO1,
+			       vModeTable[2].HorPolarity,
+			       vModeTable[2].VerPolarity);
+
+    /* reset offset pointer register*/    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
+
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
+
+    /* start compress stream */
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
+    //Stream mode: set CODEC trigger first
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
+
+    //Stream mode: start trigger (only trigger capture bit)
+    StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
+
+    //stop engine
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, 0xFF);    
+#if defined(CONFIG_AST2300)
+    do {	/* wait compress engine idle */
+	ulTemp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);    	
+    } while (!(ulTemp & 0x40000));	
+#endif
+
+    //read 30 times to get HW write pointer
+    for (i=0; i<30000; i++)
+	ulHWWp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
+
+    g_HashSrcBuffer = g_VIDEO1_COMPRESS_BUF_ADDR + 128; //skip encode data 128 byte	
+    g_HashDstBuffer = v16byteAlign((unsigned long)pVHashDstBuffer);
+    ulTemp = 300;
+
+    //Enable hash clock
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
+    g_HashMethod.HashMode = VHASHMODE_SHA1;
+    g_HashMethod.DigestLen = 20;
+    HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
+
+    if (strncmp((const char *)tArray, (const char *)ulHashSha1, g_HashMethod.DigestLen))
+    {
+	printf("[VIDEO] Encoder Test: Wrong\n");
+        //ExitVideoTest();
+        return VIDEO_ENCODE_FAIL;
+    }
+    else
+    {    
+	printf("[VIDEO] Encoder Test: Pass\n");
+    }
+
+#if 0
+    /******** prepare for next decoding test at the same chip ***********/
+    ResetVideoHost();
+
+    dwValue=0;
+
+    do
+    {
+	dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
+	i++;
+    }
+    while ((VIDEO_UNLOCK != dwValue) && (i<10));
+
+    if (VIDEO_UNLOCK != dwValue)
+    {
+	printf("[VIDEO] Video register is locked");
+	return VIDEO_UNLOCK_FAIL;
+    }
+
+    // allocate decoding buffer
+    //Use Compress buffer last time, and Don't need to allocate
+    g_VIDEO1_DECODE_BUF_1_ADDR = g_VIDEO1_COMPRESS_BUF_ADDR;
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_VIDEO1_DECODE_BUF_1_ADDR, BUF_1_ADDR_MASK);
+    
+    //	pVideo1DecAddr = malloc(VIDEO_SOURCE_SIZE);
+    g_VIDEO1_DECOMPRESS_BUF_ADDR = vBufAlign((unsigned long)pVideo1DecAddr);    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, COMPRESS_BUF_ADDR_MASK);
+    
+    //Addr = (ULONG)malloc(256);
+    //g_VIDEO1_RC4_BUF_ADDR = Addr;
+    //g_VIDEO1_DECODE_RC4_BUF_ADDR = g_VIDEO1_DECOMPRESS_BUF_ADDR + 0x800000; //assume video size is 8MB for umcompressed buf;
+    //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_RC4_TABLE_ADDR, g_VIDEO1_DECODE_RC4_BUF_ADDR, RC4_TABLE_ADDR_MASK);
+
+    //HW recommanded value
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
+    //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, 0, BUF_2_ADDR_MASK);            
+
+    /* init encoder engine */
+    InitializeVideoEngineClient (0, VIDEO1);
+
+    /* reset offset pointer register*/    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
+
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
+
+    StartVideoCodecTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
+
+    //wrtie SW write pointer
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
+
+    i = 0;
+
+    do
+    {
+        ulHWPt = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
+        i++;
+    }while((ulHWPt != ulHWWp) && (i<10000));
+
+    if (10000 > i)
+    {
+ 	printf("[VIDEO] Decoder Pointer cannot move!!! /n");
+        //ExitVideoTest();
+	return VIDEO_DECODE_FAIL;       
+    }
+        
+    //8*8 YUVA block
+    for (i=24; i<g_DefWidth*g_DefHeight; i=i+32)
+    {
+        *(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i) = 0x0;
+	*(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i+1) = 0x0;
+    }
+
+    g_HashSrcBuffer = g_VIDEO1_DECOMPRESS_BUF_ADDR;
+    //g_HashDstBuffer = VIDEO1_EN_BASE + VIDEO_ALL_SIZE; //config forward
+
+    ulTemp = 300;
+
+    //Enable hash clock
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
+    g_HashMethod.HashMode = VHASHMODE_SHA1;
+    g_HashMethod.DigestLen = 20;
+    HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
+
+    if (strncmp((const char *)tArray, (const char *)aHashDecode, g_HashMethod.DigestLen))
+    {
+	printf("[VIDEO] Decoder Test: Wrong\n");
+        //ExitVideoTest();
+        return VIDEO_DECODE_FAIL;
+    }
+    else
+    {
+	printf("[VIDEO] Decoder Test: Pass\n");
+    }
+#endif
+
+    return VIDEO_TEST_OK;
+}
+
+/********************************************************/
+/*  Only used in the host                               */
+/*  test function: Mode detection and Capture pattern   */
+/********************************************************/
+int CapTest(void)
+{
+    ULONG   dwValue, Status;
+    int     i;
+    BOOL    bAnalog;
+    ULONG	HStart, HEnd, VStart, VEnd;
+    USHORT	usCRTHor, usCRTVer;
+    ULONG   ulHor, ulVer;
+    ULONG   ulVGABaseAddr, ulCapAddr;
+    ULONG   ulFlag;
+    
+    printf("\n --------- Mode Detection Test --------- \n");
+    //clear clear register
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, 0);
+    dwValue = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG);
+
+    //  Note: Current mode detection procedure has to set signal input 1st
+    //Note: Clear and enable interrupt Encode
+    ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_EN_REG, VIDEO1_MODE_DETECTION_READY_INT_EN, VIDEO1_MODE_DETECTION_READY_INT_EN);
+    //  Set input signal
+    dwValue |= EXTERNAL_VGA_SOURCE;
+    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, (dwValue <<EXTERNAL_SOURCE_BIT), EXTERNAL_SOURCE_MASK);
+
+//  Set H/V stable maximum
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_MAXIMUM << VER_STABLE_MAX_BIT), 0x000F0000);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM << HOR_STABLE_MAX_BIT), HOR_STABLE_MAX_BIT_MASK);
+//  Set H/V stable threshold
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_THRESHOLD << VER_STABLE_THRES_BIT), VER_STABLE_THRES_BIT_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD << HOR_STABLE_THRES_BIT), HOR_STABLE_THRES_BIT_MASK);
+    
+    //Trigger mode detection
+    // turn off WATCH_DOG first
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, (WATCH_DOG_OFF << WATCH_DOG_ENABLE_BIT), WATCH_DOG_EN_MASK);
+        
+    //  Note: Clear mode detection ready interrupt
+    //ClearVideoInterrupt(MMIOBase, MODE_DETECTION_READY_CLEAR);
+    StartModeDetectionTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
+
+
+//  Note: Polling mode detection ready interrupt
+    //it sometime take a long time, especially during change mode, 
+    //so the loop count must be big, or you can't pull it by timer
+    i = 0;
+    do {
+
+		Status = ReadVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_READ);
+		i++;
+    } while ((!Status) & (i<500000));
+
+    if (!Status)
+    {
+	printf("[VIDEO] Mode detection error\n");
+        //ExitVideoTest();
+	return VIDEO_TEST_FAIL;
+    }
+
+    HStart	= (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & LEFT_EDGE_LOCATION_MASK) >> LEFT_EDGE_LOCATION_BIT;
+    HEnd	= (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & RIGHT_EDGE_LOCATION_MASK) >> RIGHT_EDGE_LOCATION_BIT;
+
+    VStart	= (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & TOP_EDGE_LOCATION_MASK) >> TOP_EDGE_LOCATION_BIT;
+    VEnd	= (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & BOTTOM_EDGE_LOCATION_MASK) >> BOTTOM_EDGE_LOCATION_BIT;
+
+    ulHor = HEnd-HStart+1;
+    ulVer = VEnd-VStart+1;
+
+    printf("[VIDEO] Resolution: H[%d] * V[%d]\n", ulHor, ulVer);
+
+    if ((g_DefWidth == ulHor) & (g_DefHeight == ulVer))
+    {
+    	printf("[VIDEO] Mode detection PASS\n");
+    }
+    else
+    {
+	printf("[VIDEO] Mode detection FAIL\n");
+	return VIDEO_TEST_FAIL;
+    }
+
+    if(!((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_MODE_DETECTION_STATUS_READ_REG) & ANALONG_DIGITAL_READ) >> ANALONG_DIGITAL_READ_BIT))
+	bAnalog = FALSE;
+    else
+	bAnalog = TRUE;
+
+    //  Note: Clear mode detection ready interrupt
+    ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
+
+    printf("\n --------- Capture Test --------- \n");
+
+    //capture engine
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HEnd << VIDEO_HDE_END_BIT), VIDEO_HDE_END_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HStart << VIDEO_HDE_START_BIT), VIDEO_HDE_START_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VEnd << VIDEO_VDE_END_BIT), VIDEO_VDE_END_MASK);
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VStart << VIDEO_VDE_START_BIT), VIDEO_VDE_START_MASK);
+	
+    ulCapAddr = vBufAlign2((ULONG)pCaptureVideo1Buf1Addr);    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, ulCapAddr, BUF_1_ADDR_MASK);
+    
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
+
+    InitializeVideoEngineHost (0,
+			       VIDEO1,
+		               vModeTable[2].HorPolarity,
+			       vModeTable[2].VerPolarity);
+
+    WriteMemoryLongHost(VIDEO_REG_BASE, 0x04, 0x01);
+    WriteMemoryLongHost(VIDEO_REG_BASE, 0x300, 0x0);
+#if defined(CONFIG_AST2300)
+	WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x0880, 0x0ec0);
+#elif defined(CONFIG_AST3000)
+	WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x2800, 0x2800);	
+#else
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0xa00, 0x2a80); //tile mode
+#endif
+
+    WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, 0xa0000000, 0xa0000000);
+   
+    //only trigger capture, in source buffer (vr44), the front of data is correct.
+    //StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
+    WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CAPTURE_TRIGGER);
+
+    i = 0;
+    do {
+        Status = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG) & CAPTURE_READY_MASK;
+	i++;
+    } while ((!Status) & (i<500000));
+
+    if (!Status)
+    {
+	printf("[VIDEO] Capture is not READY\n");
+	return VIDEO_TEST_FAIL;
+    }  
+
+#if !defined(CONFIG_AST2300)	
+    ulVGABaseAddr = ulCapAddr + 0x1000;
+
+    /* check pattern */
+    ulFlag = 0; //no 0 is error
+
+    for (i=0; i<100; i++)
+    {
+        dwValue = *(ULONG *)(ulVGABaseAddr + i*32);
+	if (0x32323232 != dwValue)
+	{
+	    printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	    printf("[VIDEO]1 i=%d value=%x\n", i, dwValue);
+            ulFlag = 1;
+            break;
+	}
+
+	dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 4);
+	if (0x32323232 != dwValue)
+	{
+	    printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	    printf("[VIDEO]2 i=%d value=%x\n", i, dwValue);
+	    ulFlag = 1;
+	    break;
+	}
+
+	dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 8);
+	if (0x80808080 != dwValue)
+	{
+	    printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	    printf("[VIDEO]3 i=%d value=%x\n", i, dwValue);
+	    ulFlag = 1;
+	    break;
+	}
+
+	dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 12);
+	if (0x80808080 != dwValue)
+	{
+	    printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	    printf("4 i=%d value=%x\n", i, dwValue);
+	    ulFlag = 1;
+	    break;
+	}
+
+	dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 16);
+	if (0x80808080 != dwValue)
+	{
+	   printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	   printf("5 i=%d value=%x\n", i, dwValue);
+	   ulFlag = 1;
+	   break;
+	}
+
+	dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 20);
+	if (0x80808080 != dwValue)
+	{
+	   printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
+	   printf("6 i=%d value=%x\n", i, dwValue);
+	   ulFlag = 1;
+	   break;
+	  }
+    }
+#endif
+
+    if (!ulFlag)
+    {
+        printf("[VIDEO] Capture Test OK\n");
+    }
+    else
+    {
+	printf("[VIDEO] Capture Test FAIL\n");
+	return VIDEO_TEST_FAIL;
+    }
+	
+    return VIDEO_TEST_OK;
+}
+
+/********************************************************/
+/*  Only used in the station                            */
+/********************************************************/
+int CRTTest(void)
+{
+    ULONG   ulVGABaseAddr;
+    BYTE    btCRTCenterMode, btCRTColorFmt;
+    USHORT  usCRTHor, usCRTVer;
+    ULONG   ulData;
+
+    int i,j;
+
+    //printf("\n --------- Turn on CRT --------- \n");
+    
+    //Enable CRT1 first
+    ulVGABaseAddr = vBufAlign((unsigned long)pCrt1Addr);
+    
+    btCRTCenterMode     = 0;
+    btCRTColorFmt	= YUV_444;
+    usCRTHor		= g_DefWidth;
+    usCRTVer		= g_DefHeight;	
+
+    CheckOnStartClient();
+
+    /* Fill Pattern */
+    for (i=0; i<usCRTHor; i++)
+    {
+	for (j=0; j<usCRTVer/8; j++)
+	{
+	    //Y
+	    //ulData = 0x10101010;
+	    ulData = 0x32323232;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32)) = ulData;
+	    //ulData = 0x10101010;
+	    ulData = 0x32323232;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +4) = ulData;
+	    //U
+	    ulData = 0x80808080;
+	    //ulData = 0x77777777;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +8) = ulData;
+	    ulData = 0x80808080;
+	    //ulData = 0x77777777;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +12) = ulData;
+	    //V
+	    ulData = 0x80808080;
+	    //ulData = 0x11111111;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +16) = ulData;
+	    ulData = 0x80808080;
+	    //ulData = 0x11111111;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +20) = ulData;
+	    //A
+	    ulData = 0xFFFFFFFFF;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +24) = ulData;
+	    ulData = 0xFFFFFFFFF;
+	    *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +28) = ulData;
+	}
+    }  /* ~Fill Pattern */
+
+#if defined(CONFIG_AST2300)       
+    if(!ASTSetModeV (0, CRT_2, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
+#else
+    if(!ASTSetModeV (0, CRT_1, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
+#endif    
+    {   
+        printf("[VIDEO] The resolution is not in mode table list\n");
+        return CRT_FAIL;
+    }
+    
+    //printf("[VIDEO] CRT turn on\n");
+
+    return VIDEO_TEST_OK;
+}
+
+int do_videotest (void)
+{
+    int dwValue=0;
+    int i = 0;
+    int iRet;    
+    ULONG   ulRestore1, ulTemp;
+    BOOL    bClient;
+
+
+    //InitVideoTest();
+    g_DefWidth = 640; 
+    g_DefHeight= 480;
+
+    printf("\n --------- Codec Test --------- \n");
+
+#if defined(CONFIG_AST2300)
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0x00002000, 0x00002000);
+#endif
+
+    CheckOnStartHost();
+    
+    do
+    {
+        dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
+	i++;
+    }
+    while ((VIDEO_UNLOCK != dwValue) && (i<1000));
+
+    if (VIDEO_UNLOCK != dwValue)
+    {
+	printf("[VIDEO] Video register is locked \n");
+	return VIDEO_TEST_FAIL;
+    }
+    AllocateEncodeBufHost(0, VIDEO1);
+
+    iRet = CodecTest();	
+    if (iRet)
+        return VIDEO_TEST_FAIL;
+
+#if defined(CONFIG_AST2300)
+    /* Init SCU */ 
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x2c + SCU_OFFSET), 0x00040000, 0x00040010);	/* Enable D2-PLL */
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, 0, 0x00000400);		/* Enable D2CLK */
+    udelay(10);
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0, 0x00002000);
+    
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x20, 0x00000030); 	/* enable video mode single edge */
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x84 + SCU_OFFSET), 0xfffe0000, 0xfffe0000); /* multi-pins */
+    WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fffff, 0x000fffff); /* multi-pins */    
+    
+    iRet = CRTTest();
+    if (iRet)
+    {
+    	printf("[VIDEO] CRT Test Failed \n");
+        return VIDEO_TEST_FAIL;
+    }
+
+    iRet = CapTest();		
+    if (iRet)
+    {
+    	printf("[VIDEO] Capture Test Failed \n");
+        return VIDEO_TEST_FAIL;
+    }
+#else
+    //Host or Client
+    bClient = ((ReadMemoryLong(SCU_BASE, SCU_HW_TRAPPING_REG) & CLIENT_MODE_EN_MASK)?TRUE:FALSE);
+    //reset video for another testing
+    ResetVideoHost();
+    dwValue=0;
+    i = 0;
+    do
+    {
+	dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
+	i++;
+    }
+    while ((VIDEO_UNLOCK != dwValue) && (i<10));
+
+    if (VIDEO_UNLOCK != dwValue)
+    {
+	printf("[VIDEO] Video register is locked");
+	return VIDEO_UNLOCK_FAIL;
+    }
+
+    //check if 1e6e0008[3,0] is 0
+    ulRestore1 = ReadMemoryLongHost(0x1e6e0000, 8);
+    dwValue = ReadMemoryLongHost(0x1e6e0000, 8)&0xF;
+
+    //set 1e6e0008[3,0] to 0
+    if (dwValue)
+    {
+        WriteMemoryLongHost(0x1e6e0000, 0, 0xfc600309);
+        
+        i=0;
+        do
+        {
+            i++;
+            dwValue = ReadMemoryLongHost(0x1e6e0000,0);
+        }while((1 != dwValue)&& (i<10));
+        
+        if (1 != dwValue)
+    	{
+    		printf("0x1e6e0000 is locked");
+    		return VIDEO_UNLOCK_FAIL;
+    	}
+    }
+
+    //only clear 1e6e0008[3,0]
+    WriteMemoryLongWithMASKHost(0x1e6e0000, 8, 0, 0xf);
+    
+    bClient = 0;
+    if (!bClient)
+    {
+        //To turn on crt, must be the client mode
+        WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_CLIENT_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
+            
+        iRet = CRTTest();
+
+        if (iRet)
+        {
+            //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
+            WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
+            //restore value
+            WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
+            //lock register
+            WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678); 
+            return VIDEO_TEST_FAIL;
+        }
+        
+        iRet = CapTest();
+		
+        if (iRet)
+        {
+            //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
+            WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
+            //restore value
+            WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
+            //lock register
+            WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678); 
+
+            return VIDEO_TEST_FAIL;
+        }
+		//WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
+    }
+    //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
+    WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
+    //restore value
+    WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
+    //lock register
+    WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678); 
+#endif
+
+    return VIDEO_TEST_OK;	
+}
+#endif /* CONFIG_SLT */
diff --git a/board/aspeed/ast2050/videotest.h b/board/aspeed/ast2050/videotest.h
new file mode 100644
index 0000000..6648e84
--- /dev/null
+++ b/board/aspeed/ast2050/videotest.h
@@ -0,0 +1,26 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* VideoTest.h */
+#ifndef _VIDEOTEST_H_
+#define _VIDEOTEST_H_
+
+#define VIDEO_TEST_OK       0
+#define VIDEO_TEST_FAIL     1
+
+#define VIDEO_UNLOCK_FAIL   1
+#define VIDEO_ENCODE_FAIL   2
+#define VIDEO_DECODE_FAIL   3
+#define CRT_FAIL            4
+
+#endif /* _VIDEOTEST_H_ */
+
diff --git a/board/aspeed/ast2050/vreg.h b/board/aspeed/ast2050/vreg.h
new file mode 100644
index 0000000..8c286b0
--- /dev/null
+++ b/board/aspeed/ast2050/vreg.h
@@ -0,0 +1,847 @@
+/*
+ *  (c) 2017 Raptor Engineering, LLC
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _VREG_H_
+#define _VREG_H_
+
+/********************************************************/
+/*    CRT register                                      */
+/********************************************************/
+#define    CRT_BASE_ADDRESS                    0x000400
+#define    VGA_GRAPH_BASE_ADDRESS              0x600000
+#define    VGA_CURSOR_BASE_ADDRESS             0x300000
+#define    VGA_OSD_BASE_ADDRESS                0x300000
+#define    RGB_565                             0x0
+#define    RGB_888                             0x1
+#define    YUV_444                             0x2
+#define	   NO_SUPPORTED_CRT_FMT				   0x3
+#define    CRT_LOW_THRESHOLD_VALUE             0x12
+#define    CRT_HIGH_THRESHOLD_VALUE            0x1E
+
+// AST3000's Registers 
+#ifdef Watcom
+#define     VIDEOBASE_OFFSET                            0x10000
+#else
+#define     VIDEOBASE_OFFSET                            0x0
+#endif
+
+#define     KEY_CONTROL_REG                             0x00 + VIDEOBASE_OFFSET
+    #define     VIDEO_LOCKED                            0
+    #define     VIDEO_UNLOCK                            1
+
+// Registers for video1 and video2
+#define     VIDEO1_ENGINE_SEQUENCE_CONTROL_REG          0x04 + VIDEOBASE_OFFSET
+#define     VIDEO2_ENGINE_SEQUENCE_CONTROL_REG          0x104 + VIDEOBASE_OFFSET
+    #define     MODE_DETECTION_TRIGGER                  0x00000001  //Bit[0] trigger HW auto mode detection
+    #define     VIDEO_CAPTURE_TRIGGER                   0x00000002  //Bit[1] trigger HW to capture video
+	#define		FORCE_HW_IDLE_MASK						(1<<2)		//Bit[2] Force engine into ready(idle) state
+		#define		ENGINE_RESET						(0<<2)
+		#define		ENGINE_IDLE							(1<<2)
+    #define     VIDEO_CAPTURE_AUTO_MODE                 0x00000008  //Bit[3]
+        #define     CAPTURE_FRAME_MODE                  0
+        #define     CAPTURE_AUTO_MODE                   1
+		#define		CAPTURE_AUTO_MODE_BIT				3
+		#define		CAPTURE_AUTO_MODE_MASK				0x00000008
+    #define     VIDEO_CODEC_TRIGGER                     0x00000010  //Bit[4] trigger HW to compress or decompress video
+        #define     CODEC_TRIGGER_BIT                   4
+        #define     CODEC_TRIGGER_MASK                  0x00000010
+        #define     CLEAR_CODEC_TRIGGER                 0
+        #define     EN_CODEC_TRIGGER                    1
+    #define     VIDEO_CODEC_AUTO_MODE                   0x00000020  //Bit[5]
+        #define     CODEC_FRAME_MODE                    0
+        #define     CODEC_AUTO_MODE                     1
+		#define		CODEC_AUTO_MODE_BIT					5
+        #define     CODEC_AUTO_MODE_MASK                0x00000020
+	#define		INSERT_FULL_FRAME_MASK					(1<<6)		//Bit[6] Insert full frame compression
+		#define		INSERT_FULL_FRAME_EN				(1<<6)
+		#define		INSERT_FULL_FRAME_OFF				(0<<6)
+    #define     WATCH_DOG_ENABLE                        0x00000080  //Bit[7] Video Enable watch dog for mode change detection
+        #define     WATCH_DOG_ENABLE_BIT                7
+        #define     WATCH_DOG_OFF                       0
+        #define     WATCH_DOG_EN                        1
+        #define     WATCH_DOG_EN_MASK                   0x00000080
+    #define     VIDEO_CRT_SELECTION                     0x00000100  //Bit[8]
+        #define     CRT1                                0
+        #define     CRT2                                1
+    #define     ANTI_TEARING_ENABLE                     0x00000200  //Bit[9] Anti-tearing mode enable for decoding
+        #define     ANTI_TEARING_EN                     1
+    #define     STREAM_DATA_MODE                        0x00000400  //Bit[11:10] Buffer and Stream Data type
+        #define     STREAM_DATA_MODE_BIT                10
+        #define     STREAM_DATA_MODE_MASK               0x00000C00
+        #define     YUV444_MODE                         0
+        #define     YUV420_MODE                         1
+        #define     YUV420_MODE_WITH_AST2000            2 //AST2000 compatible
+    #define     VIDEO_CAPTURE_READY                     0x00010000  //Bit[16] Video capture ready status read back(read only)
+		#define		CAPTURE_READY_MASK                  0x00010000  
+        #define     HW_BUSY                             0
+        #define     HW_IDLE                             1
+    #define     VIDEO_CODEC_READY                       0x00040000  //Bit[18] Video codec ready status read back(read only)
+		#define		CODEC_READY_MASK					0x00040000
+        //#define     HW_BUSY                             0
+        //#define     HW_IDLE                             1
+    
+#define    VIDEO1_CONTROL_REG                           0x08 + VIDEOBASE_OFFSET
+#define    VIDEO2_CONTROL_REG                           0x108 + VIDEOBASE_OFFSET
+    #define     VIDEO_HSYNC_POLARITY                    0x00000001  //Bit[0] Video source hsync polarity
+        #define     VIDEO_HSYNC_POLARITY_BIT            0
+        #define     NO_INVERSE_POL                      0
+        #define     INVERSE_POL							1
+    #define     VIDEO_VSYNC_POLARITY                    0x00000002  //Bit[1] Video source vsync polarity
+        #define     VIDEO_VSYNC_POLARITY_BIT            1        
+        //Setting defination the same as VIDEO_HSYNC_POLARITY
+    #define     VIDEO_EXTERNAL_SOURCE                   0x00000004  //Bit[2] Video external source
+        #define     EXTERNAL_SOURCE_BIT                 2
+        #define     INTERNAL_VGA_SOURCE                 0
+        #define     EXTERNAL_VGA_SOURCE                 1
+        #define     EXTERNAL_SOURCE_MASK                0x00000004                     
+    #define     VIDEO_ANALONG_EXTERNAL_SOURCE           0x00000008  //Bit[3] Video Analog external source
+        #define     ANALONG_EXTERNAL_SOURCE_BIT         3
+        #define     DVI_SOURCE                          0
+        #define     ANALOG_RGB_SOURCE                   1
+    #define     VIDEO_INTERNAL_TIMING_GEN               0x00000010  //Bit[4] Video Use internal timing generator
+        #define     INTERNAL_TIMING_GEN_BIT             4
+        #define     EXTERNAL_DE_SIGNAL                  0 //DVI only
+        #define     VR0C_VR10_DE_SINGAL                 1 //use VR0C and VR10 for generate VDE signal
+    /******     Video2 Only from DAC    ******/        
+    #define     VIDEO1_CAPTURE_FROM                     0x00000020  //Bit[5] Video1 capture data direct from VGA frame buffer(internal VGA only)  
+        #define     FROM_DAC_PORT                       0
+        #define     FROM_FRAME_BUFFER                   1     
+    #define     WRITE_DATA_FORMAT                       0x00000040  //Bit[7:6] Write data format
+        #define     WRITE_DATA_FORMAT_BIT               6
+        #define     WRTIE_DATA_FORMAT_MASK              0x000000C0
+        #define     CCIR601_2_YUV_FORMAT                0
+        #define     FULL_YUV_FORMAT                     1
+        #define     RGB_FORMAT                          2
+		#define     VGA_CURSOR_DISABLE                      0x00000100  //Bit[8] External video port slection
+        #define     VGA_CURSOR_NORMAL                   0
+        #define     VGA_CURSOR_OFF                      1    
+    #define     VIDEO_CAPTURE_LINEAR_MODE               0x00000200  //Bit[9] VIDEO_CAPTURE_LINEAR_MODE
+        #define     LINEAR_MODE                         0
+        #define     TILE_MODE		                    1		
+    #define     VIDEO_CLOCK_DELAY                       0x00000400  //Bit[11:10] Video clock delay control
+        #define     VIDEO_CLOCK_DELAY_BIT               10
+        #define     VIDEO_CLOCK_DELAY_MASK              0x00000C00
+        #define     DELAY_0_NS                          0
+        #define     DELAY_1_NS                          1
+        #define     INV_AND_DELAY_0_NS                  2
+        #define     INV_AND_DELAY_1_NS                  3
+    #define     VIDEO_CCIR656_SOURCE_MODE               0x00001000  //Bit[12] Video CCIR656 source mode
+        #define     RGB_SOURCE_MODE                     0
+        #define     CCIR656_SOURCE_MODE                 1
+    #define     SOURCE_PORT_CLOCK_MODE                  0x00002000  //Bit[13] Video Source port clock mode
+        #define     SINGLE_EDGE_MODE                    0
+        #define     DUAL_EDGE_MODE                      1
+    #define     EXTERNAL_PORT_SELECTION                 0x00004000  //Bit[14] External video port slection
+        #define     VIDEO_PORT_A                        0
+        #define     VIDEO_PORT_B                        1
+    #define     VIDEO_CAPTURE_FRAME_RATE                0x00010000  //Bit[23:16] Video capture frame rate control
+        #define     VIDEO_CAPTURE_FRAME_RATE_BIT        16
+        #define     VIDEO_CAPTURE_FRAME_RATE_MASK       0x00FF0000  //Maximum frame rate = XX * SourceFPS / 60
+
+#define    VIDEO1_TIMEING_GEN_HOR_REG                   0x0C + VIDEOBASE_OFFSET
+#define    VIDEO2_TIMEING_GEN_HOR_REG                   0x10C + VIDEOBASE_OFFSET
+    #define     VIDEO_HDE_END                           0x00000000  //Bit[12:0] Video HDE End timing generator
+    #define     VIDEO_HDE_END_BIT                       0  //Number of pixels from rising edge of Hsync for first active pixel
+    #define     VIDEO_HDE_END_MASK                      0x00001FFF
+    #define     VIDEO_HDE_START                         0x00010000  //Bit[28:16] Video HDE Start timing generator
+    #define     VIDEO_HDE_START_BIT                     16 //Number of pixels from rising edge of Hsync for last active pixel
+    #define     VIDEO_HDE_START_MASK                    0x1FFF0000
+        #define     FRAME_RATE_OFF                      0    
+    
+#define    VIDEO1_TIMEING_GEN_V_REG                     0x10 + VIDEOBASE_OFFSET
+#define    VIDEO2_TIMEING_GEN_V_REG                     0x110 + VIDEOBASE_OFFSET
+    #define     VIDEO_VDE_END                           0x00000001  //Bit[11:0] Video VDE End timing generator
+    #define     VIDEO_VDE_END_BIT                       0  //Number of pixels from rising edge of Vsync for first active pixel
+    #define     VIDEO_VDE_END_MASK                      0x00000FFF
+    #define     VIDEO_VDE_START                         0x00010000  //Bit[27:16] Video VDE Start timing generator
+    #define     VIDEO_VDE_START_BIT                     16 //Number of pixels from rising edge of Vsync for last active pixel
+    #define     VIDEO_VDE_START_MASK                    0x0FFF0000
+
+#define    VIDEO1_SCALE_FACTOR_REG                      0x14 + VIDEOBASE_OFFSET
+#define    VIDEO2_SCALE_FACTOR_REG                      0x114 + VIDEOBASE_OFFSET
+    #define     HOR_SCALING_FACTOR                      0x00000001  //Bit[15:0] Video Horizontal scaling factor
+    #define     HOR_SCALING_FACTOR_BIT                  0   //The formula=4096/(Horizontal scaling facotr)
+    #define     HOR_SCALING_FACTOR_MASK                 0x0000FFFF
+    #define     VER_SCALING_FACTOR                      0x00000000  //Bit[31:16] Video Vertical scaling factor
+    #define     VER_SCALING_FACTOR_BIT                  16   //The formula=4096/(Vertical scaling facotr)
+    #define     VER_SCALING_FACTOR_MASK                 0xFFFF0000
+
+#define    VIDEO1_SCALE_FACTOR_PARAMETER0_REG           0x18 + VIDEOBASE_OFFSET  //Scaling Parameters F00, F01, F02, F03
+#define    VIDEO2_SCALE_FACTOR_PARAMETER0_REG           0x118 + VIDEOBASE_OFFSET   
+
+#define    VIDEO1_SCALE_FACTOR_PARAMETER1_REG           0x1C + VIDEOBASE_OFFSET  //Scaling Parameters F10, F11, F12, F13
+#define    VIDEO2_SCALE_FACTOR_PARAMETER1_REG           0x11C + VIDEOBASE_OFFSET   
+
+#define    VIDEO1_SCALE_FACTOR_PARAMETER2_REG           0x20 + VIDEOBASE_OFFSET  //Scaling Parameters F20, F21, F22, F23
+#define    VIDEO2_SCALE_FACTOR_PARAMETER2_REG           0x120 + VIDEOBASE_OFFSET   
+
+#define    VIDEO1_SCALE_FACTOR_PARAMETER3_REG           0x24 + VIDEOBASE_OFFSET  //Scaling Parameters F30, F31, F32, F33
+#define    VIDEO2_SCALE_FACTOR_PARAMETER3_REG           0x124 + VIDEOBASE_OFFSET
+
+#define    VIDEO1_BCD_CONTROL_REG                       0x2C + VIDEOBASE_OFFSET
+#define    VIDEO2_BCD_CONTROL_REG                       0x12C + VIDEOBASE_OFFSET
+    #define     BCD_ENABLE                              0x00000001  //Bit[0] Enable block change detection(BCD)
+        #define     BCD_ENABLE_BIT                      0
+        #define     BCD_ENABLE_MASK                     0x00000001
+    #define     BCD_TOLERANCE                           0x00010000  //Bit[23:16]
+        #define     BCD_TOLERANCE_BIT                   16 //flag as changed block when the video data difference greater
+        #define     BCD_TOLERANCE_MASK                  0x00FF0000
+
+#define     VIDEO1_CAPTURE_WINDOWS_REG                  0x30 + VIDEOBASE_OFFSET
+#define     VIDEO2_CAPTURE_WINDOWS_REG                  0x130 + VIDEOBASE_OFFSET
+    #define     CAPTURE_VER_LINE						0x00000001  //Bit[10:0] Video compression vertical line total
+    #define     CAPTURE_VER_LINE_BIT					0
+    #define     CAPTURE_VER_LINE_MASK					0x000007FF
+    #define     CAPTURE_HOR_PIXEL						0x00010000  //Bit[26:16] Video compression vertical line total
+    #define     CAPTURE_HOR_PIXEL_BIT					16
+    #define     CAPTURE_HOR_PIXEL_MASK					0x07FF0000
+
+#define     VIDEO1_COMPRESS_WINDOWS_REG                 0x34 + VIDEOBASE_OFFSET
+#define     VIDEO2_COMPRESS_WINDOWS_REG                 0x134 + VIDEOBASE_OFFSET
+    #define     COMPRESS_VER_LINE                       0x00000001  //Bit[10:0] Video compression vertical line total
+    #define     COMPRESS_VER_LINE_BIT                   0
+    #define     COMPRESS_VER_LINE_MASK                  0x000007FF
+    #define     COMPRESS_HOR_PIXEL                      0x00010000  //Bit[26:16] Video compression vertical line total
+    #define     COMPRESS_HOR_PIXEL_BIT                  16
+    #define     COMPRESS_HOR_PIXEL_MASK                 0x07FF0000
+
+#define     VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG      0x38
+#define     VIDEO2_COMPRESS_BUF_PROCESS_OFFSET_REG      0x138
+    #define     COMPRESS_BUF_PROCESS_OFFSET_ALIGN       127 //128 byte alignment
+    #define     COMPRESS_BUF_PROCESS_OFFSET_MASK        0xFFFFFF
+
+#define     VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG    0x38
+#define     VIDEO2_DECOMPRESS_BUF_PROCESS_OFFSET_REG    0x138
+    #define     DECOMPRESS_BUF_PROCESS_OFFSET_ALIGN     127 //128 byte alignment
+    #define     DECOMPRESS_BUF_PROCESS_OFFSET_MASK      0xFFFFFF
+
+
+//For Compression
+#define     VIDEO1_COMPRESS_BUF_READ_OFFSET_REG         0x3C + VIDEOBASE_OFFSET     //For stream mode
+#define     VIDEO2_COMPRESS_BUF_READ_OFFSET_REG         0x13C + VIDEOBASE_OFFSET
+    #define     COMPRESS_BUF_READ_OFFSET_ALIGN          127 //128 byte alignment
+    #define     COMPRESS_BUF_READ_OFFSET_MASK           0x00FFFFFF
+//For Decompression
+#define     VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG      0x3C + VIDEOBASE_OFFSET     //For stream mode 
+#define     VIDEO2_DECOMPRESS_BUF_WRITE_OFFSET_REG      0x13C + VIDEOBASE_OFFSET
+    #define     DECOMPRESS_BUF_WRITE_OFFSET_ALIGN       127 //128 byte alignment
+    #define     DECOMPRESS_BUF_WRITE_OFFSET_MASK        0x00FFFFFF
+
+#define     VIDEO1_CRC_BUF_ADDR_REG                     0x40 + VIDEOBASE_OFFSET
+#define     VIDEO2_CRC_BUF_ADDR_REG                     0x140 + VIDEOBASE_OFFSET
+    #define     CRC_BUF_ADDR_ALIGN                      7   //8 byte alignment
+    #define     CRC_BUF_ADDR_MASK                       0x0FFFFFFF
+
+#define     VIDEO1_BUF_1_ADDR_REG                       0x44 + VIDEOBASE_OFFSET     //For Source Buffer in frame mode
+#define     VIDEO2_BUF_1_ADDR_REG                       0x144 + VIDEOBASE_OFFSET
+    #define     BUF_1_ADDR_ALIGN                        255 //256 byte alignment
+    #define     BUF_1_ADDR_MASK                         0x1FFFFFFF
+
+#define     VIDEO1_BUF_LINE_OFFSET_REG                  0x48 + VIDEOBASE_OFFSET     //Must set both in Frame/Stream mode
+#define     VIDEO2_BUF_LINE_OFFSET_REG                  0x148 + VIDEOBASE_OFFSET
+    #define     BUF_LINE_OFFSET_ALIGN                   7 //8 byte alignment
+    #define     BUF_LINE_OFFSET_MASK                    0x00003FFF
+
+#define     VIDEO1_BUF_2_ADDR_REG                       0x4C + VIDEOBASE_OFFSET     //For BCD Buffer in frame mode
+#define     VIDEO2_BUF_2_ADDR_REG                       0x14C + VIDEOBASE_OFFSET     
+    #define     BUF_2_ADDR_ALIGN                        255 //256 byte alignment
+    #define     BUF_2_ADDR_MASK                         0x1FFFFFFF
+
+#define     VIDEO1_FLAG_BUF_ADDR_REG                    0x50 + VIDEOBASE_OFFSET     //For block change flag buffer
+#define     VIDEO2_FLAG_BUF_ADDR_REG                    0x150 + VIDEOBASE_OFFSET     
+    #define     FLAG_BUF_ADDR_ALIGN                     7 //8 byte alignment
+    #define     FLAG_BUF_ADDR_MASK                      0x1FFFFFFF
+
+#define     VIDEO1_COMPRESS_BUF_ADDR_REG                0x54 + VIDEOBASE_OFFSET     //For stream mode
+#define     VIDEO2_COMPRESS_BUF_ADDR_REG                0x154 + VIDEOBASE_OFFSET     
+    #define     COMPRESS_BUF_ADDR_ALIGN                 127 //128 byte alignment
+    #define     COMPRESS_BUF_ADDR_MASK                  0x1FFFFFFF
+
+#define     VIDEO1_STREAM_BUF_SIZE                      0x58 + VIDEOBASE_OFFSET     //For stream mode 
+#define     VIDEO2_STREAM_BUF_SIZE                      0x158 + VIDEOBASE_OFFSET
+    #define     STREAM_PACKET_SIZE                      0x00000001
+        #define     STREAM_PACKET_SIZE_BIT              0
+        #define     STREAM_PACKET_SIZE_MASK             0x00000007
+        #define     PACKET_SIZE_1KB                     0
+        #define     PACKET_SIZE_2KB                     1
+        #define     PACKET_SIZE_4KB                     2
+        #define     PACKET_SIZE_8KB                     3
+        #define     PACKET_SIZE_16KB                    4
+        #define     PACKET_SIZE_32KB                    5
+        #define     PACKET_SIZE_64KB                    6
+        #define     PACKET_SIZE_128KB                   7
+    #define     RING_BUF_PACKET_NUM                     0x00000008
+        #define     RING_BUF_PACKET_NUM_BIT             3
+        #define     RING_BUF_PACKET_NUM_MASK            0x00000018
+        #define     PACKETS_4                           0
+        #define     PACKETS_8                           1
+        #define     PACKETS_16                          2
+        #define     PACKETS_32                          3
+    #define     SKIP_HIGH_MB_THRES                      0x00010000  //Bit[22:16] Skip high quality macro block threshold
+        #define     SKIP_HIGH_MB_THRES_BIT              16
+        #define     SKIP_HIGH_MB_THRES_MASK             0x007F0000
+    #define     SKIP_TEST_MODE                          0x00800000  //Bit[24:23] Skip test mode
+        #define     SKIP_TEST_MODE_BIT                  23
+        #define     SKIP_TEST_MODE_MASK                 0x01800000
+        #define     YUV_TEST                            2   //recommend
+
+#define     VIDEO1_BUF_CODEC_OFFSET_READ                0x5C + VIDEOBASE_OFFSET     //For stream mode,         
+#define     VIDEO2_BUF_CODEC_OFFSET_READ                0x15C + VIDEOBASE_OFFSET    //Video stream buffer offset read back(HW)
+    #define     BUF_CODEC_OFFSET_ALIGN                  255 //256 byte alignment
+    #define     BUF_CODEC_OFFSET_MASK                   0x00FFFFFF
+
+#define     VIDEO1_COMPRESS_CONTROL_REG                 0x60 + VIDEOBASE_OFFSET
+#define     VIDEO2_COMPRESS_CONTROL_REG                 0x160 + VIDEOBASE_OFFSET
+    #define     JPEG_ONLY_ENCODE                        0x00000001  //Bit[0] JPEG only encoding
+        #define     JPEG_ONLY_BIT                       0
+        #define     JPEG_MIX_MODE                       0   //Enable JPEG/VQ mix mode encoding
+        #define     JPEG_ONLY_MODE                      1   //JPEG encoding mode only
+    #define     VQ_4_COLOR_ENCODE                       0x00000002  //Bit[1] Enable 4 color VQ encoding
+        #define     VQ_4_COLOR_BIT                      1
+        #define     VQ_1_2_COLOR_MODE                   0   //1 and 2 color mode VQ encoding
+        #define     VQ_4_COLOR_MODE                     1   //1, 2 and 4 color VQ encoding
+    #define     QUALITY_CODEC_SETTING                   0x00000004  //Bit[2] High and best video quality codec mode setting
+        #define     QUALITY_CODEC_SETTING_BIT           2
+        #define     JPEG_CODEC_MODE                     0   //not supported in best video quality mode
+        #define     QUANTI_CODEC_MODE                   1
+    #define     JPEG_DUAL_QUALITY_EN                    0x00000008  //Bit[3] JPEG dual quality mode
+        #define     EN_JPEG_DUAL_QUALITY                1   //enable(only for normal video quality mode)
+    #define     BEST_QUALITY_EN                         0x00000010  //Bit[4] Best quality video mode enable
+        #define     BEST_QUALITY_EN_BIT                 4
+        #define     EN_BEST_QUALITY                     1   //enable(only for quantization codec mode)
+    #define     RC4_CRYPT_EN                            0x00000020  //Bit[5] Enable RC4 encryption/decryption
+		#define		RC4_CRYPT_EN_BIT					5
+		#define     RC4_CRYPT_EN_MASK                   0x00000020
+        #define     RC4_CRYPT_ON                        1   //enable
+    #define     NORMAL_QUANTI_CHROMI_TABLE              0x00000040  //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
+        #define     NORMAL_QUANTI_CHROMI_TABLE_BIT      6
+        #define     NORMAL_QUANTI_CHROMI_TABLE_MASK     0x000007C0
+    #define     NORMAL_QUANTI_LUMI_TABLE                0x00000800  //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
+        #define     NORMAL_QUANTI_LUMI_TABLE_BIT        11
+        #define     NORMAL_QUANTI_LUMI_TABLE_MASK       0x0000F800
+    #define     HIGH_QUALITY_EN                         0x00010000  //Bit[16] High video quality mode enable
+        #define     HIGH_QUALITY_EN_BIT                 16
+        #define     EN_HIGH_QUALITY                     1   //Enable
+    #define     UV_CIR656_FORMAT                        0x00080000  //Bit[19] UV fromat
+        #define     UV_CIR656_FORMAT_BIT                19
+        #define     USE_UV_CIR656                       1   //recommand
+    #define     HUFFMAN_TABLE_SELECT                    0x00100000  //Bit[20] JPEG Huffman table combination
+        #define     DUAL_TABLE                          0   //Dual Y, UV table
+        #define     SINGLE_TABLE                        1   //Single Y table
+        #define     SINGLE_UV_TABLE                     0x00200000  //1x: Single UV table
+    #define     HIGH_QUANTI_CHROMI_TABLE                0x00400000  //Bit[26:22] High quality JPEG DCT chromi quantization table
+        #define     HIGH_QUANTI_CHROMI_TABLE_BIT        22
+        #define     HIGH_QUANTI_CHROMI_TABLE_MASK       0x07C00000                
+    #define     HIGH_DEQUANTI_VALUE                     0x00400000  //Bit[26:22] High quality de-quantization value
+        #define     HIGH_DEQUANTI_VALUE_BIT             22
+        #define     HIGH_DEQUANTI_VALUE_MASK            0x07C00000        
+    #define     HIGH_QUANTI_LUMI_TABLE                  0x08000000  //Bit[31:27] High quality JPEG DCT lumi quantization table
+        #define     HIGH_QUANTI_LUMI_TABLE_BIT          27
+        #define     HIGH_QUANTI_LUMI_TABLE_MASK         0xF8000000
+    #define     BEST_DEQUANTI_VALUE                     0x08000000  //Bit[31:27] Best quality de-quantization value
+        #define     BEST_DEQUANTI_VALUE_BIT             27
+        #define     BEST_DEQUANTI_VALUE_MASK            0xF8000000
+        
+
+#define     VIDEO1_QUANTI_TABLE_LOW_REG                 0x64 + VIDEOBASE_OFFSET     //Match with 0x60 Bit[10:6], Bit[15:11]
+#define     VIDEO2_QUANTI_TABLE_LOW_REG                 0x164 + VIDEOBASE_OFFSET
+    #define     QUANTI_CHROMI_TABLE_LOW                 0x00000001  //Bit[4:0] Normal video low quality block chromi quantization table
+        #define     QUANTI_CHROMI_TABLE_LOW_BIT         0
+        #define     QUANTI_CHROMI_TABLE_LOW_MASK        0x0000001F
+    #define     QUANTI_LUMI_TABLE_LOW                   0x00000020  //Bit[9:5] Normal video low quality block lumi quantization table
+        #define     QUANTI_LUMI_TABLE_LOW_BIT           5
+        #define     QUANTI_LUMI_TABLE_LOW_MASK          0x000003E0
+
+#define     VIDEO1_QUANTI_VALUE_REG                     0x68 + VIDEOBASE_OFFSET     //Match with 0x60 Bit[26:22],Bit[31:27]
+#define     VIDEO2_QUANTI_VALUE_REG                     0x168 + VIDEOBASE_OFFSET
+    #define     HIGH_QUANTI_VALUE                       0x00000001  //Bit[14:0] High quality quantization value. Format is 1.14
+        #define     HIGH_QUANTI_VALUE_BIT               0
+        #define     HIGH_QUANTI_VALUE_MASK              0x00007FFF
+    #define     BEST_QUANTI_VALUE                       0x00010000  //Bit[30:16] Best quality quantization value. Format is 1.14
+        #define     BEST_QUANTI_VALUE_BIT               16
+        #define     BEST_QUANTI_VALUE_MASK              0x7FFF0000
+    
+#define     VIDEO1_BSD_PARA_REG                         0x6C + VIDEOBASE_OFFSET    //Video BSD Parameters Register    
+#define     VIDEO2_BSD_PARA_REG                         0x16C + VIDEOBASE_OFFSET
+    #define     BSD_HIGH_THRES                          0x00000001  //Bit[7:0] Block sharpness detection high threshold
+    #define     BSD_HIGH_THRES_BIT                      0
+    #define     BSD_HIGH_THRES_MASK                     0x000000FF
+    #define     BSD_LOW_THRES                           0x00000100  //Bit[15:8] Block shaprpness detection low threshold
+    #define     BSD_LOW_THRES_BIT                       8
+    #define     BSD_LOW_THRES_MASK                      0x0000FF00
+    #define     BSD_HIGH_COUNTS                         0x00010000  //Bit[21:16] Block sharpness detection high counts threshold
+    #define     BSD_HIGH_COUNTS_BIT                     16
+    #define     BSD_HIGH_COUNTS_MASK                    0x003F0000
+    #define     BSD_LOW_COUNTS                          0x00400000  //Bit[27:22] Block sharpness detection low counts threshold
+    #define     BSD_LOW_COUNTS_BIT                      22
+    #define     BSD_LOW_COUNTS_MASK                     0x0FC00000
+
+#define VIDEO1_COMPRESS_FRAME_SIZE_REG                  0x70 + VIDEOBASE_OFFSET
+#define VIDEO2_COMPRESS_FRAME_SIZE_REG                  0x170 + VIDEOBASE_OFFSET
+    #define     COMPRESS_FRAME_SIZE_READ                0x00000001  //Bit[19:0] Video compression frame size read back(number of DW)
+    #define     COMPRESS_FRAME_SIZE_READ_BIT            0
+    #define     COMPRESS_FRAME_SIZE_READ_MASK           0x003FFFFF
+
+#define     VIDEO1_COMPRESS_BLOCK_COUNT_REG             0x74 + VIDEOBASE_OFFSET
+#define     VIDEO2_COMPRESS_BLOCK_COUNT_REG             0x174 + VIDEOBASE_OFFSET
+    #define     PROCESS_BLOCK_COUNT_READ_BIT            0
+    #define     PROCESS_BLOCK_COUNT_READ_MASK			0x00003FFF	//Bit[13:0] Video processed total block counter read back(number of blocks)
+    #define     COMPRESS_BLOCK_COUNT_READ_BIT           16
+    #define     COMPRESS_BLOCK_COUNT_READ_MASK          0xFFFF0000	//Bit[29:16] Video processed total block counter read back(number of blocks)
+
+#define     VIDEO1_COMPRESS_FRAME_END_READ              0x78 + VIDEOBASE_OFFSET     //Video compression stream frame end pointer    
+#define     VIDEO2_COMPRESS_FRAME_END_READ              0x178 + VIDEOBASE_OFFSET
+    #define     COMPRESS_FRAME_END_READ_ALIGN           7
+    #define     COMPRESS_FRAME_END_READ_MASK            0x00FFFFFF
+
+#define     VIDEO1_COMPRESS_FRAME_COUNT_READ            0x7C + VIDEOBASE_OFFSET     
+#define     VIDEO2_COMPRESS_FRAME_COUNT_READ            0x17C + VIDEOBASE_OFFSET 
+    #define     COMPRESS_FRAME_COUNT_READ               0x00000001  //Bit[15:0] Video compression frame count read back(number of frame)
+    #define     COMPRESS_FRAME_COUNT_READ_BIT           0
+    #define     COMPRESS_FRAME_COUNT_READ_MASK          0xFFFFFFFF
+
+#define     VIDEO1_USER_DEFINE_HEADER                   0x80 + VIDEOBASE_OFFSET
+#define     VIDEO2_USER_DEFINE_HEADER                   0x180 + VIDEOBASE_OFFSET
+    #define     USER_DEFINE_HEADER                      0x00000001  //Bit[15:0] Video user defined header parameter
+    #define     USER_DEFINE_HEADER_BIT                  0
+    #define     USER_DEFINE_HEADER_MASK                 0x0000FFFF
+    
+#define     VIDE1_MODE_DETECTION_EDGE_H_REG             0x90 + VIDEOBASE_OFFSET
+#define     VIDE2_MODE_DETECTION_EDGE_H_REG             0x190 + VIDEOBASE_OFFSET
+    #define     LEFT_EDGE_LOCATION                      0x00000001  //Bit[11:0] Video source left edge location from sync rising edge
+    #define     LEFT_EDGE_LOCATION_BIT                  0
+    #define     LEFT_EDGE_LOCATION_MASK                 0x00000FFF
+	#define		NO_VER_SYNC								(1 << 12)		//Bit[12] No Vertical sync detected
+	#define		NO_HOR_SYNC								(1 << 13)		//Bit[13] No horizontal sync detected
+	#define		NO_ACTIVE_DISP							(1 << 14)		//Bit[14] No active display detected
+	#define		NO_DISP_CLOCK							(1 << 15)		
+    #define     RIGHT_EDGE_LOCATION                     0x00010000  //Bit[27:16] Video source right edge location from sync rising edge
+    #define     RIGHT_EDGE_LOCATION_BIT                 16
+    #define     RIGHT_EDGE_LOCATION_MASK                0x0FFF0000
+
+#define     VIDE1_MODE_DETECTION_EDGE_V_REG             0x94 + VIDEOBASE_OFFSET
+#define     VIDE2_MODE_DETECTION_EDGE_V_REG             0x194 + VIDEOBASE_OFFSET
+    #define     TOP_EDGE_LOCATION                       0x00000001  //Bit[11:0] Video source top edge location from sync rising edge
+    #define     TOP_EDGE_LOCATION_BIT                   0
+    #define     TOP_EDGE_LOCATION_MASK                  0x00000FFF
+    #define     BOTTOM_EDGE_LOCATION                    0x00010000  //Bit[27:16] Video source bottom edge location from sync rising edge
+    #define     BOTTOM_EDGE_LOCATION_BIT                16
+    #define     BOTTOM_EDGE_LOCATION_MASK               0x0FFF0000
+
+#define VIDEO1_MODE_DETECTION_STATUS_READ_REG           0x98 + VIDEOBASE_OFFSET
+#define VIDEO2_MODE_DETECTION_STATUS_READ_REG           0x198 + VIDEOBASE_OFFSET    
+    #define     MODE_DETECTION_HOR_TIME_READ            0x00000001  //Bit[11:0] Mode detection Horizontal time read back (read only)
+    #define     MODE_DETECTION_HOR_TIME_READ_BIT        0
+    #define     MODE_DETECTION_HOR_TIME_READ_MASK       0x00000FFF
+    #define     ANALONG_DIGITAL_READ                    0x00001000  //Bit[12] Auto detection for external analog or digital source read back
+        #define     ANALONG_DIGITAL_READ_BIT            12
+        #define     DVI_SIGNAL                          0
+        #define     ADC_SIGNAL                          1
+    #define     MODE_DETECTION_HOR_STABLE_READ          0x00002000  //Bit[13] Mode detection horizontal stable read back
+        #define     HOR_STABLE                          1
+    #define     MODE_DETECTION_VER_STABLE_READ          0x00004000  //Bit[14] Mode detection vertical stable read back
+        #define     VER_STABLE                          1
+    #define     OUT_LOCK_READ                           0x00008000  //Bit[15] Mode detection out of lock read back
+        #define     SIGNAL_OUT_LOCK                     1
+    #define     MODE_DETECTION_VER_LINE_READ            0x00010000  //Bit[27:16] Mode detection Vertical lines read back
+    #define     MODE_DETECTION_VER_LINE_READ_BIT        16
+    #define     MODE_DETECTION_VER_LINE_READ_MASK       0x0FFF0000
+    #define     VSYNC_POLARITY_READ                     0x10000000  //Bit[28] Vsync polarity read back
+    #define     HSYNC_POLARITY_READ                     0x20000000  //Bit[29] Hsync polarity read back
+    #define     MODE_DETECTION_VSYNC_READY              0x40000000  //Bit[30] Mode detection Vsync ready
+    #define     MODE_DETECTION_HSYNC_READY              0x80000000  //Bit[31] Mode detection Hsync ready
+
+/******     VIDEO MEMAGER SETTING               ******/
+#define     VIDEOM_ENGINE_SEQUENCE_CONTROL_REG          0x204 + VIDEOBASE_OFFSET
+    #define     VIDEOM_CAPTURE_TRIGGER                  0x00000002  //Bit[1] trigger HW to capture video
+    #define     VIDEOM_AUTO_MODE						0x00000008  //Bit[3]
+        #define     DISABLE_AUTO_MODE                   0
+        #define     AUTO_COMPRESS						1
+    #define     VIDEOM_CODEC_TRIGGER                    0x00000010  //Bit[4] trigger HW to compress or decompress video
+    #define     VIDEOM_SOURCE_SELECTION                 0x00000100  //Bit[8]
+        #define     VIDEO1                              0
+        #define     VIDEO2                              1
+    //#define     STREAM_DATA_MODE                        0x00000400  //Bit[11:10] Buffer and Stream Data type
+    //    #define     STREAM_DATA_MODE_BIT                10
+    //    #define     STREAM_DATA_MODE_MASK               0x00000C00
+    //    #define     YUV444_MODE                         0
+    //    #define     YUV420_MODE                         1
+    //    #define     YUV420_MODE_WITH_AST2000            2 //AST2000 compatible
+    #define     VIDEOM_CAPTURE_READY                    0x00010000  //Bit[16] Video capture ready status read back(read only)
+        //#define     HW_BUSY                             0
+        //#define     HW_IDLE                             1
+    #define     VIDEOM_CODEC_READY                      0x00040000  //Bit[18] Video codec ready status read back(read only)
+        //#define     HW_BUSY                             0
+        //#define     HW_IDLE                             1
+
+#define    VIDEOM_SCALE_FACTOR_REG                      0x214 + VIDEOBASE_OFFSET
+//    #define     HOR_SCALING_FACTOR                      0x00000001  //Bit[15:0] Video Horizontal scaling factor
+//    #define     HOR_SCALING_FACTOR_BIT                  0   //The formula=4096/(Horizontal scaling facotr)
+//    #define     HOR_SCALING_FACTOR_MASK                 0x0000FFFF
+//    #define     VER_SCALING_FACTOR                      0x00000000  //Bit[31:16] Video Vertical scaling factor
+//    #define     VER_SCALING_FACTOR_BIT                  16   //The formula=4096/(Vertical scaling facotr)
+//    #define     VER_SCALING_FACTOR_MASK                 0xFFFF0000
+
+#define    VIDEOM_SCALE_FACTOR_PARAMETER0_REG           0x218 + VIDEOBASE_OFFSET  //Scaling Parameters F00, F01, F02, F03
+
+#define    VIDEOM_SCALE_FACTOR_PARAMETER1_REG           0x21C + VIDEOBASE_OFFSET  //Scaling Parameters F10, F11, F12, F13
+
+#define    VIDEOM_SCALE_FACTOR_PARAMETER2_REG           0x220 + VIDEOBASE_OFFSET  //Scaling Parameters F20, F21, F22, F23
+
+#define    VIDEOM_SCALE_FACTOR_PARAMETER3_REG           0x224 + VIDEOBASE_OFFSET  //Scaling Parameters F30, F31, F32, F33
+
+#define    VIDEOM_BCD_CONTROL_REG                       0x22C + VIDEOBASE_OFFSET
+    //#define     BCD_ENABLE                              0x00000001  //Bit[0] Enable block change detection(BCD)
+    //#define     BCD_TOLERANCE                           0x00010000  //Bit[23:16]
+    //    #define     BCD_TOLERANCE_BIT                   16 //flag as changed block when the video data difference greater
+    //    #define     BCD_TOLERANCE_MASK                  0x00FF0000
+
+#define     VIDEOM_CAPTURE_WINDOWS_REG                  0x230 + VIDEOBASE_OFFSET
+    //#define     RC4_TABLE_ADDR_ALIGN                    7   //8 byte alignment
+    //#define     RC4_TABLE_ADDR_MASK                     0x0FFFFFFF
+
+#define     VIDEOM_COMPRESS_WINDOWS_REG                 0x234 + VIDEOBASE_OFFSET
+    //#define     COMPRESS_VER_LINE                       0x00000001  //Bit[12:0] Video compression vertical line total
+    //#define     COMPRESS_VER_LINE_BIT                   0
+    //#define     COMPRESS_VER_LINE_MASK                  0x00001FFF
+    //#define     COMPRESS_HOR_PIXEL                      0x00010000  //Bit[12:0] Video compression vertical line total
+    //#define     COMPRESS_HOR_PIXEL_BIT                  16
+    //#define     COMPRESS_HOR_PIXEL_MASK                 0x1FFF0000
+
+#define     VIDEOM_COMPRESS_BUF_PROCESS_OFFSET_REG      0x238
+    //#define     COMPRESS_BUF_PROCESS_OFFSET_ALIGN       127 //128 byte alignment
+    //#define     COMPRESS_BUF_PROCESS_OFFSET_MASK        0x3FFFFF
+
+
+//For Compression
+#define     VIDEOM_COMPRESS_BUF_READ_OFFSET_REG         0x23C + VIDEOBASE_OFFSET     //For stream mode
+    //#define     COMPRESS_BUF_READ_OFFSET_ALIGN          127 //128 byte alignment
+    //#define     COMPRESS_BUF_READ_OFFSET_MASK           0x003FFFFF
+//For Decompression
+#define     VIDEOM_DECOMPRESS_BUF_WRITE_OFFSET_REG      0x23C + VIDEOBASE_OFFSET     //For stream mode 
+    //#define     DECOMPRESS_BUF_WRITE_OFFSET_ALIGN       127 //128 byte alignment
+    //#define     DECOMPRESS_BUF_WRITE_OFFSET_MASK        0x003FFFFF
+    
+#define     VIDEOM_BUF_1_ADDR_REG                       0x244 + VIDEOBASE_OFFSET     //For Source Buffer in frame mode
+    //#define     BUF_1_ADDR_ALIGN                        255 //256 byte alignment
+    //#define     BUF_1_ADDR_MASK                         0x0FFFFFFF
+
+#define     VIDEOM_BUF_LINE_OFFSET_REG                  0x248 + VIDEOBASE_OFFSET     //Must set both in Frame/Stream mode
+    //#define     BUF_LINE_OFFSET_ALIGN                   7 //8 byte alignment
+    //#define     BUF_LINE_OFFSET_MASK                    0x00003FFF
+
+#define     VIDEOM_BUF_2_ADDR_REG                       0x24C + VIDEOBASE_OFFSET     //For BCD Buffer in frame mode
+    //#define     BUF_2_ADDR_ALIGN                        255 //256 byte alignment
+    //#define     BUF_2_ADDR_MASK                         0x0FFFFFFF
+
+#define     VIDEOM_FLAG_BUF_ADDR_REG                    0x250 + VIDEOBASE_OFFSET     //For block change flag buffer
+    //#define     FLAG_BUF_ADDR_ALIGN                     7 //8 byte alignment
+    //#define     FLAG_BUF_ADDR_MASK                      0x0FFFFFFF
+
+#define     VIDEOM_COMPRESS_BUF_ADDR_REG                0x254 + VIDEOBASE_OFFSET     //For stream mode
+    //#define     FLAG_BUF_ADDR_ALIGN                     7 //8 byte alignment
+    //#define     FLAG_BUF_ADDR_MASK                      0x0FFFFFFF
+    
+#define     VIDEOM_BUF_CODEC_OFFSET_READ                0x25C + VIDEOBASE_OFFSET     //For stream mode,         
+    //#define     BUF_CODEC_OFFSET_ALIGN                  255 //256 byte alignment
+    //#define     BUF_CODEC_OFFSET_MASK                   0x003FFFFF
+    
+#define     VIDEOM_COMPRESS_CONTROL_REG                 0x260 + VIDEOBASE_OFFSET
+    //#define     JPEG_ONLY_ENCODE                        0x00000001  //Bit[0] JPEG only encoding
+    //    #define     JPEG_MIX_MODE                       0   //Enable JPEG/VQ mix mode encoding
+    //    #define     JPEG_ONLY_MODE                      1   //JPEG encoding mode only
+    //#define     VQ_4_COLOR_ENCODE                       0x00000002  //Bit[1] Enable 4 color VQ encoding
+    //    #define     VQ_1_2_COLOR_MODE                   0   //1 and 2 color mode VQ encoding
+    //    #define     VQ_4_COLOR_MODE                     1   //1, 2 and 4 color VQ encoding
+    //#define     QUALITY_CODEC_SETTING                   0x00000004  //Bit[2] High and best video quality codec mode setting
+    //    #define     JPEG_CODEC_MODE                     0   //not supported in best video quality mode
+    //    #define     QUANTI_CODEC_MODE                   1
+    //#define     JPEG_DUAL_QUALITY_EN                    0x00000008  //Bit[3] JPEG dual quality mode
+    //    #define     EN_JPEG_DUAL_QUALITY                1   //enable(only for normal video quality mode)
+    //#define     BEST_QUALITY_EN                         0x00000010  //Bit[4] Best quality video mode enable
+    //    #define     EN_BEST_QUALITY                     1   //enable(only for quantization codec mode)
+    //#define     RC4_CRYPT_EN                            0x00000020  //Bit[5] Enable RC4 encryption/decryption
+    //    #define     EN_RC4_CRYPT                        1   //enable
+    //#define     NORMAL_QUANTI_CHROMI_TABLE              0x00000040  //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
+    //    #define     NORMAL_QUANTI_CHROMI_TABLE_BIT      6
+    //    #define     NORMAL_QUANTI_CHROMI_TABLE_MASK     0x000007C0
+    //#define     NORMAL_QUANTI_LUMI_TABLE                0x00000800  //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
+    //    #define     NORMAL_QUANTI_LUMI_TABLE_BIT        11
+    //    #define     NORMAL_QUANTI_LUMI_TABLE_MASK       0x0000F800
+    //#define     HIGH_QUALITY_EN                         0x00010000  //Bit[16] High video quality mode enable
+    //    #define     EN_HIGH_QUALITY                     1   //Enable
+    //#define     UV_CIR656_FORMAT                        0x00080000  //Bit[19] UV fromat
+    //    #define     USE_UV_CIR656                       1   //recommand
+    //#define     HUFFMAN_TABLE_SELECT                    0x00100000  //Bit[20] JPEG Huffman table combination
+    //    #define     DUAL_TABLE                          0   //Dual Y, UV table
+    //    #define     SINGLE_TABLE                        1   //Single Y table
+    //    #define     SINGLE_UV_TABLE                     0x00200000  //1x: Single UV table
+    //#define     HIGH_QUANTI_CHROMI_TABLE                0x00400000  //Bit[26:22] High quality JPEG DCT chromi quantization table
+    //    #define     HIGH_QUANTI_CHROMI_TABLE_BIT        22
+    //    #define     HIGH_QUANTI_CHROMI_TABLE_MASK       0x07C00000                
+    //#define     HIGH_DEQUANTI_VALUE                     0x00400000  //Bit[26:22] High quality de-quantization value
+    //    #define     HIGH_DEQUANTI_VALUE_BIT             22
+    //    #define     HIGH_DEQUANTI_VALUE_MASK            0x07C00000        
+    //#define     HIGH_QUANTI_LUMI_TABLE                  0x08000000  //Bit[31:27] High quality JPEG DCT lumi quantization table
+    //    #define     HIGH_QUANTI_LUMI_TABLE_BIT          27
+    //    #define     HIGH_QUANTI_LUMI_TABLE_MASK         0xF8000000
+    //#define     BEST_DEQUANTI_VALUE                     0x08000000  //Bit[31:27] Best quality de-quantization value
+    //    #define     BEST_QUANTI_VALUE_BIT               27
+    //    #define     BEST_QUANTI_VALUE_MASK              0xF8000000
+    
+#define     VIDEOM_QUANTI_TABLE_LOW_REG                 0x264 + VIDEOBASE_OFFSET     //Match with 0x60 Bit[10:6], Bit[15:11]
+//    #define     QUANTI_CHROMI_TABLE_LOW                 0x00000001  //Bit[4:0] Normal video low quality block chromi quantization table
+//        #define     QUANTI_CHROMI_TABLE_LOW_BIT         0
+//        #define     QUANTI_CHROMI_TABLE_LOW_MASK        0x0000001F
+//    #define     QUANTI_LUMI_TABLE_LOW                   0x00000020  //Bit[9:5] Normal video low quality block lumi quantization table
+//        #define     QUANTI_CHROMI_TABLE_LOW_BIT         5
+//        #define     QUANTI_CHROMI_TABLE_LOW_MASK        0x000003E0
+
+#define     VIDEOM_QUANTI_VALUE_REG                     0x268 + VIDEOBASE_OFFSET     //Match with 0x60 Bit[26:22],Bit[31:27]
+//    #define     HIGH_QUANTI_VALUE                       0x00000001  //Bit[14:0] High quality quantization value. Format is 1.14
+//        #define     HIGH_QUANTI_VALUE_BIT               0
+//        #define     HIGH_QUANTI_VALUE_MASK              0x00007FFF
+//    #define     BEST_QUANTI_VALUE                       0x00010000  //Bit[30:16] Best quality quantization value. Format is 1.14
+//        #define     BEST_QUANTI_VALUE_BIT               16
+//        #define     BEST_QUANTI_VALUE_MASK              0x7FFF0000
+    
+#define     VIDEOM_BSD_PARA_REG                         0x26C + VIDEOBASE_OFFSET    //Video BSD Parameters Register    
+//    #define     BSD_HIGH_THRES                          0x00000001  //Bit[7:0] Block sharpness detection high threshold
+//    #define     BSD_HIGH_THRES_BIT                      0
+//    #define     BSD_HIGH_THRES_MASK                     0x000000FF
+//    #define     BSD_LOW_THRES                           0x00000100  //Bit[15:8] Block shaprpness detection low threshold
+//    #define     BSD_LOW_THRES_BIT                       8
+//    #define     BSD_LOW_THRES_MASK                      0x0000FF00
+//    #define     BSD_HIGH_COUNTS                         0x00010000  //Bit[21:16] Block sharpness detection high counts threshold
+//    #define     BSD_HIGH_COUNTS_BIT                     16
+//    #define     BSD_HIGH_COUNTS_MASK                    0x003F0000
+//    #define     BSD_LOW_COUNTS                          0x01000000  //Bit[27:24] Block sharpness detection low counts threshold
+//    #define     BSD_LOW_COUNTS_BIT                      24
+//    #define     BSD_LOW_COUNTS_MASK                     0x3F000000
+
+#define VIDEOM_COMPRESS_FRAME_SIZE_REG					  0x270 + VIDEOBASE_OFFSET
+//    #define     COMPRESS_FRAME_SIZE_READ                0x00000001  //Bit[19:0] Video compression frame size read back(number of DW)
+//    #define     COMPRESS_FRAME_SIZE_READ_BIT            0
+//    #define     COMPRESS_FRAME_SIZE_READ_MASK           0x000FFFFF
+
+#define     VIDEOM_COMPRESS_BLOCK_COUNT_REG				  0x274 + VIDEOBASE_OFFSET
+//    #define     COMPRESS_BLOCK_COUNT_READ               0x00000001  //Bit[15:0] Video compress block counter read back(number of blocks)
+//    #define     COMPRESS_BLOCK_COUNT_READ_BIT           0
+//    #define     COMPRESS_BLOCK_COUNT_READ_MASK          0x0000FFFF
+
+#define     VIDEOM_COMPRESS_FRAME_END_READ              0x278 + VIDEOBASE_OFFSET     //Video compression stream frame end pointer    
+    //#define     COMPRESS_FRAME_END_READ_ALIGN           7
+    //#define     COMPRESS_FRAME_END_READ_MASK            0x003FFFFF
+    
+#define     VIDEOM_USER_DEFINE_HEADER_REG			      0x280 + VIDEOBASE_OFFSET
+//    #define     USER_DEFINE_HEADER                      0x00000001  //Bit[15:0] Video user defined header parameter
+//    #define     USER_DEFINE_HEADER_BIT                  0
+//    #define     USER_DEFINE_HEADER_MASK                 0x0000FFFF
+
+/******  VR300-VR3FC: General Control registers  *****/
+#define     VIDEO_CONTROL_REG                           0x300 + VIDEOBASE_OFFSET
+    #define     CODEC_DECOMPRESS_MODE                   0x00000001  //Bit[0] Codec in de-compression mode
+        #define     CODEC_DECOMPRESS_MODE_BIT           0
+        #define     CODEC_DECOMPRESS_MODE_MASK          0x00000001 
+        #define     COMPRESS_MODE                       0
+        #define     DECOMPRESS_MODE                     1
+    #define     VIDEO_SAFE_MODE							0x00000002  //Bit[1] VIDEO SAFE MODE
+		#define     VIDEO_SAFE_MODE_BIT					1
+		#define     VIDEO_SAFE_MODE_OFF		            0
+        #define     VIDEO_SAFE_MODE_ON		            1
+    #define     DELAY_VSYNC								0x00000004  //Bit[2] Delay Internal VSYNC
+        #define     DELAY_VSYNC_BIT                     2
+        #define     DELAY_VSYNC_MASK                    (1<<2)
+		#define		DELAY_VSYNC_OFF						(0<<2)
+		#define		DELAY_VSYNC_EN						(1<<2)
+    #define     VER_DOWNSCALING_LINE_BUFFER_EN          0x00000010  //Bit[5:4] Video vertical downscaling line buffer enable
+		#define		VER_LINE_BUFFER_MASK				(3<<4)
+        #define     LINE_BUFFER_OFF                     (0<<4)
+        #define     LINE_BUFFER_VIDEO1                  1
+        #define     LINE_BUFFER_VIDEO2                  2
+        #define     LINE_BUFFER_VIDEOM                  3
+    #define     RC4_KEY_BUFFER_SELECTION				(1UL<<6)  //Bit[7:6] RC4 Key Buffer Selection
+		#define		RC4_KEY_BUFFER_SELECTION_BIT		6
+		#define		RC4_KEY_BUFFER_SELECTION_MASK		(3UL<<6)
+        #define     RC4_KEY_BUFFER_VIDEO1               0
+        #define     RC4_KEY_BUFFER_VIDEO2               1
+        #define     RC4_KEY_BUFFER_VIDEOM               2
+    #define     RC4_INIT_RESET							(1UL<<8)  //Bit[8] RC4 initial reset
+		#define     RC4_INIT_RESET_BIT					8
+		#define     RC4_INIT_RESET_MASK					(1UL<<8)
+		#define     RC4_NORMAL_MODE						0
+		#define     RC4_RESET_COUNTER					1
+    #define     RC4_TEST_MODE							(1UL<<9)  //Bit[9] RC4 test mode
+		#define     RC4_TEST_MODE_BIT					9
+		#define     RC4_TEST_OFF						0
+		#define     RC4_TEST_ON							1
+    #define     RC4_SAVE_MODE							(1UL<<14)  //Bit[14] RC4 save mode
+		#define     RC4_SAVE_MODE_BIT					14
+		#define     RC4_SAVE_MODE_MASK					(1UL<<14)
+		#define     RC4_SAVE_MODE_OFF					0
+		#define     RC4_SAVE_MODE_ON					1
+    #define     RC4_NO_RESET_FRAME						(1UL<<15)  //Bit[15] RC4 no reset when frame completed
+		#define     RC4_NO_RESET_FRAME_BIT				15
+		#define     RC4_NO_RESET_FRAME_MASK				(1UL<<15)
+		#define     RC4_NO_RESET_FRAME_OFF				0		//Always reset
+		#define     RC4_NO_RESET_FRAME_ON				1
+
+#define VIDEO_INT_CONTROL_EN_REG                        0x304 + VIDEOBASE_OFFSET
+    #define     VIDEO1_WATCH_DOG_INT_EN                 0x00000001  //Bit[0] Enable Video1 mode detection watch dog out of lock interrupt
+    #define     VIDEO1_INPUT_COMPLETE_INT_EN            0x00000002  //Bit[1] Enable Video1 video input complete interrupt  (frame complete only for frame mode)
+    #define     VIDEO1_PACKET_READY_INT_EN              0x00000004  //Bit[2] Enable Video1 packet ready interrupt
+    #define     VIDEO1_COMPRESS_COMPLETE_INT_EN         0x00000008  //Bit[3] Enable Video1 compression complete interrupt
+    #define     VIDEO1_MODE_DETECTION_READY_INT_EN      0x00000010  //Bit[4] Enable video1 mode detection ready interrupt
+    #define     VIDEO1_FRAME_COMPLETE_INT_EN            0x00000020  //Bit[5] Enable Video1 frame complete interrupt     (only for stream mode)
+    #define     VIDEO1_STREAM_ERR_INT_EN                0x00000040  //Bit[6] Enable Video1 decode stream error interrupt
+    #define     VIDEO2_WATCH_DOG_INT_EN                 0x00000100  //Bit[8] Enable Video2 mode detection watch dog out of lock interrupt
+    #define     VIDEO2_INPUT_COMPLETE_INT_EN            0x00000200  //Bit[9] Enable Video2 video input complete interrupt  (frame complete only for frame mode)
+    #define     VIDEO2_PACKET_READY_INT_EN              0x00000400  //Bit[10] Enable Video2 packet ready interrupt
+    #define     VIDEO2_COMPRESS_COMPLETE_INT_EN         0x00000800  //Bit[11] Enable Video2 compression complete interrupt
+    #define     VIDEO2_MODE_DETECTION_READY_INT_EN      0x00001000  //Bit[12] Enable video2 mode detection ready interrupt
+    #define     VIDEO2_FRAME_COMPLETE_INT_EN            0x00002000  //Bit[13] Enable Video2 frame complete interrupt    (only for stream mode)
+    #define     VIDEO2_STREAM_ERR_INT_EN                0x00004000  //Bit[14] Enable Video2 decode stream error interrupt
+    #define     VIDEOM_INPUT_COMPLETE_INT_EN            0x00010000  //Bit[16] Enable VideoM video input complete interrupt
+    #define     VIDEOM_COMPRESS_COMPLETE_INT_EN         0x00020000  //Bit[17] Enable VideoM compression complete interrupt
+	#define     VIDEOM_PACKET_READY_INT_EN				0x00040000  //Bit[18] Enable VideoM packet ready interrupt
+	#define     VIDEOM_FRAME_COMPLETE_INT_EN            0x00080000  //Bit[19] Enable VideoM frame complete interrupt    (only for stream mode)
+    
+#define VIDEO_INT_CONTROL_READ_REG                      0x308 + VIDEOBASE_OFFSET //Clear when write 1
+    #define     VIDEO1_WATCH_DOG_READ                   0x00000001  //Bit[0] Video1 mode detection watch dog out of lock interrupt status read back
+        #define     VIDEO1_WATCH_DOG_BIT				0
+        #define     VIDEO1_WATCH_DOG_MASK				0x00000001
+    #define     VIDEO1_INPUT_COMPLETE_READ              0x00000002  //Bit[1] Video1 video input complete interrupt status read back (frame complete only for frame mode)
+        #define     VIDEO1_INPUT_COMPLETE_BIT			1
+        #define     VIDEO1_INPUT_COMPLETE_MASK			0x00000002
+    #define     VIDEO1_PACKET_READY_READ                0x00000004  //Bit[2] Video1 packet ready interrupt status read back
+        #define     VIDEO1_PACKET_READY_BIT		        2
+        #define     VIDEO1_PACKET_READY_MASK		    0x00000004
+    #define     VIDEO1_COMPRESS_COMPLETE_READ           0x00000008  //Bit[3] Video1 compression complete interrupt status read back
+        #define     VIDEO1_COMPRESS_COMPLETE_BIT		3
+        #define     VIDEO1_COMPRESS_COMPLETE_MASK		0x00000008
+    #define     VIDEO1_MODE_DETECTION_READY_READ        0x00000010  //Bit[4] Video1 mode detection ready interrupt status read back
+        #define     VIDEO1_MODE_DETECTION_READY_BIT     4
+    #define     VIDEO1_FRAME_COMPLETE_READ              0x00000020  //Bit[5] Video1 frame complete interrupt status read back
+        #define     VIDEO1_FRAME_COMPLETE_BIT			5
+        #define     VIDEO1_FRAME_COMPLETE_MASK			0x00000020
+    #define     VIDEO1_STREAM_ERR_READ                  0x00000040  //Bit[6] Video1 decode stream error interrupt status read back
+        #define     VIDEO1_STREAM_ERR_BIT				6
+        #define     VIDEO1_STREAM_ERR_MASK				0x00000040
+    #define     VIDEO2_WATCH_DOG_READ                   0x00000100  //Bit[8] Video2 mode detection watch dog out of lock interrupt status read back
+        #define     VIDEO2_WATCH_DOG_BIT				8
+        #define     VIDEO2_WATCH_DOG_MASK				0x00000100
+    #define     VIDEO2_INPUT_COMPLETE_READ              0x00000200  //Bit[9] Video2 video input complete interrupt status read back (frame complete only for frame mode)
+        #define     VIDEO2_INPUT_COMPLETE_BIT			9
+        #define     VIDEO2_INPUT_COMPLETE_MASK			0x00000200
+    #define     VIDEO2_PACKET_READY_READ                0x00000400  //Bit[10] Video2 packet ready interrupt status read back
+        #define     VIDEO2_PACKET_READY_BIT		        10
+        #define     VIDEO2_PACKET_READY_MASK		    0x00000400
+    #define     VIDEO2_COMPRESS_COMPLETE_READ           0x00000800  //Bit[11] Video2 compression complete interrupt status read back 
+        #define     VIDEO2_COMPRESS_COMPLETE_BIT		11
+        #define     VIDEO2_COMPRESS_COMPLETE_MASK		0x00000800      
+		#define     VIDEO2_MODE_DETECTION_READY_READ    0x00001000  //Bit[12] Video2 mode detection ready interrupt status read back
+        #define     VIDEO2_MODE_DETECTION_READY_BIT     12              
+    #define     VIDEO2_FRAME_COMPLETE_READ              0x00002000  //Bit[13] Video2 frame complete interrupt status read back
+        #define     VIDEO2_FRAME_COMPLETE_BIT		    13
+        #define     VIDEO2_FRAME_COMPLETE_MASK			0x00002000
+    #define     VIDEO2_STREAM_ERR_READ                  0x00004000  //Bit[14] Video2 decode stream error interrupt status read back
+        #define     VIDEO2_STREAM_ERR_BIT				14
+        #define     VIDEO2_STREAM_ERR_MASK				0x00004000
+    //need check spec
+    #define     VIDEOM_INPUT_COMPLETE_READ              0x00010000  //Bit[16] VideoM video input complete interrupt status read back
+        #define     VIDEOM_INPUT_COMPLETE_BIT			16
+        #define     VIDEOM_INPUT_COMPLETE_MASK			0x00010000
+    #define     VIDEOM_COMPRESS_COMPLETE_READ           0x00020000  //Bit[17] VideoM compression complete interrupt status read back
+        #define     VIDEOM_COMPRESS_COMPLETE_BIT		17
+        #define     VIDEOM_COMPRESS_COMPLETE_MASK		0x00020000
+    #define     VIDEOM_PACKET_READY_READ                0x00040000  //Bit[18] Clear Packet ready interrupt when write 1
+        #define     VIDEOM_PACKET_READY_BIT             18
+        #define     VIDEOM_PACKET_READY_MASK            0x00040000    
+    #define     VIDEOM_FRAME_COMPLETE_READ              0x00080000  //Bit[19] Clear Frame complete interrupt when write 1
+        #define     VIDEOM_FRAME_COMPLETE_BIT           19
+        #define     VIDEOM_FRAME_COMPLETE_MASK          0x00080000
+   
+#define VIDEO_INT_CONTROL_CLEAR_REG                     0x308 + VIDEOBASE_OFFSET //Clear when write 1
+    //Clear when write 1
+    #define     VIDEO1_WATCH_DOG_CLEAR                  0x00000001  //Bit[0] Clear mode detection watch dog out of lock interrupt when write 1
+    #define     VIDEO1_INPUT_COMPLETE_CLEAR             0x00000002  //Bit[1] Clear video input complete interrupt when write 1 (frame complete only for frame mode)
+    #define     VIDEO1_PACKET_READY_CLEAR               0x00000004  //Bit[2] Clear Packet ready interrupt when write 1
+        #define     VIDEO1_PACKET_READY_CLEAR_BIT       2
+        #define     VIDEO1_PACKET_READY_CLEAR_MASK      0x00000004
+    #define     VIDEO1_COMPRESS_COMPLETE_CLEAR          0x00000008  //Bit[3] Clear video compression interrupt when write 1
+    #define     VIDEO1_MODE_DETECTION_READY_CLEAR       0x00000010  //Bit[4] Clear Video1 Mode detection ready interrupt when write 1
+    #define     VIDEO1_FRAME_COMPLETE_CLEAR             0x00000020  //Bit[5] Clear Frame complete interrupt when write 1
+        #define     VIDEO1_FRAME_COMPLETE_CLEAR_BIT     5
+        #define     VIDEO1_FRAME_COMPLETE_CLEAR_MASK    0x00000020
+    #define     VIDEO1_STREAM_ERR_CLEAR                 0x00000040  //Bit[6] Clear decode stream error interrupt when write 1
+    #define     VIDEO2_WATCH_DOG_CLEAR                  0x00000100  //Bit[8] Clear Mode detection interrupt when write 1
+    #define     VIDEO2_INPUT_COMPLETE_CLEAR             0x00000200  //Bit[9] Clear video input complete interrupt when write 1
+    #define     VIDEO2_PACKET_READY_CLEAR               0x00000400  //Bit[10] Clear packet ready interrupt when write 1
+    #define     VIDEO2_COMPRESS_COMPLETE_CLEAR          0x00000800  //Bit[11] Clear video compression complete interrupt when write 1
+    #define     VIDEO2_MODE_DETECTION_READY_CLEAR       0x00001000  //Bit[12] Clear Video2 Mode detection ready interrupt when write 1
+    #define     VIDEO2_FRAME_COMPLETE_CLEAR             0x00002000  //Bit[13] Clear Frame complete interrupt when write 1 (frame complete only for frame mode)
+    #define     VIDEO2_STREAM_ERR_CLEAR                 0x00004000  //Bit[14] Clear Decode stream error interrupt when write 1
+    //need check spec
+    #define     VIDEOM_INPUT_COMPLETE_CLEAR             0x00010000  //Bit[16] Clear video input complete interrupt when write 1
+    #define     VIDEOM_COMPRESS_COMPLETE_CLEAR          0x00020000  //Bit[17] Clear compression complete interrupt when write 1
+        #define     VIDEOM_COMPRESS_COMPLETE_CLEAR_BIT  17
+        #define     VIDEOM_COMPRESS_COMPLETE_CLEAR_MASK 0x00020000    
+	#define     VIDEOM_PACKET_READY_CLEAR				0x00040000  //Bit[18] Clear compression complete interrupt when write 1
+        #define     VIDEOM_PACKET_READY_CLEAR_BIT       18
+        #define     VIDEOM_PACKET_READY_CLEAR_MASK      0x00040000    
+    #define     VIDEOM_FRAME_COMPLETE_CLEAR             0x00100000  //Bit[20] Clear Frame complete interrupt when write 1
+        #define     VIDEOM_FRAME_COMPLETE_CLEAR_BIT     20
+        #define     VIDEOM_FRAME_COMPLETE_CLEAR_MASK    0x00100000
+    #define     VIDEOM_STREAM_ERR_CLEAR                 0x00200000  //Bit[21] Clear decode stream error interrupt when write 1
+    
+#define VIDEO_MODE_DETECTION_PARAM_REG                  0x30C + VIDEOBASE_OFFSET
+    #define     EDGE_PIXEL_THRES_BIT                    8           //Bit[15:8] Mode detection edge pixel threshold
+    #define     EDGE_PIXEL_THRES_MASK                   0x0000FF00  
+    #define     VER_STABLE_MAX_BIT                      16          //Bit[19:16] Mode detection vertical stable maximum
+    #define     VER_STABLE_MAX_BIT_MASK                 0x000F0000  
+    #define     HOR_STABLE_MAX_BIT                      20          //Bit[23:20] Mode detection horizontal stable maximum
+    #define     HOR_STABLE_MAX_BIT_MASK                 0x00F00000
+    #define     VER_STABLE_THRES_BIT                    24          //Bit[27:24] Mode detection vertical stable threshold
+    #define     VER_STABLE_THRES_BIT_MASK               0x0F000000  
+    #define     HOR_STABLE_THRES_BIT                    28          //Bit[31:28] Mode detection horizontal stable threshold
+    #define     HOR_STABLE_THRES_BIT_MASK               0xF0000000
+    
+#define VIDEO_CRC_PRIMARY_REG                           0x320 + VIDEOBASE_OFFSET
+    #define     CRC_CHECK_EN                            0x00000001  //Bit[0] Video port 1/2 Enable video capture write CRC check
+        #define     CRC_CHECK_EN_BIT                    0
+    #define     CRC_CHECK_HIGH                          0x00000002  //Bit[1] Video port 1/2 CRC check high bit only
+        #define     CRC_CHECK_HIGH_BIT                  1
+    #define     SKIP_COUNT_MAX                          0x00000004  //Bit[7:2] Video port 1/2 Max capture write skip count
+        #define     SKIP_COUNT_MAX_BIT                  2
+        #define     SKIP_COUNT_MAX_MASK                 0x000000FC
+    #define     CRC_PRIMARY_POLY_LOW                    0x00000100  //Bit[15:8] Primary CRC low 8-bit polynomial
+        #define     CRC_RIMARY_POLY_LOW_BIT             8
+        #define     CRC_RIMARY_POLY_LOW_MASK            0x0000FF00
+    #define     CRC_PRIMARY_POLY_HIGH                   0x00010000  //Bit[31:16] Primary CRC high 8-bit polynomial
+        #define     CRC_RIMARY_POLY_HIGH_BIT            16
+        #define     CRC_RIMARY_POLY_HIGH_MASK           0xFFFF0000
+        
+
+#define VIDEO_CRC_SECOND_REG                            0x324 + VIDEOBASE_OFFSET
+    #define     CRC_SECOND_POLY_LOW                     0x00000100  //Bit[15:8] Secondary CRC low 8-bit polynomial
+        #define     CRC_SECOND_POLY_LOW_BIT             8
+        #define     CRC_SECOND_POLY_LOW_MASK            0x0000FF00
+    #define     CRC_SECOND_POLY_HIGH                    0x00010000  //Bit[31:16] Secondary CRC high 8-bit polynomial
+        #define     CRC_SECOND_POLY_HIGH_BIT            16
+        #define     CRC_SECOND_POLY_HIGH_MASK           0xFFFF0000
+
+#define VIDEO1_RC4_KEYS_REG                              0x400 + VIDEOBASE_OFFSET //Total Video1 RC4 Keys     
+#define VIDEO2_RC4_KEYS_REG                              0x500 + VIDEOBASE_OFFSET //Total Video2 RC4 Keys     
+#define VIDEOM_RC4_KEYS_REG                              0x600 + VIDEOBASE_OFFSET //Total VideoM RC4 Keys     
+
+#endif /* end of _VREG_H_ */
+
author	Timothy Pearson <tpearson@raptorengineering.com>	2017-08-23 15:54:21 -0500
committer	Timothy Pearson <tpearson@raptorengineering.com>	2017-08-23 15:54:21 -0500
commit	0223e595f4033e91e93403a7317bcc9e47676b8f (patch)
tree	2ccd7127bc343f82456b76eeb0da2d380f6eaf65 /board/aspeed/ast2050
download	ast2050-uboot-0223e595f4033e91e93403a7317bcc9e47676b8f.zip ast2050-uboot-0223e595f4033e91e93403a7317bcc9e47676b8f.tar.gz