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* Add support for Intel 5 Series / 3400 Series chipsetsHelge Wagner2010-08-111-1/+3
| | | | | | | | | | | (At least) for the QM57 which i have tested an additional patch was needed as some reserved bits in the "Software Sequencing Flash Control Register" (SSFC) needs to be programmed to 1 in the QM57. Corresponding to flashrom svn r1137. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Split off programmer.h from flash.hCarl-Daniel Hailfinger2010-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Corresponding to flashrom svn r1112. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Move Intel SPI initialisation to ichspi.cMichael Karcher2010-07-221-3/+210
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Corresponding to flashrom svn r1098. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Use generic unlocking infrastructure for SPI chipsCarl-Daniel Hailfinger2010-07-141-1/+0
| | | | | | | | | Actually check if the unlock worked instead of just assuming it worked. Corresponding to flashrom svn r1082. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Convert SPI chips to partial writeCarl-Daniel Hailfinger2010-07-141-23/+2
| | | | | | | | | | However, wrap the write functions in a compat layer to allow converting the rest of flashrom later. Tested on Intel NM10 by David Hendricks. Corresponding to flashrom svn r1080. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Kill global variables, constants and functions if local scope sufficesCarl-Daniel Hailfinger2010-07-031-12/+14
| | | | | | | | | | | | | | | | | | | | | | | Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Corresponding to flashrom svn r1068. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* ichspi: try harder to conform to address restrictionsCarl-Daniel Hailfinger2010-05-281-1/+49
| | | | | | | | | | | | | | ICH SPI can enforce address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Corresponding to flashrom svn r1016. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Handle the following architectures in generic flashrom codeCarl-Daniel Hailfinger2010-05-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Corresponding to flashrom svn r1013. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
* Introduce a generic SPI read function: spi_write_chunked()Carl-Daniel Hailfinger2010-05-211-36/+10
| | | | | | | | | | | | | | | Every SPI programmer driver had its own completely different chip write implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Corresponding to flashrom svn r1005. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: David Hendricks <dhendrix@google.com>
* Convert various prints to use msg_p* and msg_g* respectivelySean Nelson2010-05-071-44/+35
| | | | | | | | | Convert programmer print messages to msg_p* convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel. Corresponding to flashrom svn r997. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Polish the flashrom code comments and outputs a bitUwe Hermann2010-03-251-1/+1
| | | | | | | | | | | - Fix a number of typos (found via ispell). - Use correct vendor names (as per their websites) consistently. Corresponding to flashrom svn r985. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Split spi.c into programmer and chip code Remove chipdriver.h include from ↵Sean Nelson2010-02-261-0/+1
| | | | | | | | | | | | | | | | | | | flash.h Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c Corresponding to flashrom svn r914. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Rewrite substantial parts of the ICH SPI supportCarl-Daniel Hailfinger2010-02-111-53/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This megapatch rewrites substantial parts of ICH SPI to actually do what the SPI layer wants instead of its own weird idea about commands (running unrequested commands, running modified commands). Besides that, there is a fair share of cleanups as well. - Add JEDEC_EWSR (Enable Write Status Register) to default commands. - Mark a no longer used opcode/preopcode table as unused. - Declare all commands as non-atomic/standalone by default. The ICH SPI driver has no business executing commands (preopcodes) automatically if they were not requested. - Automatically adjust preopcode/opcode pairings (like WREN+ERASE) based on what the SPI layer requested. The ICH SPI driver has no business executing altered opcode pairs as it sees fit. - Fix incomplete initialization in the case of a locked down chipset. Leaving the first 4 opcodes with uninitialized pairings had unpredictable results. - switch() exists for a reason. Nested if() checking on the same variable is an interesting style. - Actually check if the requested readcnt/writecnt for a command is supported by the hardware instead of delivering corrupt/incomplete commands and data. - If a command has unsupported readlen/writelen, complain loudly to the user. - Use find_opcode instead of open-coding the same stuff in a dozen variations. - Introduce infrastructure for updating the command set of unlocked chipsets on the fly. Corresponding to flashrom svn r894. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com>
* Allow one to disable programmer debug messages at compile timeCarl-Daniel Hailfinger2010-01-071-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Programmer debug messages during programmer init/shutdown are useful because they print hardware settings and desired configuration. They help in getting a quick overview of hardware and software state on startup and shutdown. Programmer debug messages during flash chip access are mostly a distraction in logs and should only be enabled if someone is having problems which are suspected to stem from a programmer hardware or programmer software bug. Disable those messages by default, they can be reenabled by #define COMM_DEBUG in the affected programmer file. An added benefit is a tremendous size reduction in verbose probe/read/write/erase logs because only flash chip driver messages remain. In some cases, logs will shrink from 65 MB to 10 kB or less. The right(tm) fix would be two different debug levels (DEBUG and SPEW) and the ability to differentiate between programmer debug messages and flash chip debug messages. Until the design for the message printing infrastructure is finished, this is the best stop-gap measure we can get. Corresponding to flashrom svn r834. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audioahcked@gmail.com>
* Kill hardcoded block erase on ICH SPICarl-Daniel Hailfinger2009-11-251-11/+7
| | | | | | | | | | | | The existing code does not work for all SPI chips, and it just was a band-aid to cope with locked down chipsets back in a time when there was no eraseblock infrastructure. Basically, this unbreaks a few SPI chips on ICH. Corresponding to flashrom svn r777. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Maciej Pijanka <maciej.pijanka@gmail.com>
* ichspi: remove obnoxious debug messageCarl-Daniel Hailfinger2009-10-221-4/+1
| | | | | | | | | | | | | | | | | Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Corresponding to flashrom svn r753. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be>
* The current ICH SPI preop handling is a hack which spews lots of warnings, ↵Carl-Daniel Hailfinger2009-09-181-14/+21
| | | | | | | | | | | | | | | | | | but still yields correct results With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Corresponding to flashrom svn r727. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
* Standardize on using __func__ instead of __FUNCTION__Uwe Hermann2009-09-021-4/+4
| | | | | | | | | | | | | | | The __func__ variant is standardized in C99 and recommended to be used instead of __FUNCTION__ in the gcc info page. Only _very_ old versions of gcc did not know about __func__, but we've been using both __func__ and __FUNCTION__ for a long while now, and nobody complained about this, so all our users seem to use recent enough compilers. Corresponding to flashrom svn r711. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Remove unnecessary #include filesCarl-Daniel Hailfinger2009-08-091-1/+0
| | | | | | | | | | Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Corresponding to flashrom svn r671. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Replace most of the switch cases in the spi code with lookup on a struct insteadCarl-Daniel Hailfinger2009-07-221-0/+20
| | | | | | | | | | | | | | | This brings the SPI code in line with the generic programmer infrastructure. This patch is a reworked version of a patch by Jakob Bornecrantz. Corresponding to flashrom svn r657. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Use a distinct return code for SPI commands with unsupported/invalid lengthCarl-Daniel Hailfinger2009-07-141-3/+10
| | | | | | | | | | | Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Corresponding to flashrom svn r653. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add SPI multicommand infrastructureCarl-Daniel Hailfinger2009-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> Corresponding to flashrom svn r645. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
* Check result of all SPI erase functionsCarl-Daniel Hailfinger2009-06-241-1/+1
| | | | | | | | | | | | | | Since block erase functions do not know the block length (it's not specified in any standard), block erase functions now get an additional parameter blocklen. This enables flashrom to verify the erase result for block erase functions at correct boundaries. Tested by Uwe on SB600. Corresponding to flashrom svn r630. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Use spi_nbyte_program in ichspi.cCarl-Daniel Hailfinger2009-06-171-20/+7
| | | | | | | | | This shortens the code a lot and makes it more readable. Corresponding to flashrom svn r600. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Support reads of arbitrary rangeCarl-Daniel Hailfinger2009-06-161-2/+2
| | | | | | | | | | | | That means you can tell flashrom to read exactly bytes 12345-56789 (start 12345, length 44445) and it will not fetch a single byte more. Uwe tested this on one LPC, one SPI, and one parallel flash board. Corresponding to flashrom svn r596. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Every SPI host controller implemented its own way to read flash chipsCarl-Daniel Hailfinger2009-06-131-45/+2
| | | | | | | | | | | | | | | | | | | | | | This was partly due to a design problem in the abstraction layer. There should be exactly two different functions for reading SPI chips: - memory mapped reads - SPI command reads. Each of them should be contained in a separate function, optionally taking parameters where needed. This patch solves the problems mentioned above, shortens the code and makes the code logic a lot more obvious. Since open-coding the min() function leads to errors, include it in this patch as well. Corresponding to flashrom svn r589. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Add programmer-specific delay functionsCarl-Daniel Hailfinger2009-06-051-2/+2
| | | | | | | | | | | Add external programmer delay functions so external programmers can handle the delay on their own if needed. Corresponding to flashrom svn r578. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Urja Rannikko <urjaman@gmail.com>
* Add bus type annotation to struct flashchipsCarl-Daniel Hailfinger2009-05-311-14/+14
| | | | | | | | | | | | | | | | | | | Right now, the annotation only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Corresponding to flashrom svn r556. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Use REMS instead of RES in the ICH SPI default opcode tableCarl-Daniel Hailfinger2009-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RES is Read Electronic Signature (1 Byte, identical for different chips) REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique) RDID is Read JEDEC ID (3 bytes, unique) Of the chips which don't support RDID, a sizable portion supports REMS which gives us both a manufacturer ID and a device ID. This is clearly superior to having only a device ID (the RES case) which has multiple documented collisions. The RES/REMS problem is aggravated by inconsistent naming in vendor data sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte IDs and 3+byte IDs with varying names but mostly consistent opcodes, it makes sense to set our own standard about how the opcodes are called. The best way forward would be to have the ICH SPI driver reprogram the opcode menu on the fly if the opcode menu doesn't contain the requested opcode and the opcode menu is not locked. Until that happens, this patch improves detection accuracy by a factor of 256 for some chips. Corresponding to flashrom svn r549. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Uwe Hermann with the flash chip "SST SST25VF040.REMS". Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Use accessor functions for MMIOCarl-Daniel Hailfinger2009-05-171-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some MMIO accesses used volatile, others didn't (and risked non-execution of side effects) and even with volatile, some accesses looked dubious. Since the MMIO accessor functions and the onboard flash accessor functions are functionally identical (but have different signatures), make the flash accessors wrappers for the MMIO accessors. For some of the conversions, I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b ) Corresponding to flashrom svn r524. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Uwe tested read, write, erase with this patch on a random board to make sure nothing breaks. Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Eliminate all 'inline's from the flashrom codeUwe Hermann2009-05-161-6/+6
| | | | | | | | | | | | They serve pretty much no purpose, compilers can optimize pretty much all of what we might mark as inline anyway, _and_ inlines are not enforced in any way by the compiler either. They're totally unneeded. Kill them. Corresponding to flashrom svn r522. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Drop unused/duplicated #includes and some dead codeUwe Hermann2009-05-161-3/+0
| | | | | | | | | Build-tested on 32bit x86. Corresponding to flashrom svn r521. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* There are various reasons why a SPI command can failCarl-Daniel Hailfinger2009-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | Among others, I have seen the following problems: - The SPI opcode is not supported by the controller. ICH-style controllers exhibit this if SPI config is locked down. - The address in in a prohibited area. This can happen on ICH for any access (BBAR) and for writes in chipset write protected areas. - There is no SPI controller. Introduce separate error codes for unsupported opcode and prohibited address. Add the ability to adjust REMS and RES addresses to the minium supported read address with the help of spi_get_valid_read_addr(). That function needs to call SPI controller specific functions like reading BBAR on ICH. Corresponding to flashrom svn r500. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Trim default ICH SPI delay from 1000 to 10 microsecondsCarl-Daniel Hailfinger2009-05-091-4/+4
| | | | | | | | | | | | | | | | Since many commands take around 10 microseconds to complete, it is totally pointless to wait for 1000 microseconds before checking the status again. This patch is tested and reduced write time on ICH7 with SST25VF080B from over one hour to 62 seconds. Thanks to Ali Nadalizadeh for testing! Corresponding to flashrom svn r487. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com>
* Chips like the SST SST25VF080B can only handle single byte writes outside ↵Carl-Daniel Hailfinger2009-05-091-1/+1
| | | | | | | | | | | | | | | | | | AAI mode Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Corresponding to flashrom svn r485. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Some coding style and consistency fixesUwe Hermann2009-04-151-7/+5
| | | | | | | Corresponding to flashrom svn r429 and coreboot v2 svn r4117. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Fix one dead increment and one dead assignment as found by clangPeter Stuge2009-01-261-1/+0
| | | | | | | | | Thanks Patrick! Corresponding to flashrom svn r410 and coreboot v2 svn r3918. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Add ICH opcode debuggingPeter Stuge2009-01-151-0/+1
| | | | | | | Corresponding to flashrom svn r383 and coreboot v2 svn r3862. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Various ichspi.c refinementsFENG yu ning2008-12-151-27/+30
| | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-081-0/+134
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* ichspi: use spi_nbyte_read() instead of running the opcode directlyCarl-Daniel Hailfinger2008-11-181-9/+5
| | | | | | | | | | | | | | Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Corresponding to flashrom svn r346 and coreboot v2 svn r3758. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add additional SPI sector erase and chip erase command functionsCarl-Daniel Hailfinger2008-11-031-16/+5
| | | | | | | | | | | | | | | | | | | Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Corresponding to flashrom svn r337 and coreboot v2 svn r3722. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer2008-11-021-15/+45
| | | | | | | | | | | | opcode instead This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Corresponding to flashrom svn r336 and coreboot v2 svn r3721. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-181-12/+12
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Trivial indent fix in ichspi.cPeter Stuge2008-07-071-3/+3
| | | | | | | Corresponding to flashrom svn r301 and coreboot v2 svn r3417. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* First attempt to clean up SPI probing and create a common construct: the ↵Stefan Reinauer2008-06-301-53/+54
| | | | | | | | | | | | | | | | | | flash bus At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* This patch adds support for VIA SPI controller on VT8237SRudolf Marek2008-06-301-26/+44
| | | | | | | | | It is similar with few documented exceptions to ICH7 SPI controller. Corresponding to flashrom svn r282 and coreboot v2 svn r3398. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se>
* Add a debug marker after ICH SPI opcode programmingCarl-Daniel Hailfinger2008-06-291-1/+2
| | | | | | | Corresponding to flashrom svn r281 and coreboot v2 svn r3397. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix ICH7 non-SPI that broke in r3393Peter Stuge2008-06-291-1/+1
| | | | | | | | | | | | r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Corresponding to flashrom svn r280 and coreboot v2 svn r3395. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Multiple unrelated changesStefan Reinauer2008-06-271-41/+211
| | | | | | | | | | | | * ICH7 SPI support * fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Corresponding to flashrom svn r278 and coreboot v2 svn r3393. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se>
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