Add support for Intel 5 Series / 3400 Series chipsets

(At least) for the QM57 which i have tested an additional patch was
needed as some reserved bits in the "Software Sequencing Flash Control
Register" (SSFC) needs to be programmed to 1 in the QM57.

Corresponding to flashrom svn r1137.

Signed-off-by: Helge Wagner <helge.wagner@ge.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>

1 files changed, 3 insertions, 1 deletions

diff --git a/ichspi.c b/ichspi.c
index 126ed00..bb6007e 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -560,7 +560,9 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
 	}
 
 	/* Assemble SSFS + SSFC */
-	temp32 = 0;
+	/* keep reserved bits (23-19,7,0) */
+	temp32 = REGREAD32(ICH9_REG_SSFS);
+	temp32 &= 0xF8008100;
 
 	/* clear error status registers */
 	temp32 |= (SSFS_CDS + SSFS_FCERR);