Fix VIA VX*** support

Helge Wagner's patch that added VIA VX900 chipset support made me look
closer at the datasheets which led to some concise documentation about
newer VIA chipsets: http://flashrom.org/VIA

Based on that this patch adds full support for VX800/VX820, VX855/VX875
and VX900, including SPI and LPC. VT8237S was not changed (SPI support
only) because there is no public datasheet and it is not clear how to
distinguish between LPC and SPI strapping and investigations in (NDAed)
documents have not brought up anything conclusively.

enable_flash_vt823x could probably be enhanced too due to various
ignored LPC options of the chipset.

Corresponding to flashrom svn r1578.

Signed-off-by: Helge Wagner <Helge.Wagner@ge.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

1 files changed, 3 insertions, 5 deletions

diff --git a/ichspi.c b/ichspi.c
index 0223ae3..20eb549 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1844,14 +1844,12 @@ static const struct spi_programmer spi_programmer_via = {
 	.write_aai = default_spi_write_aai,
 };
 
-int via_init_spi(struct pci_dev *dev)
+int via_init_spi(struct pci_dev *dev, uint32_t mmio_base)
 {
-	uint32_t mmio_base;
 	int i;
 
-	mmio_base = (pci_read_long(dev, 0xbc)) << 8;
-	msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
-	ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
+	ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70);
+	/* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
 
 	/* Not sure if it speaks all these bus protocols. */
 	internal_buses_supported = BUS_LPC | BUS_FWH;