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/*
* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2006 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5211_beacon.c,v 1.4 2008/11/10 04:08:02 sam Exp $
*/
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR5211
#include "ah.h"
#include "ah_internal.h"
#include "ar5211/ar5211.h"
#include "ar5211/ar5211reg.h"
#include "ar5211/ar5211desc.h"
/*
* Routines used to initialize and generated beacons for the AR5211/AR5311.
*/
/*
* Initialize all of the hardware registers used to send beacons.
*/
void
ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
{
OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
/*
* Set the Beacon register after setting all timers.
*/
OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
}
/*
* Legacy api to initialize all of the beacon registers.
*/
void
ar5211BeaconInit(struct ath_hal *ah,
uint32_t next_beacon, uint32_t beacon_period)
{
HAL_BEACON_TIMERS bt;
bt.bt_nexttbtt = next_beacon;
/*
* TIMER1: in AP/adhoc mode this controls the DMA beacon
* alert timer; otherwise it controls the next wakeup time.
* TIMER2: in AP mode, it controls the SBA beacon alert
* interrupt; otherwise it sets the start of the next CFP.
*/
switch (AH_PRIVATE(ah)->ah_opmode) {
case HAL_M_STA:
case HAL_M_MONITOR:
bt.bt_nextdba = 0xffff;
bt.bt_nextswba = 0x7ffff;
break;
case HAL_M_IBSS:
case HAL_M_HOSTAP:
bt.bt_nextdba = (next_beacon -
ath_hal_dma_beacon_response_time) << 3; /* 1/8 TU */
bt.bt_nextswba = (next_beacon -
ath_hal_sw_beacon_response_time) << 3; /* 1/8 TU */
break;
}
/*
* Set the ATIM window
* Our hardware does not support an ATIM window of 0
* (beacons will not work). If the ATIM windows is 0,
* force it to 1.
*/
bt.bt_nextatim = next_beacon + 1;
bt.bt_intval = beacon_period &
(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
ar5211SetBeaconTimers(ah, &bt);
}
void
ar5211ResetStaBeaconTimers(struct ath_hal *ah)
{
uint32_t val;
OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
val = OS_REG_READ(ah, AR_STA_ID1);
val |= AR_STA_ID1_PWR_SAV; /* XXX */
/* tell the h/w that the associated AP is not PCF capable */
OS_REG_WRITE(ah, AR_STA_ID1,
val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
}
/*
* Set all the beacon related bits on the h/w for stations
* i.e. initializes the corresponding h/w timers;
* also tells the h/w whether to anticipate PCF beacons
*/
void
ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
{
struct ath_hal_5211 *ahp = AH5211(ah);
HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
HALASSERT(bs->bs_intval != 0);
/* if the AP will do PCF */
if (bs->bs_cfpmaxduration != 0) {
/* tell the h/w that the associated AP is PCF capable */
OS_REG_WRITE(ah, AR_STA_ID1,
OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
/* set CFP_PERIOD(1.024ms) register */
OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
/* set CFP_DUR(1.024ms) register to max cfp duration */
OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
/* set TIMER2(128us) to anticipated time of next CFP */
OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
} else {
/* tell the h/w that the associated AP is not PCF capable */
OS_REG_WRITE(ah, AR_STA_ID1,
OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
}
/*
* Set TIMER0(1.024ms) to the anticipated time of the next beacon.
*/
OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
/*
* Start the beacon timers by setting the BEACON register
* to the beacon interval; also write the tim offset which
* we should know by now. The code, in ar5211WriteAssocid,
* also sets the tim offset once the AID is known which can
* be left as such for now.
*/
OS_REG_WRITE(ah, AR_BEACON,
(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
| SM(bs->bs_intval, AR_BEACON_PERIOD)
| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
);
/*
* Configure the BMISS interrupt. Note that we
* assume the caller blocks interrupts while enabling
* the threshold.
*/
HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
/*
* Set the sleep duration in 1/8 TU's.
*/
#define SLEEP_SLOP 3
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
(bs->bs_sleepduration - SLEEP_SLOP) << 3);
#undef SLEEP_SLOP
}
#endif /* AH_SUPPORT_AR5211 */
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