| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert "Revert "MFC r328083,328096,328116,328119,328120,328128,328135,328153,... | Luiz Souza | 2018-02-23 | 1 | -2/+6 |
| * | Revert "Revert "MFC r327964:"" | Luiz Souza | 2018-02-23 | 1 | -0/+21 |
| * | Revert "Revert "MFC r323822 (by cem):"" | Luiz Souza | 2018-02-23 | 1 | -0/+7 |
| * | Revert "Revert "MFC r327469:"" | Luiz Souza | 2018-02-23 | 1 | -0/+1 |
| * | Revert "Revert "MFC r327118:"" | Luiz Souza | 2018-02-23 | 1 | -0/+1 |
| * | Revert "MFC r327118:" | Luiz Souza | 2018-02-21 | 1 | -1/+0 |
| * | Revert "MFC r327469:" | Luiz Souza | 2018-02-21 | 1 | -1/+0 |
| * | Revert "MFC r323822 (by cem):" | Luiz Souza | 2018-02-21 | 1 | -7/+0 |
| * | Revert "MFC r327964:" | Luiz Souza | 2018-02-21 | 1 | -21/+0 |
| * | Revert "MFC r328083,328096,328116,328119,328120,328128,328135,328153,328157," | Luiz Souza | 2018-02-21 | 1 | -6/+2 |
| * | MFC r328083,328096,328116,328119,328120,328128,328135,328153,328157, | kib | 2018-02-19 | 1 | -2/+6 |
| * | MFC r327964: | kib | 2018-02-19 | 1 | -0/+21 |
| * | MFC r323822 (by cem): | kib | 2018-02-19 | 1 | -0/+7 |
| * | MFC r327469: | kib | 2018-02-19 | 1 | -0/+1 |
| * | MFC r327118: | kib | 2018-02-19 | 1 | -0/+1 |
| * | MFC r314636,r314700: MCA: add AMD Error Thresholding support | avg | 2017-04-14 | 1 | -0/+16 |
| * | MFC r315361 and r315364: Hide MONITORX/MWAITX from guests. | grehan | 2017-03-25 | 1 | -0/+1 |
| * | Add x86 CPU features definitions published in the Intel SDM rev. 58. | kib | 2016-04-16 | 1 | -0/+14 |
| * | re-enable AMD Topology extension on certain models if disabled by BIOS | avg | 2016-04-12 | 1 | -0/+1 |
| * | Add defines for the LAPIC TSC deadline timer mode. The LVT timer mode | kib | 2016-03-28 | 1 | -1/+3 |
| * | Add standard extended feature bit 6 from the Intel SDM rev. 57, which | kib | 2015-12-29 | 1 | -0/+1 |
| * | x86: Add CPUID_STDEXT_* macros for CPU feature bits | cem | 2015-12-21 | 1 | -0/+5 |
| * | Add bit names for the IA32_MISC_ENABLE msr. | kib | 2015-07-28 | 1 | -0/+11 |
| * | Rewrite amd64 PCID implementation to follow an algorithm described in | kib | 2015-05-09 | 1 | -0/+1 |
| * | Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE. | neel | 2015-05-06 | 1 | -1/+4 |
| * | Add x2APIC support. Enable it by default if CPU is capable. The | kib | 2015-02-09 | 1 | -0/+1 |
| * | Update Features2 to display SDBG capability of processor. This is | sbruno | 2015-01-08 | 1 | -0/+1 |
| * | Merge from projects/bhyve_svm all the changes outside vmm.ko or bhyve utilities: | neel | 2014-10-20 | 1 | -0/+14 |
| * | Support Intel-specific MSRs that are accessed when booting up a linux in bhyve: | neel | 2014-10-09 | 1 | -0/+4 |
| * | Restructure the MSR handling so it is entirely handled by processor-specific | neel | 2014-09-20 | 1 | -0/+4 |
| * | Add a define for index of IA32_XSS MSR, which is, per SDM rev. 50, an | kib | 2014-09-06 | 1 | -0/+2 |
| * | Add more bits for the XSAVE features from CPUID 0xd, sub-function 1 | kib | 2014-09-06 | 1 | -0/+3 |
| * | - Output a summary of optional VT-x features in dmesg similar to CPU | jhb | 2014-07-30 | 1 | -0/+19 |
| * | Whitespace fix. | jhb | 2014-05-22 | 1 | -3/+3 |
| * | Add definitions for more structured extended features as well as | jhb | 2014-05-16 | 1 | -6/+25 |
| * | Rename the AMD MSR_PERFCTR[0-3] so the Pentium Pro MSR_PERFCTR[0-1] | tijl | 2014-01-31 | 1 | -6/+4 |
| * | Add bits for the AMD features from CPUID function 0x80000001 ECX, | kib | 2013-11-08 | 1 | -0/+6 |
| * | x86: detect mwait capabilities and extensions, when present | avg | 2013-07-28 | 1 | -0/+23 |
| * | Move the previously added CPUID7 macros to CPUID_STDEXT. | rpaulo | 2013-04-18 | 1 | -17/+11 |
| * | Add the most current CPUID7_* definitions. | rpaulo | 2013-04-18 | 1 | -0/+17 |
| * | Make the code to check if VMX is enabled more readable by using macros | neel | 2013-04-11 | 1 | -0/+5 |
| * | Add macros required to enable VMX operation on Intel processors. | neel | 2013-01-05 | 1 | -0/+2 |
| * | Provide the reading and display of the Standard Extended Features, | kib | 2012-11-01 | 1 | -0/+11 |
| * | Add support for the XSAVEOPT instruction use. Our XSAVE/XRSTOR usage | kib | 2012-07-14 | 1 | -0/+5 |
| * | Add x2apic MSR definitions | grehan | 2012-04-17 | 1 | -1/+35 |
| * | Recognize the RDRAND instruction feature. | jhb | 2012-04-09 | 1 | -0/+1 |
| * | Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replace | tijl | 2012-03-19 | 1 | -0/+678 |
