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* Rework the list of all pmaps: embed the list link into pmap.br2016-04-262-24/+12
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* o Add device tree files and kernel configuration filesbr2016-04-266-2/+83
| | | | | for RISC-V cpus synthesized on FPGA hardware. o Include new files to the build.
* Add the non-standard "IO interrupt" vector used by lowRISC.br2016-04-264-3/+29
| | | | | | | For now they provide UART irq only. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of basic bus_space_read/write functions.br2016-04-262-12/+183
| | | | | Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of OF_decode_addr().br2016-04-261-0/+58
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* Move arm's devmap to some generic place, so it can be usedbr2016-04-262-61/+2
| | | | | | | | | by other architectures. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D6091 Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* o Implement shared pagetables and switch from 4 to 3 levels pagebr2016-04-258-76/+140
| | | | | | | | | | | | | | | | | | | | | | | | memory system. RISC-V ISA has only single page table base register for both kernel and user addresses translation. Before this commit we were using an extra (4th) level of pagetables for switching between kernel and user pagetables, but then realized FPGA hardware has 3-level page system hardcoded. It is also become clear that the bitfile synthesized for 4-level system is untested/broken, so we can't use extra level for switching. We are now share level 1 of pagetables between kernel and user VA. This requires to keep track of all the user pmaps created and once we adding L1 page to kernel pmap we have to add it to all the user pmaps. o Change the VM layout as we must have topmost bit to be 1 in the selected page system for kernel addresses and 0 for user addresses. o Implement pmap_kenter_device(). o Create the l3 tables for the early devmap. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Do not setup machine exception vector.br2016-04-251-7/+0
| | | | | | | | | | | | | Sounds strange, but both RocketCore and lowRISC do not operate if we set it. All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses default machine trap vector address and operates fine with this. Original Berkeley Boot Loader (bbl) does not set this as well. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Revert r298477 ("Clear the DDR memory").br2016-04-251-11/+0
| | | | | | | | | There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of hardware (the bitfile synthesized for 4-level page memory system) and clearing was helpful, but then realized support for 4-level page system is untested/broken in both RocketCore and lowRISC.
* Clear the DDR memory. This should be done by bootloaders,br2016-04-221-0/+11
| | | | | | but they have no such feature yet. This fixes operation on Rocket Core and lowRISC.
* Add memory barriers (fence instructions) so the data wrotten by hardwarebr2016-04-221-3/+7
| | | | | | | | | to physical address now can be read by VA. This fixes operation on Rocket Core (FPGA). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Correct the event queue initialization.br2016-04-221-7/+8
| | | | | | | This fixes operation on Rocket Core. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* risc-v: for pointers replace 0 with NULL.pfg2016-04-141-1/+1
| | | | | | These are mostly cosmetical, no functional change. Found with devel/coccinelle.
* Add support for ddb(4).br2016-03-1012-8/+1125
| | | | | Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Make the fdt_get_mem_regions memsize argument optional. It's only used inandrew2016-03-011-2/+1
| | | | | | by a few callers. Sponsored by: ABT Systems Ltd
* Correct the memory rman ranges to be to BUS_SPACE_MAXADDRjhibbits2016-03-011-3/+4
| | | | | | | | | | | | | Summary: As part of the migration of rman_res_t to be typed to uintmax_t, memory ranges must be clamped appropriately for the bus, to prevent completely bogus addresses from being used. This is extracted from D4544. Reviewed By: cem Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5134
* Fix fdt_get_mem_regions() to work with 64-bit addresseswma2016-02-291-1/+1
| | | | | | | | | | | | Use u_long instead of uint32_t variables to avoid overflow in case of PA space bigger than 32-bit. Obtained from: Semihalf Submitted by: Michal Stanek <mst@semihalf.com> Sponsored by: Annapurna Labs Approved by: cognet (mentor) Reviewed by: andrew, br, wma Differential revision: https://reviews.freebsd.org/D5393
* o Use uint64_t for page number as it doesn't fit uint32_t.br2016-02-262-14/+16
| | | | | | | | | o Implement growkernel bits for L1 level of pagetables. This allows us to boot with 128GB of physical memory. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add support for symmetric multiprocessing (SMP).br2016-02-2418-107/+1008
| | | | | | | | | | | | | Tested on Spike simulator with 2 and 16 cores (tlb enabled), so set MAXCPU to 16 at this time. This uses FDT data to get information about CPUs (code based on arm64 mp_machdep). Invalidate entire TLB cache as it is the only way yet. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* o Grab physical memory regions information from the device tree.br2016-02-231-5/+10
| | | | o Increase memory size.
* Add basic trap handlers for illegal instruction and breakpointbr2016-02-221-0/+23
| | | | exceptions.
* Fix comment.br2016-02-221-2/+3
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* Remove duplicates.br2016-02-221-4/+0
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* Provide stack(9) MD stubs for RISC-V so ktr(9) can be compiled in.br2016-02-221-0/+63
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* Fix ktrace call.br2016-02-221-1/+1
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* As <machine/vmparam.h> is included from <vm/vm_param.h>, there is noskra2016-02-223-3/+0
| | | | | | | | need to include it explicitly when <vm/vm_param.h> is already included. Suggested by: alc Reviewed by: alc Differential Revision: https://reviews.freebsd.org/D5379
* Introduce a RMAN_IS_DEFAULT_RANGE() macro, and use it.jhibbits2016-02-201-1/+1
| | | | | | | | | | | This simplifies checking for default resource range for bus_alloc_resource(), and improves readability. This is part of, and related to, the migration of rman_res_t from u_long to uintmax_t. Discussed with: jhb Suggested by: marcel
* Increase kernel and user VA space.br2016-02-183-32/+34
| | | | | | | This allows us to boot with more than 128MB of physical memory. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of atomic_swap_32().br2016-02-171-0/+13
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* Use better form representing 32 x 128-bit floating-point registers.br2016-02-171-1/+1
| | | | Suggested by: kib
* There is no need to pre save tp in cpu_fork().br2016-02-171-6/+0
| | | | Discussed with: jhb
* Add the implementation of savectx().br2016-02-171-4/+23
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* Use callee-saved registers to pass args through fork_trampoline().br2016-02-172-17/+9
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* Use __uint64_t type for floating point registersbr2016-02-121-1/+1
| | | | | | as compiler don't know about __uint128_t yet. Discussed with: theraven, kib
* o Move non-generic kernel configuration out from GENERIC.br2016-02-113-3/+52
| | | | | | | | | | o Add kernel configuration for QEMU. Both SPIKE and QEMU kernel configs are temporary (until we will be able to obtain DTB from loader). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Stop device enumeration when we see first empty slot.br2016-02-111-3/+2
| | | | | | | | This fixes operation in QEMU and saves some booting time as well. Pointed out by: Sagar Karandikar <skarandikar@berkeley.edu> Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Include sys/_task.h into uma_int.h, so that taskqueue.h isn't aglebius2016-02-092-2/+0
| | | | | | requirement for uma_int.h. Suggested by: jhb
* Access pcpup using gp register.br2016-02-043-16/+6
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* Reuse gp register for pcpu pointer.br2016-02-046-23/+38
| | | | | | | | | | | gp (global pointer) is used by compiler in userland only, so re-use it for pcpup in kernel, save it on stack on switching out to userland and load back on return to kernel. Discussed with: jhb, andrew, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D5178
* Fix build.br2016-02-041-0/+1
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* Fix build.glebius2016-02-041-0/+1
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* Welcome the RISC-V 64-bit kernel.br2016-01-2936-0/+9929
| | | | | | | | | | | | | | | | | | | | | | | | This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
* Correct RISC-V exception types.br2016-01-181-4/+6
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* Import RISC-V machine headers. This is a minimal set required to compilebr2015-12-1757-0/+4616
kernel and userland. Reviewed by: andrew, imp, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4554
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