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| author | br <br@FreeBSD.org> | 2016-04-25 13:20:57 +0000 |
|---|---|---|
| committer | br <br@FreeBSD.org> | 2016-04-25 13:20:57 +0000 |
| commit | 63312613f4fa9b00e0032ffa9cc5d98ec58e1a08 (patch) | |
| tree | fe4237cd8c86185422674258a70df833bd56ed78 /sys/riscv | |
| parent | 8f86ed9783540d0930c785f7745de916dde84a3d (diff) | |
| download | FreeBSD-src-63312613f4fa9b00e0032ffa9cc5d98ec58e1a08.zip FreeBSD-src-63312613f4fa9b00e0032ffa9cc5d98ec58e1a08.tar.gz | |
Revert r298477 ("Clear the DDR memory").
There is no need to clear all the DDR memory (we only need to clear
BSS section).
I was playing with non-default version of hardware (the bitfile
synthesized for 4-level page memory system) and clearing was helpful,
but then realized support for 4-level page system is untested/broken
in both RocketCore and lowRISC.
Diffstat (limited to 'sys/riscv')
| -rw-r--r-- | sys/riscv/riscv/locore.S | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S index 1c2063a..ef81686 100644 --- a/sys/riscv/riscv/locore.S +++ b/sys/riscv/riscv/locore.S @@ -126,17 +126,6 @@ _start: csrr a0, mhartid bnez a0, mpentry -#if defined(DDR_CLEAR_SIZE) - /* Clear DDR memory */ - la t0, _end - li t1, DDR_CLEAR_SIZE -1: - sd zero, 0(t0) - addi t0, t0, 8 - bltu t0, t1, 1b - /* End */ -#endif - /* Build event queue for current core */ build_ring |
