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| author | br <br@FreeBSD.org> | 2016-04-25 13:30:37 +0000 |
|---|---|---|
| committer | br <br@FreeBSD.org> | 2016-04-25 13:30:37 +0000 |
| commit | 03e30c2263a33640cfa88601e15f6e41b3516d92 (patch) | |
| tree | c2b6339a42a980f3756cb67b0dd9018fd2082a7b /sys/riscv | |
| parent | 63312613f4fa9b00e0032ffa9cc5d98ec58e1a08 (diff) | |
| download | FreeBSD-src-03e30c2263a33640cfa88601e15f6e41b3516d92.zip FreeBSD-src-03e30c2263a33640cfa88601e15f6e41b3516d92.tar.gz | |
Do not setup machine exception vector.
Sounds strange, but both RocketCore and lowRISC do not operate
if we set it.
All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses
default machine trap vector address and operates fine with this.
Original Berkeley Boot Loader (bbl) does not set this as well.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Diffstat (limited to 'sys/riscv')
| -rw-r--r-- | sys/riscv/riscv/locore.S | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S index ef81686..3c7a6b3 100644 --- a/sys/riscv/riscv/locore.S +++ b/sys/riscv/riscv/locore.S @@ -133,9 +133,6 @@ _start: la t0, hardstack_end csrw mscratch, t0 - la t0, mentry - csrw mtvec, t0 - li t0, 0 csrw sscratch, t0 @@ -335,10 +332,6 @@ ENTRY(mpentry) lw t1, 0(t0) beqz t1, 1b - /* Setup machine exception vector */ - la t0, mentry - csrw mtvec, t0 - /* Build event queue ring for this core */ build_ring |
