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* Revert "Revert "MFC r319873:""Luiz Souza2018-02-231-4/+5
| | | | This reverts commit 4c9907d21517c211b27a3cf5b7a2a976623820cc.
* Revert "MFC r319873:"Luiz Souza2018-02-211-5/+4
| | | | This reverts commit 5dad0dd804a33b8a372d49fa342b24c67b1c2fb3.
* Revert "MFC r319871:"Luiz Souza2018-02-211-0/+4
| | | | This reverts commit 045793a68906243d204d36b336867187c1a33f00.
* MFC r319871:kib2018-02-191-4/+0
| | | | | | | Make struct syscall_args visible to userspace compilation environment from machine/proc.h, consistently on all architectures. (cherry picked from commit 06d5fa0600b92e97e90e41785ef10f641bdec89f)
* MFC r319873:kib2018-02-191-4/+5
| | | | | | | Move struct syscall_args syscall arguments parameters container into struct thread. (cherry picked from commit 985b26c6741218c134a15526fd32b736bd73fa8a)
* Fix indentation for r323068jpaetzel2017-11-031-1/+1
| | | | | | | | | | PR: 220170 Reported by: lidl MFC after: 3 days Pointyhat to: jpaetzel (cherry picked from commit b35131985ba34d195fcd9e25a16a979fff5c628d) (cherry picked from commit 957e5fdfa90fae8e3fe1ab547e91a0991c94f784)
* Allow kldload tcpmd5jpaetzel2017-11-031-0/+1
| | | | | | | | PR: 220170 MFC after: 2 weeks (cherry picked from commit f7739d7e092d8732c6f89f4b3e8df007d620552c) (cherry picked from commit 221df4835e8b41b4615c2bbdc6d95fa804755b9c)
* MFC efivar(8) (by imp):kib2017-05-201-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of revisions merged: r307070 r307071 r307072 r307074 r307189 r307224 r307339 r307390 r307391 r309776 r314231 r314232 r314615 r314616 r314617 r314618 r314619 r314620 r314621 r314623 r314890 r314925 r314926 r314927 r314928 r315770 r315771 Discussed with: gjb (re), imp Sponsored by: The FreeBSD Foundation
* MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,mjg2017-03-161-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r313254,r313341 amd64: add atomic_fcmpset == sparc64: add atomic_fcmpset == Implement atomic_fcmpset_* for arm and arm64. == Add atomic_fcmpset_*() inlines for powerpc Summary: atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value from the target memory location into the 'old' pointer in the case of failure. == i386: add atomic_fcmpset == Don't retry a lost reservation in atomic_fcmpset() The desired behavior of atomic_fcmpset_() is to always exit on error. Instead of retrying on lost reservation, leave the retry to the caller, and return == Add atomic_fcmpset_*() inlines for MIPS atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value from the target memory location into the 'old' pointer. == i386: fixup fcmpset An incorrect output specifier was used which worked with clang by accident, but breaks with the in-tree gcc version. While here plug a whitespace nit. == Implement atomic_fcmpset_*() for RISC-V. == Use 64bit store instruction in atomic_fcmpset_64.
* MFC r313194:kib2017-02-111-2/+0
| | | | Define the vm_ooffset_t and vm_pindex_t types as machine-independend.
* Update comments for the MD functions managing contexts for newkib2016-06-161-11/+10
| | | | | | | | | | | | | | | | threads, to make it less confusing and using modern kernel terms. Rename the functions to reflect current use of the functions, instead of the historic KSE conventions: cpu_set_fork_handler -> cpu_fork_kthread_handler (for kthreads) cpu_set_upcall -> cpu_copy_thread (for forks) cpu_set_upcall_kse -> cpu_set_upcall (for new threads creation) Reviewed by: jhb (previous version) Sponsored by: The FreeBSD Foundation MFC after: 1 week Approved by: re (hrs) Differential revision: https://reviews.freebsd.org/D6731
* Remove duplicate define.br2016-06-081-1/+0
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* Fix typos.br2016-06-021-11/+11
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* Add support for loadable kernel modules.br2016-06-012-3/+368
| | | | Submitted by: Yukishige Shibata <y-shibat@mtd.biglobe.ne.jp>
* * Enable KDTRACE options as we support DTrace now.br2016-06-011-2/+7
| | | | * Add bpf device to kernel config.
* Increase the size and alignment of the setjmp buffer.br2016-05-261-3/+3
| | | | | | | | This is required for future CPU extentions. Reviewed by: brooks Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add initial DTrace support for RISC-V.br2016-05-243-1/+28
| | | | | Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Store the original value of stack pointer to the exception framebr2016-05-241-1/+3
| | | | | | | | (the value we had before supervisor exception occurred). This helps consumers (e.g. DTrace) to not proceed additional calculations. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Eliminate an unused #include. For a brief period of time, _unrhdr.h wasalc2016-05-131-1/+0
| | | | | | used to implement PCID support on amd64. Reviewed by: kib
* Rework the list of all pmaps: embed the list link into pmap.br2016-04-262-24/+12
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* o Add device tree files and kernel configuration filesbr2016-04-266-2/+83
| | | | | for RISC-V cpus synthesized on FPGA hardware. o Include new files to the build.
* Add the non-standard "IO interrupt" vector used by lowRISC.br2016-04-264-3/+29
| | | | | | | For now they provide UART irq only. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of basic bus_space_read/write functions.br2016-04-262-12/+183
| | | | | Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of OF_decode_addr().br2016-04-261-0/+58
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* Move arm's devmap to some generic place, so it can be usedbr2016-04-262-61/+2
| | | | | | | | | by other architectures. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D6091 Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* o Implement shared pagetables and switch from 4 to 3 levels pagebr2016-04-258-76/+140
| | | | | | | | | | | | | | | | | | | | | | | | memory system. RISC-V ISA has only single page table base register for both kernel and user addresses translation. Before this commit we were using an extra (4th) level of pagetables for switching between kernel and user pagetables, but then realized FPGA hardware has 3-level page system hardcoded. It is also become clear that the bitfile synthesized for 4-level system is untested/broken, so we can't use extra level for switching. We are now share level 1 of pagetables between kernel and user VA. This requires to keep track of all the user pmaps created and once we adding L1 page to kernel pmap we have to add it to all the user pmaps. o Change the VM layout as we must have topmost bit to be 1 in the selected page system for kernel addresses and 0 for user addresses. o Implement pmap_kenter_device(). o Create the l3 tables for the early devmap. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Do not setup machine exception vector.br2016-04-251-7/+0
| | | | | | | | | | | | | Sounds strange, but both RocketCore and lowRISC do not operate if we set it. All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses default machine trap vector address and operates fine with this. Original Berkeley Boot Loader (bbl) does not set this as well. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Revert r298477 ("Clear the DDR memory").br2016-04-251-11/+0
| | | | | | | | | There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of hardware (the bitfile synthesized for 4-level page memory system) and clearing was helpful, but then realized support for 4-level page system is untested/broken in both RocketCore and lowRISC.
* Clear the DDR memory. This should be done by bootloaders,br2016-04-221-0/+11
| | | | | | but they have no such feature yet. This fixes operation on Rocket Core and lowRISC.
* Add memory barriers (fence instructions) so the data wrotten by hardwarebr2016-04-221-3/+7
| | | | | | | | | to physical address now can be read by VA. This fixes operation on Rocket Core (FPGA). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Correct the event queue initialization.br2016-04-221-7/+8
| | | | | | | This fixes operation on Rocket Core. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* risc-v: for pointers replace 0 with NULL.pfg2016-04-141-1/+1
| | | | | | These are mostly cosmetical, no functional change. Found with devel/coccinelle.
* Add support for ddb(4).br2016-03-1012-8/+1125
| | | | | Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Make the fdt_get_mem_regions memsize argument optional. It's only used inandrew2016-03-011-2/+1
| | | | | | by a few callers. Sponsored by: ABT Systems Ltd
* Correct the memory rman ranges to be to BUS_SPACE_MAXADDRjhibbits2016-03-011-3/+4
| | | | | | | | | | | | | Summary: As part of the migration of rman_res_t to be typed to uintmax_t, memory ranges must be clamped appropriately for the bus, to prevent completely bogus addresses from being used. This is extracted from D4544. Reviewed By: cem Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5134
* Fix fdt_get_mem_regions() to work with 64-bit addresseswma2016-02-291-1/+1
| | | | | | | | | | | | Use u_long instead of uint32_t variables to avoid overflow in case of PA space bigger than 32-bit. Obtained from: Semihalf Submitted by: Michal Stanek <mst@semihalf.com> Sponsored by: Annapurna Labs Approved by: cognet (mentor) Reviewed by: andrew, br, wma Differential revision: https://reviews.freebsd.org/D5393
* o Use uint64_t for page number as it doesn't fit uint32_t.br2016-02-262-14/+16
| | | | | | | | | o Implement growkernel bits for L1 level of pagetables. This allows us to boot with 128GB of physical memory. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add support for symmetric multiprocessing (SMP).br2016-02-2418-107/+1008
| | | | | | | | | | | | | Tested on Spike simulator with 2 and 16 cores (tlb enabled), so set MAXCPU to 16 at this time. This uses FDT data to get information about CPUs (code based on arm64 mp_machdep). Invalidate entire TLB cache as it is the only way yet. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* o Grab physical memory regions information from the device tree.br2016-02-231-5/+10
| | | | o Increase memory size.
* Add basic trap handlers for illegal instruction and breakpointbr2016-02-221-0/+23
| | | | exceptions.
* Fix comment.br2016-02-221-2/+3
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* Remove duplicates.br2016-02-221-4/+0
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* Provide stack(9) MD stubs for RISC-V so ktr(9) can be compiled in.br2016-02-221-0/+63
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* Fix ktrace call.br2016-02-221-1/+1
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* As <machine/vmparam.h> is included from <vm/vm_param.h>, there is noskra2016-02-223-3/+0
| | | | | | | | need to include it explicitly when <vm/vm_param.h> is already included. Suggested by: alc Reviewed by: alc Differential Revision: https://reviews.freebsd.org/D5379
* Introduce a RMAN_IS_DEFAULT_RANGE() macro, and use it.jhibbits2016-02-201-1/+1
| | | | | | | | | | | This simplifies checking for default resource range for bus_alloc_resource(), and improves readability. This is part of, and related to, the migration of rman_res_t from u_long to uintmax_t. Discussed with: jhb Suggested by: marcel
* Increase kernel and user VA space.br2016-02-183-32/+34
| | | | | | | This allows us to boot with more than 128MB of physical memory. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Add the implementation of atomic_swap_32().br2016-02-171-0/+13
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* Use better form representing 32 x 128-bit floating-point registers.br2016-02-171-1/+1
| | | | Suggested by: kib
* There is no need to pre save tp in cpu_fork().br2016-02-171-6/+0
| | | | Discussed with: jhb
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