| Commit message (Collapse) | Author | Age | Files | Lines |
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This reverts commit 4c9907d21517c211b27a3cf5b7a2a976623820cc.
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This reverts commit 5dad0dd804a33b8a372d49fa342b24c67b1c2fb3.
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This reverts commit 045793a68906243d204d36b336867187c1a33f00.
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Make struct syscall_args visible to userspace compilation environment
from machine/proc.h, consistently on all architectures.
(cherry picked from commit 06d5fa0600b92e97e90e41785ef10f641bdec89f)
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Move struct syscall_args syscall arguments parameters container into
struct thread.
(cherry picked from commit 985b26c6741218c134a15526fd32b736bd73fa8a)
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PR: 220170
Reported by: lidl
MFC after: 3 days
Pointyhat to: jpaetzel
(cherry picked from commit b35131985ba34d195fcd9e25a16a979fff5c628d)
(cherry picked from commit 957e5fdfa90fae8e3fe1ab547e91a0991c94f784)
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PR: 220170
MFC after: 2 weeks
(cherry picked from commit f7739d7e092d8732c6f89f4b3e8df007d620552c)
(cherry picked from commit 221df4835e8b41b4615c2bbdc6d95fa804755b9c)
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List of revisions merged:
r307070
r307071
r307072
r307074
r307189
r307224
r307339
r307390
r307391
r309776
r314231
r314232
r314615
r314616
r314617
r314618
r314619
r314620
r314621
r314623
r314890
r314925
r314926
r314927
r314928
r315770
r315771
Discussed with: gjb (re), imp
Sponsored by: The FreeBSD Foundation
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r313254,r313341
amd64: add atomic_fcmpset
==
sparc64: add atomic_fcmpset
==
Implement atomic_fcmpset_* for arm and arm64.
==
Add atomic_fcmpset_*() inlines for powerpc
Summary:
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value
from the target memory location into the 'old' pointer in the case of failure.
==
i386: add atomic_fcmpset
==
Don't retry a lost reservation in atomic_fcmpset()
The desired behavior of atomic_fcmpset_() is to always exit on error. Instead
of retrying on lost reservation, leave the retry to the caller, and return
==
Add atomic_fcmpset_*() inlines for MIPS
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the
read value from the target memory location into the 'old' pointer.
==
i386: fixup fcmpset
An incorrect output specifier was used which worked with clang by accident,
but breaks with the in-tree gcc version.
While here plug a whitespace nit.
==
Implement atomic_fcmpset_*() for RISC-V.
==
Use 64bit store instruction in atomic_fcmpset_64.
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Define the vm_ooffset_t and vm_pindex_t types as machine-independend.
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threads, to make it less confusing and using modern kernel terms.
Rename the functions to reflect current use of the functions, instead
of the historic KSE conventions:
cpu_set_fork_handler -> cpu_fork_kthread_handler (for kthreads)
cpu_set_upcall -> cpu_copy_thread (for forks)
cpu_set_upcall_kse -> cpu_set_upcall (for new threads creation)
Reviewed by: jhb (previous version)
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Approved by: re (hrs)
Differential revision: https://reviews.freebsd.org/D6731
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Submitted by: Yukishige Shibata <y-shibat@mtd.biglobe.ne.jp>
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* Add bpf device to kernel config.
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This is required for future CPU extentions.
Reviewed by: brooks
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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(the value we had before supervisor exception occurred).
This helps consumers (e.g. DTrace) to not proceed additional calculations.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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used to implement PCID support on amd64.
Reviewed by: kib
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for RISC-V cpus synthesized on FPGA hardware.
o Include new files to the build.
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For now they provide UART irq only.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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by other architectures.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D6091
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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memory system.
RISC-V ISA has only single page table base register for both kernel
and user addresses translation. Before this commit we were using an
extra (4th) level of pagetables for switching between kernel and user
pagetables, but then realized FPGA hardware has 3-level page system
hardcoded. It is also become clear that the bitfile synthesized for
4-level system is untested/broken, so we can't use extra level for
switching.
We are now share level 1 of pagetables between kernel and user VA.
This requires to keep track of all the user pmaps created and once we
adding L1 page to kernel pmap we have to add it to all the user pmaps.
o Change the VM layout as we must have topmost bit to be 1 in the
selected page system for kernel addresses and 0 for user addresses.
o Implement pmap_kenter_device().
o Create the l3 tables for the early devmap.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Sounds strange, but both RocketCore and lowRISC do not operate
if we set it.
All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses
default machine trap vector address and operates fine with this.
Original Berkeley Boot Loader (bbl) does not set this as well.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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There is no need to clear all the DDR memory (we only need to clear
BSS section).
I was playing with non-default version of hardware (the bitfile
synthesized for 4-level page memory system) and clearing was helpful,
but then realized support for 4-level page system is untested/broken
in both RocketCore and lowRISC.
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but they have no such feature yet.
This fixes operation on Rocket Core and lowRISC.
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to physical address now can be read by VA.
This fixes operation on Rocket Core (FPGA).
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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This fixes operation on Rocket Core.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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These are mostly cosmetical, no functional change.
Found with devel/coccinelle.
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Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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by a few callers.
Sponsored by: ABT Systems Ltd
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Summary:
As part of the migration of rman_res_t to be typed to uintmax_t, memory ranges
must be clamped appropriately for the bus, to prevent completely bogus addresses
from being used.
This is extracted from D4544.
Reviewed By: cem
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5134
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Use u_long instead of uint32_t variables to avoid overflow
in case of PA space bigger than 32-bit.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Approved by: cognet (mentor)
Reviewed by: andrew, br, wma
Differential revision: https://reviews.freebsd.org/D5393
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o Implement growkernel bits for L1 level of pagetables.
This allows us to boot with 128GB of physical memory.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.
This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).
Invalidate entire TLB cache as it is the only way yet.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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o Increase memory size.
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exceptions.
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need to include it explicitly when <vm/vm_param.h> is already included.
Suggested by: alc
Reviewed by: alc
Differential Revision: https://reviews.freebsd.org/D5379
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This simplifies checking for default resource range for bus_alloc_resource(),
and improves readability.
This is part of, and related to, the migration of rman_res_t from u_long to
uintmax_t.
Discussed with: jhb
Suggested by: marcel
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This allows us to boot with more than 128MB of physical memory.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Suggested by: kib
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Discussed with: jhb
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