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* Move all the power management (SMBus) drivers to their own directory,rpaulo2014-09-235-3264/+0
| | | | away from sys/pci.
* Move amdsmb and nfsmb from dev/pci to their own device directory.rpaulo2014-09-232-1242/+0
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* Move pci/ncr to dev/ncr.rpaulo2014-09-233-7767/+0
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* Move rl(4) to dev/rl.glebius2014-09-192-3286/+0
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* Fix various NIC drivers to properly cleanup static DMA resources.jhb2014-06-111-4/+3
| | | | | | | | | | | | | | | In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
* Increase the number of TX DMA segments from 32 to 35. It turnedyongari2014-03-311-1/+1
| | | | | | | | | | out 32 is not enough to support a full sized TSO packet. While I'm here fix a long standing bug introduced in r169632 in bce(4) where it didn't include L2 header length of TSO packet in the maximum DMA segment size calculation. In collaboration with: rmacklem MFC after: 2 weeks
* - Implement the RX EARLYOFF and RXDV GATED bits as done by RealTek's Linuxmarius2014-02-051-0/+6
| | | | | | | | | | driver as version 8.037.00 for RTL8168{E-VL,EP,F,G,GU} and RTL8111B. This makes reception of packets work with the RTL8168G (HW rev. 0x4c000000) in my Shuttle DS47. - Consistently use RL_MSI_MESSAGES. In joint forces with: yongari MFC after: 5 days
* Try to make the style used here consistent.marius2014-02-051-12/+3
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* Add preliminary support for RTL8168EP.yongari2013-10-291-0/+1
| | | | Submitted by: Edward O'Callaghan (eocallaghan <> alterapraxis dot com)
* Add preliminary support for RTL8168G, RTL8168GU and RTL8411B.yongari2013-10-291-0/+3
| | | | | | | | | RTL8168GU has two variants(GMII and MII) but it uses the same chip revision id. Driver checks PCI device id of controller and sets internal capability flag(i.e. jumbo frame and link speed down in WOL). H/W donated by: RealTek Semiconductor Corp.
* The r48589 promised to remove implicit inclusion of if_var.h soon. Prepareglebius2013-10-261-0/+1
| | | | | | | | to this event, adding if_var.h to files that do need it. Also, include all includes that now are included due to implicit pollution via if_var.h Sponsored by: Netflix Sponsored by: Nginx, Inc.
* Add preliminary support for RTL8106E PCIe FastEthernet.yongari2013-10-211-0/+1
| | | | H/W donated by: RealTek Semiconductor Corp.
* Correct MAC revision bits. Previously it always cleared bit 20 andyongari2013-10-211-0/+1
| | | | bit 21.
* Update PCI drivers to no longer look at the MEMIO-enabled bit in the PCIscottl2013-08-121-2/+2
| | | | | | | | | | | | | | | | | command register. The lazy BAR allocation code in FreeBSD sometimes disables this bit when it detects a range conflict, and will re-enable it on demand when a driver allocates the BAR. Thus, the bit is no longer a reliable indication of capability, and should not be checked. This results in the elimination of a lot of code from drivers, and also gives the opportunity to simplify a lot of drivers to use a helper API to set the busmaster enable bit. This changes fixes some recent reports of disk controllers and their associated drives/enclosures disappearing during boot. Submitted by: jhb Reviewed by: jfv, marius, achadd, achim MFC after: 1 day
* - Corrrect mispellings of word usefulgabor2013-04-171-1/+1
| | | | Submitted by: Christoph Mallon <christoph.mallon@gmx.de> (via private mail)
* Fix build.glebius2013-02-211-1/+0
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* Most other giant locked storage drivers in the tree don't useimp2013-02-211-5/+0
| | | | | splsoftclock to note the need for future locking, so remove it from here.
* Kill now-bogus splhigh() -- it is a nopimp2013-02-211-1/+0
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* Mark 'ticks', 'time_second', and 'time_uptime' as volatile to prevent thejhb2013-01-281-1/+1
| | | | | | | compiler from caching their values in tight loops. Reviewed by: bde MFC after: 1 week
* Add D-Link DFE-520TX rev C1.yongari2013-01-162-0/+7
| | | | | Tested by: Ruslan Makhmatkhanov < cvs-src <> yandex dot ru > MFC After: 1 week
* Mechanically substitute flags from historic mbuf allocator withglebius2012-12-051-1/+1
| | | | | | | | | malloc(9) flags within sys. Exceptions: - sys/contrib not touched - sys/mbuf.h edited manually
* Remove duplicate const specifiers in many drivers (I hope I got all ofdim2012-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
* intpm: add ATI IXP400 pci idavg2012-04-161-0/+3
| | | | | | | PR: kern/136762 Submitted by: Aurelien Mere <freebsd@amc-os.com> Tested by: Jens Link <jens.link@gmx.de> MFC after: 5 days
* intpm: return only SMB bus error codes from SMB methodsavg2012-04-081-3/+3
| | | | | PR: kern/25733 MFC after: 5 days
* intpm: reflect the fact that SB800 and later AMD chipsets are not supportedavg2012-04-081-0/+3
| | | | | | | | They do not have compatible configuration registers in PCI configuration space. Instead their configuration resides in AMD "PM I/O" space (accessed via a pair of I/O space registers). MFC after: 5 days
* Use correct Config registers for RTL8139 family. Unlike RTL8168 andyongari2012-02-252-14/+37
| | | | | | | | | | | | | RTL810x family , RTL8139 has different register map for Config registers. While here, follow the lead of re(4) in WOL configuration. - Disable WOL_UCAST and WOL_MCAST capabilities by default. - Config5 register write does not need to unlock EEPROM access on RTL8139 family but unlocking EEPROM access does not affect its operation and make it consistent with re(4). Reported by: Matt Renzelmann mjr <> cs dot wisc dot edu
* To save more power, switch to 10/100Mbps link when controller isyongari2011-11-231-0/+1
| | | | | | | | put into suspend/shutdown. Old PCI controllers performed that operation in firmware but for RTL8111C or newer controllers, it's responsibility of driver. It's not clear whether the firmware of RTL8111B still downgrades its speed to 10/100Mbps so leave it as it was.
* Make sure to stop TX MAC before freeing queued TX frames.yongari2011-11-231-16/+19
| | | | | | For RTL8111DP, check if the TX MAC is active by reading RL_GTXSTART register. For RTL8402/8168E-VL/8168F/8411, wait until TX queue is empty.
* - There's no need to overwrite the default device method with the defaultmarius2011-11-223-13/+4
| | | | | | | | | | one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
* Add preliminary support for RTL8168/8111F PCIe Gigabit ethernet.yongari2011-11-171-0/+1
| | | | H/W donated by: RealTek Semiconductor Corp.
* Add preliminary support for second generation RTL8105E PCIeyongari2011-11-171-0/+1
| | | | | | FastEthernet. H/W donated by: RealTek Semiconductor Corp.
* Disable PCIe ASPM (Active State Power Management) for allyongari2011-11-161-0/+1
| | | | | | | | | controllers. More and more RealTek controllers started to implement EEE feature. Vendor driver seems to load a kind of firmware for EEE with additional PHY fixups. It is known that the EEE feature may need ASPM support. Unfortunately there is no documentation for EEE of the controller so enabling ASPM may cause more problems.
* Add preliminary support for RTL8411 PCIe Gigabit ethernet withyongari2011-11-161-0/+1
| | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp.
* Add preliminary support for RTL8402 PCIe FastEthernet withyongari2011-11-161-0/+1
| | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp.
* - Import the common MII bitbang'ing code from NetBSD and convert drivers tomarius2011-11-012-201/+52
| | | | | | | | | | | | | | | | | | | | | | | | take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
* Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.yongari2011-10-171-1/+1
| | | | | | | | Because driver is accessing a common MII structure in mii_pollstat(), updating user supplied structure should be done before dropping a driver lock. Reported by: Karim (fodillemlinkarimi <> gmail dot com)
* Add new device id of D-Link DGE-530T Rev. C controller. DGE-503Tyongari2011-07-301-0/+1
| | | | | | | | Rev A1 and B1 is supported by sk(4) but the DGE-530T Rev. C controller is re-branded RealTek 8169 controller. PR: kern/159116 Approved by: re (kib)
* Do a sweep of the tree replacing calls to pci_find_extcap() with calls tojhb2011-03-231-3/+3
| | | | pci_find_cap() instead.
* Add initial support for RTL8401E PCIe Fast Ethernet.yongari2011-02-161-0/+1
| | | | PR: 154789
* Add support for RTL8105E PCIe Fast Ethernet controller. It seemsyongari2011-01-261-0/+1
| | | | | | | | | | | | | | the controller has a kind of embedded controller/memory and vendor applies a large set of magic code via undocumented PHY registers in device initialization stage. I guess it's a firmware image for the embedded controller in RTL8105E since the code is too big compared to other DSP fixups. However I have no idea what that magic code does and what's purpose of the embedded controller. Fortunately driver seems to still work without loading the firmware. While I'm here change device description of RTL810xE controller. H/W donated by: Realtek Semiconductor Corp.
* Do not use interrupt taskqueue on controllers with MSI/MSI-Xyongari2011-01-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | capability. One of reason using interrupt taskqueue in re(4) was to reduce number of TX/RX interrupts under load because re(4) controllers have no good TX/RX interrupt moderation mechanism. Basic TX interrupt moderation is done by hardware for most controllers but RX interrupt moderation through undocumented register showed poor RX performance so it was disabled in r215025. Using taskqueue to handle RX interrupt greatly reduced number of interrupts but re(4) consumed all available CPU cycles to run the taskqueue under high TX/RX network load. This can happen even with RTL810x fast ethernet controller and I believe this is not acceptable for most systems. To mitigate the issue, use one-shot timer register to moderate RX interrupts. The timer register provides programmable one-shot timer and can be used to suppress interrupt generation. The timer runs at 125MHZ on PCIe controllers so the minimum time allowed for the timer is 8ns. Data sheet says the register is 32 bits but experimentation shows only lower 13 bits are valid so maximum time that can be programmed is 65.528us. This yields theoretical maximum number of RX interrupts that could be generated per second is about 15260. Combined with TX completion interrupts re(4) shall generate less than 20k interrupts. This number is still slightly high compared to other intelligent ethernet controllers but system is very responsive even under high network load. Introduce sysctl variable dev.re.%d.int_rx_mod that controls amount of time to delay RX interrupt processing in units of us. Value 0 completely disables RX interrupt moderation. To provide old behavior for controllers that have MSI/MSI-X capability, introduce a new tunable hw.re.intr_filter. If the tunable is set to non-zero value, driver will use interrupt taskqueue. The default value of the tunable is 0. This tunable has no effect on controllers that has no MSI/MSI-X capability or if MSI/MSI-X is explicitly disabled by administrator. While I'm here cleanup interrupt setup/teardown since re(4) uses single MSI/MSI-X message at this moment.
* Remove TX taskqueue and directly invoke re_start in interrupt task.yongari2011-01-251-1/+0
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* Prefer MSI-X to MSI on controllers that support MSI-X. Allyongari2011-01-251-0/+2
| | | | | | | recent PCIe controllers(RTL8102E or later and RTL8168/8111C or later) supports either 2 or 4 MSI-X messages. Unfortunately vendor did not publicly release RSS related information yet. However switching to MSI-X is one-step forward to support RSS.
* Change model names of controller RTL_HWREV_8168_SPIN[123] to real ones.yongari2011-01-181-3/+3
| | | | | | | s/RL_HWREV_8168_SPIN1/RL_HWREV_8168B_SPIN1/g s/RL_HWREV_8168_SPIN2/RL_HWREV_8168B_SPIN2/g s/RL_HWREV_8168_SPIN3/RL_HWREV_8168B_SPIN3/g No functional changes.
* Implement initial jumbo frame support for RTL8168/8111 C/D/E PCIeyongari2011-01-171-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | GbE controllers. It seems these controllers no longer support multi-fragmented RX buffers such that driver have to allocate physically contiguous buffers. o Retire RL_FLAG_NOJUMBO flag and introduce RL_FLAG_JUMBOV2 to mark controllers that use new jumbo frame scheme. o Configure PCIe max read request size to 4096 for standard frames and reduce it to 512 for jumbo frames. o TSO/checksum offloading is not supported for jumbo frames on these controllers. Reflect it to ioctl handler and driver initialization. o Remove unused rl_stats_no_timeout in softc. o Embed a pointer to structure rl_hwrev into softc to keep track of controller MTU limitation and remove rl_hwrev in softc since that information is available through a pointer to structure rl_hwrev. Special thanks to Realtek for donating sample hardwares which made this possible. H/W donated by: Realtek Semiconductor Corp.
* Add initial support for RTL8168E/8111E-VL PCIe GbE.yongari2011-01-171-0/+1
| | | | H/W donated by: Realtek Semiconductor Corp.
* Implement TSO on RealTek RTL8168/8111 C or later controllers.yongari2011-01-101-0/+2
| | | | | | | | | | | | RealTek changed TX descriptor format for later controllers so these controllers require MSS configuration in different location of TX descriptor. TSO is enabled by default for controllers that use new descriptor format. For old controllers, TSO is still disabled by default due to broken frames under certain conditions but users can enable it. Special thanks to Hayes Wang at RealTek. MFC after: 2 weeks
* Remove standard PCI configuration space register definitions.yongari2010-11-081-35/+0
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* Remove trailing white spaces.yongari2010-11-081-7/+7
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* Consistently use tab character instead of using space character.yongari2010-11-081-500/+500
| | | | No functional changes.
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