| Commit message (Collapse) | Author | Age | Files | Lines |
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r315845, 315430, r317981, r315466
o Fix some overly long lines, whitespace and other bugs according to
style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method,
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.
o Trim/adjust includes.
o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4).
o Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)
Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.
CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.
o Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications.
o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter have been added to ports as sysutils/mmc-utils.
Among others, the `mmc` tool of mmc-utils allows for partitioning
eMMC devices (tested working).
o For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.
o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.
o In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
controllers as such in order to match the PCI one.
Additionally, in the entry for the 80860F14 SDXC controller remove
the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.
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Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need
this on a few earlier arm SoCs.
Restrict where we need to define fdt_fixup_table to just PowerPC and
Marvell.
Add the missing void to function signatures in much of the arm code.
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ARM: Remove unused includes.
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ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it
directly.
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Reviewed by: ganbold
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Only affects comments: no functional change.
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by other architectures.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D6091
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
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Replacements specific to arm, mips, pc98, powerpc and sparc64.
Discussed in: freebsd-current
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independent code that needs to know about INTRNG such as PCI drivers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
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Found with devel/coccinelle.
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a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This
is because the kernel linker only searches for symbols in dependent modules,
so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc
was not compiled into the kernel (even if you hand-loaded mmc first).
(Thanks to jilles@ for providing the vital clue about the kernel linker.)
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intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
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slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
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identical.
Sponsored by: ABT Systems Ltd
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Only L2 PIPT cache is supported for __ARM_ARCH >= 6.
In fact, this is just a pure proclamation as this option is used
only in armv4 specific files now.
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in all but ARMv4 specific files.
Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address
in L2 cache functions if ARM_L2_PIPT is defined.
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The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
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the various bridge drivers out of dev/mmc.c and into the bridge drivers.
Requested by: jhb (almost two years ago; better late than never)
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and enable it for Odroid C1 board.
Together with r291676 change, dwc(4) can receive packets now.
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definition in a file.* file under sys/arm/arm in the few cases we need it
for non-fdt platforms.
Sponsored by: ABT Systems Ltd
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Sponsored by: ABT Systems Ltd
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the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.
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This also adds a newbus interface that allows a SoC to override the
following settings:
- if_dwc specific SoC initialization;
- if_dwc descriptor type;
- if_dwc MII clock.
This seems to be an old version of the hardware descriptors but it is
still in use in a few SoCs (namely Allwinner A20 and Amlogic at least).
Tested on Cubieboard2 and Banana pi.
Tested for regressions on Altera Cyclone by br@ (old version).
Obtained from: NetBSD
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years for head. However, it is continuously misused as the mpsafe argument
for callout_init(9). Deprecate the flag and clean up callout_init() calls
to make them more consistent.
Differential Revision: https://reviews.freebsd.org/D2613
Reviewed by: jhb
MFC after: 2 weeks
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Submitted by: John Wehle
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Differential Revision: https://reviews.freebsd.org/D2590
Submitted by: John Wehle
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Submitted by: John Wehle
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determined at runtime so there's no need to set the values in
each DTS.
Tested on YYHD18 (aml8726-m3), VSATV102 (aml8726-m6), and
ODROIDC1 (aml8726-m8b).
Differential Revision: https://reviews.freebsd.org/D2588
Submitted by: John Wehle
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we have both the Amlogic pic and a GIC. This may be the case in some
configurations.
Differential Revision: https://reviews.freebsd.org/D2432
Submitted by: John Wehle <john@feith.com>
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The aml8726-m3 SoC is identified as a Cortex A9-r2 rev 4 CPU and
it hangs sometimes during the boot when WFI is used by the kernel.
Differential Revision: https://reviews.freebsd.org/D2473
Submitted by: John Wehle
Suggested by: ian@
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Amlogic pic driver.
Differential Revision: https://reviews.freebsd.org/D2472
Submitted by: John Wehle
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available on the aml8726-m6 (and later) SoC which allows for
lower speeds.
Differential Revision: https://reviews.freebsd.org/D2433
Submitted by: John Wehle
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1) Advertise the actual min / max speeds the hardware is capable
of supporting given the reference clock used by the board.
2) Rather than attempting to extend the hardware's timeout register
in software (the hardware doesn't have sufficient bits to directly
support long timeouts), simply implement the same timeout approach
used in the SDXC driver.
3) Set the timeout for a linked command (e.g. STOP TRANSMISSION) based
on the previous multiblock read / write.
The changes have been smoke tested on both the ODROID-C1 and the VSATV102-M6
using the following cards:
* PQI 2GB microSD
* SanDisk 2GB microSD
* PQI 8GB SDHC (not a microSD so only tested on the ATV-102)
* PNY 8GB microSDHC
* SanDisk Ultra 32GB microSDHC
Submitted by: John Wehle
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options they set to the main kernel config.
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- Remove a redundant file from files.aml8726
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This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.
This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.
MFC after: 1 week
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supply clk81 information. It also changes the hardware strings
in some of the drivers to match what's present in the GNU files.
Submitted by: John Wehle
Reviewed by: imp
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present in the GNU dts files.
Submitted by: John Wehle
Reviewed by: imp
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specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.
The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer
Submitted by: John Wehle
Approved by: stas (mentor)
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