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* Don't advertise the Instruction Based Sampling feature because it requiresneel2014-10-171-0/+5
| | | | | | | | emulating a large number of MSRs. Ignore writes to a couple more AMD-specific MSRs and return 0 on read. This further reduces the unimplemented MSRs accessed by a Linux guest on boot.
* Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 inneel2014-10-171-0/+8
| | | | | | | | | | CPUID.80000001H:ECX. Handle accesses to PerfCtrX and PerfEvtSelX MSRs by ignoring writes and returning 0 on reads. This further reduces the number of unimplemented MSRs hit by a Linux guest during boot.
* Use the correct fault type (VM_PROT_EXECUTE) for an instruction fetch.neel2014-10-161-0/+2
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* Fix topology enumeration issues exposed by AMD Bulldozer Family 15h processor.neel2014-10-161-2/+24
| | | | | | | | | | | | | Initialize CPUID.80000008H:ECX[7:0] with the number of logical processors in the package. This fixes a panic during early boot in NetBSD 7.0 BETA. Clear the Topology Extension feature bit from CPUID.80000001H:ECX since we don't emulate leaves 0x8000001D and 0x8000001E. This fixes a divide by zero panic in early boot in Centos 6.4. Tested on an "AMD Opteron 6320" courtesy of Ben Perrault. Reviewed by: grehan
* Actually hide the SVM capability by clearing CPUID.80000001H:ECX[bit 3]neel2014-10-151-2/+6
| | | | | | after it has been initialized by cpuid_count(). Submitted by: Anish Gupta (akgupt3@gmail.com)
* Remove extraneous comments.neel2014-10-111-22/+6
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* Get rid of unused headers.neel2014-10-113-193/+126
| | | | | | Restrict scope of malloc types M_SVM and M_SVM_VLAPIC by making them static. Replace ERR() with KASSERT(). style(9) cleanup.
* Get rid of unused forward declaration of 'struct svm_softc'.neel2014-10-111-2/+1
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* style(9) fixes.neel2014-10-111-8/+1
| | | | Get rid of unused headers.
* Use a consistent style for messages emitted when the module is loaded.neel2014-10-111-28/+24
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* IFC @r272887neel2014-10-108-13/+133
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| * Support Intel-specific MSRs that are accessed when booting up a linux in bhyve:neel2014-10-091-0/+100
| | | | | | | | | | | | | | | | | | - MSR_PLATFORM_INFO - MSR_TURBO_RATIO_LIMITx - MSR_RAPL_POWER_UNIT Reviewed by: grehan MFC after: 1 week
| * Pass up the error status of minidumpsys() to its callers.markj2014-10-082-3/+4
| | | | | | | | | | | | PR: 193761 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Sponsored by: EMC / Isilon Storage Division
| * Add an argument to the x86 pmap_invalidate_cache_range() to requestkib2014-10-082-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | forced invalidation of the cache range regardless of the presence of self-snoop feature. Some recent Intel GPUs in some modes are not coherent, and dirty lines in CPU cache must be flushed before the pages are transferred to GPU domain. Reviewed by: alc (previous version) Tested by: pho (amd64) Sponsored by: The FreeBSD Foundation MFC after: 1 week
| * Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT'.neel2014-10-063-0/+14
| | | | | | | | | | | | | | | | The hypervisor hides the MONITOR/MWAIT capability by unconditionally setting CPUID.01H:ECX[3] to 0 so the guest should not expect these instructions to be present anyways. Discussed with: grehan
* | Fix bhyvectl so it works correctly on AMD/SVM hosts. Also, add command lineneel2014-10-102-0/+88
| | | | | | | | | | | | | | | | | | | | | | options to display some key VMCB fields. The set of valid options that can be passed to bhyvectl now depends on the processor type. AMD-specific options are identified by a "--vmcb" or "--avic" in the option name. Intel-specific options are identified by a "--vmcs" in the option name. Submitted by: Anish Gupta (akgupt3@gmail.com)
* | IFC @r272481neel2014-10-053-68/+30
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| * Get rid of code that dealt with the hardware not being able to save/restoreneel2014-10-021-55/+17
| | | | | | | | | | | | | | | | | | | | the PAT MSR on guest exit/entry. This workaround was done for a beta release of VMware Fusion 5 but is no longer needed in later versions. All Intel CPUs since Nehalem have supported saving and restoring MSR_PAT in the VM exit and entry controls. Discussed with: grehan
| * msi: add Xen MSI implementationroyger2014-09-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MSI interrupts when running on Xen. Apart from adding the Xen related code needed in order to register MSI interrupts this patch also makes the msi_init function a hook in init_ops, so different MSI implementations can have different initialization functions. Sponsored by: Citrix Systems R&D xen/interface/physdev.h: - Add the MAP_PIRQ_TYPE_MULTI_MSI to map multi-vector MSI to the Xen public interface. x86/include/init.h: - Add a hook for setting custom msi_init methods. amd64/amd64/machdep.c: i386/i386/machdep.c: - Set the default msi_init hook to point to the native MSI initialization method. x86/xen/pv.c: - Set the Xen MSI init hook when running as a Xen guest. x86/x86/local_apic.c: - Call the msi_init hook instead of directly calling msi_init. xen/xen_intr.h: x86/xen/xen_intr.c: - Introduce support for registering/releasing MSI interrupts with Xen. - The MSI interrupts will use the same PIC as the IO APIC interrupts. xen/xen_msi.h: x86/xen/xen_msi.c: - Introduce a Xen MSI implementation. x86/xen/xen_nexus.c: - Overwrite the default MSI hooks in the Xen Nexus to use the Xen MSI implementation. x86/xen/xen_pci.c: - Introduce a Xen specific PCI bus that inherits from the ACPI PCI bus and overwrites the native MSI methods. - This is needed because when running under Xen the MSI messages used to configure MSI interrupts on PCI devices are written by Xen itself. dev/acpica/acpi_pci.c: - Lower the quality of the ACPI PCI bus so the newly introduced Xen PCI bus can take over when needed. conf/files.i386: conf/files.amd64: - Add the newly created files to the build process.
| * Allow the PIC's IMR register to be read before ICW initialisation.grehan2014-09-271-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of git submit e179f6914152eca9, the Linux kernel does a simple probe of the PIC by writing a pattern to the IMR and then reading it back, prior to the init sequence of ICW words. The bhyve PIC emulation wasn't allowing the IMR to be read until the ICW sequence was complete. This limitation isn't required so relax the test. With this change, Linux kernels 3.15-rc2 and later won't hang on boot when calibrating the local APIC. Reviewed by: tychon MFC after: 3 days
* | IFC @r272185neel2014-09-278-23/+32
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| * ddb: allow specifying the exact address of the symtab and strtabroyger2014-09-251-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the FreeBSD kernel is loaded from Xen the symtab and strtab are not loaded the same way as the native boot loader. This patch adds three new global variables to ddb that can be used to specify the exact position and size of those tables, so they can be directly used as parameters to db_add_symbol_table. A new helper is introduced, so callers that used to set ksym_start and ksym_end can use this helper to set the new variables. It also adds support for loading them from the Xen PVH port, that was previously missing those tables. Sponsored by: Citrix Systems R&D Reviewed by: kib ddb/db_main.c: - Add three new global variables: ksymtab, kstrtab, ksymtab_size that can be used to specify the position and size of the symtab and strtab. - Use those new variables in db_init in order to call db_add_symbol_table. - Move the logic in db_init to db_fetch_symtab in order to set ksymtab, kstrtab, ksymtab_size from ksym_start and ksym_end. ddb/ddb.h: - Add prototype for db_fetch_ksymtab. - Declate the extern variables ksymtab, kstrtab and ksymtab_size. x86/xen/pv.c: - Add support for finding the symtab and strtab when booted as a Xen PVH guest. Since Xen loads the symtab and strtab as NetBSD expects to find them we have to adapt and use the same method. amd64/amd64/machdep.c: arm/arm/machdep.c: i386/i386/machdep.c: mips/mips/machdep.c: pc98/pc98/machdep.c: powerpc/aim/machdep.c: powerpc/booke/machdep.c: sparc64/sparc64/machdep.c: - Use the newly introduced db_fetch_ksymtab in order to set ksymtab, kstrtab and ksymtab_size.
| * As per [1] Intel only supports this driver on 64bit platforms.bz2014-09-232-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now restrict it to amd64. Other architectures might be re-added later once tested. Remove the drivers from the global NOTES and files files and move them to the amd64 specifics. Remove the drivers from the i386 modules build and only leave the amd64 version. Rather than depending on "inet" depend on "pci" and make sure that ixl(4) and ixlv(4) can be compiled independently [2]. This also allows the drivers to build properly on IPv4-only or IPv6-only kernels. PR: 193824 [2] Reviewed by: eric.joyner intel.com MFC after: 3 days References: [1] http://lists.freebsd.org/pipermail/svn-src-all/2014-August/090470.html
| * Update and clarify comments. Remove the useless counter for impossible, butkib2014-09-212-12/+13
| | | | | | | | | | | | | | seen in wild situation (on buggy hypervisors). In collaboration with: bde MFC after: 1 week
| * Add some more KTR events to help debugging.neel2014-09-202-1/+8
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| * MSR_KGSBASE is no longer saved and restored from the guest MSR save area. Thisneel2014-09-201-7/+0
| | | | | | | | | | | | | | | | behavior was changed in r271888 so update the comment block to reflect this. MSR_KGSBASE is accessible from the guest without triggering a VM-exit. The permission bitmap for MSR_KGSBASE is modified by vmx_msr_guest_init() so get rid of redundant code in vmx_vminit().
| * Restructure the MSR handling so it is entirely handled by processor-specificneel2014-09-2010-372/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | code. There are only a handful of MSRs common between the two so there isn't too much duplicate functionality. The VT-x code has the following types of MSRs: - MSRs that are unconditionally saved/restored on every guest/host context switch (e.g., MSR_GSBASE). - MSRs that are restored to guest values on entry to vmx_run() and saved before returning. This is an optimization for MSRs that are not used in host kernel context (e.g., MSR_KGSBASE). - MSRs that are emulated and every access by the guest causes a trap into the hypervisor (e.g., MSR_IA32_MISC_ENABLE). Reviewed by: grehan
* | Simplify register state save and restore across a VMRUN:neel2014-09-274-145/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Host registers are now stored on the stack instead of a per-cpu host context. - Host %FS and %GS selectors are not saved and restored across VMRUN. - Restoring the %FS/%GS selectors was futile anyways since that only updates the low 32 bits of base address in the hidden descriptor state. - GS.base is properly updated via the MSR_GSBASE on return from svm_launch(). - FS.base is not used while inside the kernel so it can be safely ignored. - Add function prologue/epilogue so svm_launch() can be traced with Dtrace's FBT entry/exit probes. They also serve to save/restore the host %rbp across VMRUN. Reviewed by: grehan Discussed with: Anish Gupta (akgupt3@gmail.com)
* | Allow more VMCB fields to be cached:neel2014-09-215-223/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | - CR2 - CR0, CR3, CR4 and EFER - GDT/IDT base/limit fields - CS/DS/ES/SS selector/base/limit/attrib fields The caching can be further restricted via the tunable 'hw.vmm.svm.vmcb_clean'. Restructure the code such that the fields above are only modified in a single place. This makes it easy to invalidate the VMCB cache when any of these fields is modified.
* | Get rid of unused stat VMM_HLT_IGNORED.neel2014-09-212-2/+0
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* | The memory type bits (PAT, PCD, PWT) associated with a nested PTE or PDEneel2014-09-211-14/+5
| | | | | | | | are identical to the traditional x86 page tables.
* | IFC r271888.neel2014-09-2013-405/+433
| | | | | | | | Restructure MSR emulation so it is all done in processor-specific code.
* | IFC @r271887neel2014-09-2010-43/+139
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| * - Use NULL instead of 0 for fpcurthread.kib2014-09-181-13/+16
| | | | | | | | | | | | | | | | | | - Note the quirk with the interrupt enabled state of the dna handler. - Use just panic() instead of printf() and panic(). Print tid instead of pid, the fpu state is per-thread. Sponsored by: The FreeBSD Foundation MFC after: 1 week
| * Re-gen after r271743 implementing most ofbz2014-09-185-19/+109
| | | | | | | | | | | | | | timer_{create,settime,gettime,getoverrun,delete}. MFC after: 3 days Sponsored by: DARPA, AFRL
| * Implement most of timer_{create,settime,gettime,getoverrun,delete}bz2014-09-183-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | for amd64/linux32. Fix the entirely bogus (untested) version from r161310 for i386/linux using the same shared code in compat/linux. It is unclear to me if we could support more clock mappings but the current set allows me to successfully run commercial 32bit linux software under linuxolator on amd64. Reviewed by: jhb Differential Revision: D784 MFC after: 3 days Sponsored by: DARPA, AFRL
| * Presence of any VM_PROT bits in the permission argument on x86 implieskib2014-09-171-1/+2
| | | | | | | | | | | | | | | | | | that the entry is readable and valid. Reported by: markj Submitted by: alc Tested by: pho (previous version), markj MFC after: 3 days
* | IFC @r271694neel2014-09-1723-1078/+471
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| * Add a sysctl to export the EFI memory map along with a handler in thejhb2014-09-131-0/+20
| | | | | | | | | | | | | | | | sysctl(8) binary to format it. Reviewed by: emaste MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D771
| * Optimize the common case of injecting an interrupt into a vcpu after a HLTneel2014-09-123-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | by explicitly moving it out of the interrupt shadow. The hypervisor is done "executing" the HLT and by definition this moves the vcpu out of the 1-instruction interrupt shadow. Prior to this change the interrupt would be held pending because the VMCS guest-interruptibility-state would indicate that "blocking by STI" was in effect. This resulted in an unnecessary round trip into the guest before the pending interrupt could be injected. Reviewed by: grehan
| * MFamd64: Use initializecpu() to set various model-specific registers onjhb2014-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AP startup and AP resume (it was already used for BSP startup and BSP resume). - Split code to do one-time probing of cache properties out of initializecpu() and into initializecpucache(). This is called once on the BSP during boot. - Move enable_sse() into initializecpu(). - Call initializecpu() for AP startup instead of enable_sse() and manually frobbing MSR_EFER to enable PG_NX. - Call initializecpu() when an AP resumes. In theory this will now properly re-enable PG_NX in MSR_EFER when resuming a PAE kernel on APs.
| * Create a separate structure for per-CPU state saved across suspend andjhb2014-09-066-38/+29
| | | | | | | | | | | | | | | | | | resume that is a superset of a pcb. Move the FPU state out of the pcb and into this new structure. As part of this, move the FPU resume code on amd64 into a C function. This allows resumectx() to still operate only on a pcb and more closely mirrors the i386 code. Reviewed by: kib (earlier version)
| * Apply known workarounds for modern MacBooks.pfg2014-09-051-0/+2
| | | | | | | | | | | | | | | | | | | | The legacy USB circuit tends to give trouble on MacBook. While the original report covered MacBook, extend the fix preemptively for the newer MacBookPro too. PR: 191693 Reviewed by: emaste MFC after: 5 days
| * Add mrsas(4) to GENERIC for i386 and amd64.markj2014-09-041-0/+1
| | | | | | | | | | Approved by: ambrisko, kadesai MFC after: 3 days
| * Merge the amd64 and i386 identcpu.c into a single x86 implementation.jhb2014-09-041-916/+0
| | | | | | | | | | This brings the structured extended features mask and VT-x reporting to i386 and Intel cache and TLB info (under bootverbose) to amd64.
| * Remove trailing whitespace.jhb2014-09-041-8/+8
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| * - Move prototypes for various functions into out of C files and intojhb2014-09-043-11/+3
| | | | | | | | | | | | | | | | | | | | <machine/md_var.h>. - Move some CPU-related variables out of i386/i386/identcpu.c to initcpu.c to match amd64. - Move the declaration of has_f00f_hack out of identcpu.c to machdep.c. - Remove a misleading comment from i386/i386/initcpu.c (locore zeros the BSS before it calls identify_cpu()) and remove explicit zero assignments to reduce the diff with amd64.
| * Update a comment to reflect the changes in r213408.alc2014-09-021-1/+1
| | | | | | | | MFC after: 5 days
| * The "SUB" instruction used in getcc() actually does 'x -= y' so use theneel2014-08-301-42/+66
| | | | | | | | | | | | | | | | | | | | | | | | proper constraint for 'x'. The "+r" constraint indicates that 'x' is an input and output register operand. While here generate code for different variants of getcc() using a macro GETCC(sz) where 'sz' indicates the operand size. Update the status bits in %rflags when emulating AND and OR opcodes. Reviewed by: grehan
| * Minor space/tab cleanups.pfg2014-08-301-5/+5
| | | | | | | | | | | | | | | | | | Most of them were ripped from the GSoC 2104 SMAP + kpatch project. This is only a cosmetic change. Taken from: Oliver Pinter (op@) MFC after: 5 days
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