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* Don't advertise the Instruction Based Sampling feature because it requiresneel2014-10-171-0/+5
* Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 inneel2014-10-171-0/+8
* Use the correct fault type (VM_PROT_EXECUTE) for an instruction fetch.neel2014-10-161-0/+2
* Fix topology enumeration issues exposed by AMD Bulldozer Family 15h processor.neel2014-10-161-2/+24
* Actually hide the SVM capability by clearing CPUID.80000001H:ECX[bit 3]neel2014-10-151-2/+6
* Remove extraneous comments.neel2014-10-111-22/+6
* Get rid of unused headers.neel2014-10-113-193/+126
* Get rid of unused forward declaration of 'struct svm_softc'.neel2014-10-111-2/+1
* style(9) fixes.neel2014-10-111-8/+1
* Use a consistent style for messages emitted when the module is loaded.neel2014-10-111-28/+24
* IFC @r272887neel2014-10-108-13/+133
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| * Support Intel-specific MSRs that are accessed when booting up a linux in bhyve:neel2014-10-091-0/+100
| * Pass up the error status of minidumpsys() to its callers.markj2014-10-082-3/+4
| * Add an argument to the x86 pmap_invalidate_cache_range() to requestkib2014-10-082-10/+15
| * Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT'.neel2014-10-063-0/+14
* | Fix bhyvectl so it works correctly on AMD/SVM hosts. Also, add command lineneel2014-10-102-0/+88
* | IFC @r272481neel2014-10-053-68/+30
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| * Get rid of code that dealt with the hardware not being able to save/restoreneel2014-10-021-55/+17
| * msi: add Xen MSI implementationroyger2014-09-301-0/+1
| * Allow the PIC's IMR register to be read before ICW initialisation.grehan2014-09-271-13/+12
* | IFC @r272185neel2014-09-278-23/+32
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| * ddb: allow specifying the exact address of the symtab and strtabroyger2014-09-251-3/+5
| * As per [1] Intel only supports this driver on 64bit platforms.bz2014-09-232-0/+6
| * Update and clarify comments. Remove the useless counter for impossible, butkib2014-09-212-12/+13
| * Add some more KTR events to help debugging.neel2014-09-202-1/+8
| * MSR_KGSBASE is no longer saved and restored from the guest MSR save area. Thisneel2014-09-201-7/+0
| * Restructure the MSR handling so it is entirely handled by processor-specificneel2014-09-2010-372/+201
* | Simplify register state save and restore across a VMRUN:neel2014-09-274-145/+85
* | Allow more VMCB fields to be cached:neel2014-09-215-223/+245
* | Get rid of unused stat VMM_HLT_IGNORED.neel2014-09-212-2/+0
* | The memory type bits (PAT, PCD, PWT) associated with a nested PTE or PDEneel2014-09-211-14/+5
* | IFC r271888.neel2014-09-2013-405/+433
* | IFC @r271887neel2014-09-2010-43/+139
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| * - Use NULL instead of 0 for fpcurthread.kib2014-09-181-13/+16
| * Re-gen after r271743 implementing most ofbz2014-09-185-19/+109
| * Implement most of timer_{create,settime,gettime,getoverrun,delete}bz2014-09-183-10/+12
| * Presence of any VM_PROT bits in the permission argument on x86 implieskib2014-09-171-1/+2
* | IFC @r271694neel2014-09-1723-1078/+471
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| * Add a sysctl to export the EFI memory map along with a handler in thejhb2014-09-131-0/+20
| * Optimize the common case of injecting an interrupt into a vcpu after a HLTneel2014-09-123-1/+64
| * MFamd64: Use initializecpu() to set various model-specific registers onjhb2014-09-101-1/+1
| * Create a separate structure for per-CPU state saved across suspend andjhb2014-09-066-38/+29
| * Apply known workarounds for modern MacBooks.pfg2014-09-051-0/+2
| * Add mrsas(4) to GENERIC for i386 and amd64.markj2014-09-041-0/+1
| * Merge the amd64 and i386 identcpu.c into a single x86 implementation.jhb2014-09-041-916/+0
| * Remove trailing whitespace.jhb2014-09-041-8/+8
| * - Move prototypes for various functions into out of C files and intojhb2014-09-043-11/+3
| * Update a comment to reflect the changes in r213408.alc2014-09-021-1/+1
| * The "SUB" instruction used in getcc() actually does 'x -= y' so use theneel2014-08-301-42/+66
| * Minor space/tab cleanups.pfg2014-08-301-5/+5
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