diff options
Diffstat (limited to 'test/CodeGen')
25 files changed, 596 insertions, 34 deletions
diff --git a/test/CodeGen/2004-06-17-UnorderedCompares.c b/test/CodeGen/2004-06-17-UnorderedCompares.c index 2c80180..38eafd0 100644 --- a/test/CodeGen/2004-06-17-UnorderedCompares.c +++ b/test/CodeGen/2004-06-17-UnorderedCompares.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -std=c99 %s -emit-llvm -o - | FileCheck %s // CHECK: @Test -// CHECK-NOT: call +// CHECK-NOT: call{{ }} _Bool A, B, C, D, E, F; void TestF(float X, float Y) { diff --git a/test/CodeGen/address-safety-attr-kasan.cpp b/test/CodeGen/address-safety-attr-kasan.cpp new file mode 100644 index 0000000..c84ba88 --- /dev/null +++ b/test/CodeGen/address-safety-attr-kasan.cpp @@ -0,0 +1,38 @@ +// Make sure the sanitize_address attribute is emitted when using both ASan and KASan. +// Also document that __attribute__((no_sanitize_address)) doesn't disable KASan instrumentation. + +/// RUN: %clang_cc1 -triple i386-unknown-linux -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NOASAN %s +/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-ASAN %s +/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=kernel-address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-KASAN %s + +int HasSanitizeAddress() { + return 1; +} +// CHECK-NOASAN: {{Function Attrs: nounwind$}} +// CHECK-ASAN: Function Attrs: nounwind sanitize_address +// CHECK-KASAN: Function Attrs: nounwind sanitize_address + +__attribute__((no_sanitize("address"))) +int NoSanitizeQuoteAddress() { + return 0; +} +// CHECK-NOASAN: {{Function Attrs: nounwind$}} +// CHECK-ASAN: {{Function Attrs: nounwind$}} +// CHECK-KASAN: {{Function Attrs: nounwind sanitize_address$}} + +__attribute__((no_sanitize_address)) +int NoSanitizeAddress() { + return 0; +} +// CHECK-NOASAN: {{Function Attrs: nounwind$}} +// CHECK-ASAN: {{Function Attrs: nounwind$}} +// CHECK-KASAN: {{Function Attrs: nounwind sanitize_address$}} + +__attribute__((no_sanitize("kernel-address"))) +int NoSanitizeKernelAddress() { + return 0; +} + +// CHECK-NOASAN: {{Function Attrs: nounwind$}} +// CHECK-ASAN: {{Function Attrs: nounwind sanitize_address$}} +// CHECK-KASAN: {{Function Attrs: nounwind$}} diff --git a/test/CodeGen/arm-interrupt-attr.c b/test/CodeGen/arm-interrupt-attr.c index 73f1cfe..fcbf1c7 100644 --- a/test/CodeGen/arm-interrupt-attr.c +++ b/test/CodeGen/arm-interrupt-attr.c @@ -28,11 +28,11 @@ __attribute__((interrupt("UNDEF"))) void test_undef_interrupt() { // CHECK: define arm_aapcscc void @test_undef_interrupt() [[UNDEF_ATTR:#[0-9]+]] } -// CHECK: attributes [[GENERIC_ATTR]] = { nounwind alignstack=8 {{"interrupt"[^=]}} -// CHECK: attributes [[IRQ_ATTR]] = { nounwind alignstack=8 "interrupt"="IRQ" -// CHECK: attributes [[FIQ_ATTR]] = { nounwind alignstack=8 "interrupt"="FIQ" -// CHECK: attributes [[SWI_ATTR]] = { nounwind alignstack=8 "interrupt"="SWI" -// CHECK: attributes [[ABORT_ATTR]] = { nounwind alignstack=8 "interrupt"="ABORT" -// CHECK: attributes [[UNDEF_ATTR]] = { nounwind alignstack=8 "interrupt"="UNDEF" - -// CHECK-APCS: attributes [[GENERIC_ATTR]] = { nounwind "interrupt" +// CHECK: attributes [[GENERIC_ATTR]] = { {{.*}} {{"interrupt"[^=]}} +// CHECK: attributes [[IRQ_ATTR]] = { {{.*}} "interrupt"="IRQ" +// CHECK: attributes [[FIQ_ATTR]] = { {{.*}} "interrupt"="FIQ" +// CHECK: attributes [[SWI_ATTR]] = { {{.*}} "interrupt"="SWI" +// CHECK: attributes [[ABORT_ATTR]] = { {{.*}} "interrupt"="ABORT" +// CHECK: attributes [[UNDEF_ATTR]] = { {{.*}} "interrupt"="UNDEF" + +// CHECK-APCS: attributes [[GENERIC_ATTR]] = { {{.*}} "interrupt" diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c index 5b02450..a2eb900 100644 --- a/test/CodeGen/arm_acle.c +++ b/test/CodeGen/arm_acle.c @@ -336,3 +336,69 @@ uint32_t test_crc32cw(uint32_t a, uint32_t b) { uint32_t test_crc32cd(uint32_t a, uint64_t b) { return __crc32cd(a, b); } + +/* 10.1 Special register intrinsics */ +// ARM-LABEL: test_rsr +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]]) +uint32_t test_rsr() { +#ifdef __ARM_32BIT_STATE + return __arm_rsr("cp1:2:c3:c4:5"); +#else + return __arm_rsr("1:2:3:4:5"); +#endif +} + +// ARM-LABEL: test_rsr64 +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]]) +uint64_t test_rsr64() { +#ifdef __ARM_32BIT_STATE + return __arm_rsr64("cp1:2:c3"); +#else + return __arm_rsr64("1:2:3:4:5"); +#endif +} + +// ARM-LABEL: test_rsrp +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]]) +void *test_rsrp() { + return __arm_rsrp("sysreg"); +} + +// ARM-LABEL: test_wsr +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}}) +void test_wsr(uint32_t v) { +#ifdef __ARM_32BIT_STATE + __arm_wsr("cp1:2:c3:c4:5", v); +#else + __arm_wsr("1:2:3:4:5", v); +#endif +} + +// ARM-LABEL: test_wsr64 +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}}) +void test_wsr64(uint64_t v) { +#ifdef __ARM_32BIT_STATE + __arm_wsr64("cp1:2:c3", v); +#else + __arm_wsr64("1:2:3:4:5", v); +#endif +} + +// ARM-LABEL: test_wsrp +// AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}}) +void test_wsrp(void *v) { + __arm_wsrp("sysreg", v); +} + +// AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"} +// AArch32: ![[M3]] = !{!"cp1:2:c3"} +// AArch32: ![[M4]] = !{!"sysreg"} + +// AArch64: ![[M0]] = !{!"1:2:3:4:5"} +// AArch64: ![[M1]] = !{!"sysreg"} diff --git a/test/CodeGen/arm_neon_intrinsics.c b/test/CodeGen/arm_neon_intrinsics.c index 756e3b4..d92c32c 100644 --- a/test/CodeGen/arm_neon_intrinsics.c +++ b/test/CodeGen/arm_neon_intrinsics.c @@ -2399,6 +2399,12 @@ float32_t test_vget_lane_f32(float32x2_t a) { return vget_lane_f32(a, 1); } +// CHECK-LABEL: test_vget_lane_f16 +// CHECK: vmov +float32_t test_vget_lane_f16(float16x4_t a) { + return vget_lane_f16(a, 1); +} + // CHECK-LABEL: test_vgetq_lane_u8 // CHECK: vmov uint8_t test_vgetq_lane_u8(uint8x16_t a) { @@ -2453,6 +2459,12 @@ float32_t test_vgetq_lane_f32(float32x4_t a) { return vgetq_lane_f32(a, 3); } +// CHECK-LABEL: test_vgetq_lane_f16 +// CHECK: vmov +float32_t test_vgetq_lane_f16(float16x8_t a) { + return vgetq_lane_f16(a, 3); +} + // CHECK-LABEL: test_vget_lane_s64 // The optimizer is able to remove all moves now. int64_t test_vget_lane_s64(int64x1_t a) { @@ -9157,6 +9169,12 @@ float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) { return vset_lane_f32(a, b, 1); } +// CHECK-LABEL: test_vset_lane_f16 +// CHECK: mov +float16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) { + return vset_lane_f16(*a, b, 1); +} + // CHECK-LABEL: test_vsetq_lane_u8 // CHECK: vmov uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) { @@ -9211,6 +9229,12 @@ float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) { return vsetq_lane_f32(a, b, 3); } +// CHECK-LABEL: test_vsetq_lane_f16 +// CHECK: vmov +float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { + return vsetq_lane_f16(*a, b, 3); +} + // CHECK-LABEL: test_vset_lane_s64 // The optimizer is able to get rid of all moves now. int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) { diff --git a/test/CodeGen/attr-disable-tail-calls.c b/test/CodeGen/attr-disable-tail-calls.c new file mode 100644 index 0000000..8141349 --- /dev/null +++ b/test/CodeGen/attr-disable-tail-calls.c @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -triple x86_64-apple-macosx10.7.0 %s -emit-llvm -mdisable-tail-calls -o - | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLE +// RUN: %clang_cc1 -triple x86_64-apple-macosx10.7.0 %s -emit-llvm -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLE + +// CHECK: define i32 @f1() [[ATTR:#[0-9]+]] { + +int f1() { + return 0; +} + +// DISABLE: attributes [[ATTR]] = { {{.*}} "disable-tail-calls"="true" {{.*}} } +// ENABLE: attributes [[ATTR]] = { {{.*}} "disable-tail-calls"="false" {{.*}} } diff --git a/test/CodeGen/attr-mode-vector-types.c b/test/CodeGen/attr-mode-vector-types.c new file mode 100644 index 0000000..3c028fb --- /dev/null +++ b/test/CodeGen/attr-mode-vector-types.c @@ -0,0 +1,41 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -emit-llvm -o - | FileCheck %s + +typedef int __attribute__((mode(byte))) __attribute__((vector_size(4))) vec_t1; +typedef int __attribute__((mode(QI))) __attribute__((vector_size(8))) vec_t2; +typedef int __attribute__((mode(SI))) __attribute__((vector_size(16))) vec_t3; +typedef int __attribute__((mode(DI))) __attribute__((vector_size(64)))vec_t4; +typedef float __attribute__((mode(SF))) __attribute__((vector_size(128))) vec_t5; +typedef float __attribute__((mode(DF))) __attribute__((vector_size(256))) vec_t6; + +void check() { + // CHECK: alloca <4 x i8> + vec_t1 v1; + // CHECK: alloca <8 x i8> + vec_t2 v2; + // CHECK: alloca <4 x i32> + vec_t3 v3; + // CHECK: alloca <8 x i64> + vec_t4 v4; + // CHECK: alloca <32 x float> + vec_t5 v5; + // CHECK: alloca <32 x double> + vec_t6 v6; +} + +// CHECK: ret i32 4 +int check_size1() { return sizeof(vec_t1); } + +// CHECK: ret i32 8 +int check_size2() { return sizeof(vec_t2); } + +// CHECK: ret i32 16 +int check_size3() { return sizeof(vec_t3); } + +// CHECK: ret i32 64 +int check_size4() { return sizeof(vec_t4); } + +// CHECK: ret i32 128 +int check_size5() { return sizeof(vec_t5); } + +// CHECK: ret i32 256 +int check_size6() { return sizeof(vec_t6); } diff --git a/test/CodeGen/attr-target.c b/test/CodeGen/attr-target.c new file mode 100644 index 0000000..8c0f335 --- /dev/null +++ b/test/CodeGen/attr-target.c @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s -o - | FileCheck %s + +int baz(int a) { return 4; } + +int __attribute__((target("avx,sse4.2,arch=ivybridge"))) foo(int a) { return 4; } + +int __attribute__((target("tune=sandybridge"))) walrus(int a) { return 4; } +int __attribute__((target("fpmath=387"))) koala(int a) { return 4; } + +int __attribute__((target("mno-sse2"))) echidna(int a) { return 4; } + +int bar(int a) { return baz(a) + foo(a); } + +// Check that we emit the additional subtarget and cpu features for foo and not for baz or bar. +// CHECK: baz{{.*}} #0 +// CHECK: foo{{.*}} #1 +// We ignore the tune attribute so walrus should be identical to baz and bar. +// CHECK: walrus{{.*}} #0 +// We're currently ignoring the fpmath attribute so koala should be identical to baz and bar. +// CHECK: koala{{.*}} #0 +// CHECK: echidna{{.*}} #2 +// CHECK: bar{{.*}} #0 +// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2" +// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+sse,+sse2,+avx,+sse4.2" +// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2,-sse2" diff --git a/test/CodeGen/bounds-checking.c b/test/CodeGen/bounds-checking.c index d93cd3e..90b7f0f 100644 --- a/test/CodeGen/bounds-checking.c +++ b/test/CodeGen/bounds-checking.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fsanitize=local-bounds -emit-llvm -triple x86_64-apple-darwin10 %s -o - | FileCheck %s -// RUN: %clang_cc1 -fsanitize=array-bounds -O -fsanitize-undefined-trap-on-error -emit-llvm -triple x86_64-apple-darwin10 -DNO_DYNAMIC %s -o - | FileCheck %s +// RUN: %clang_cc1 -fsanitize=array-bounds -O -fsanitize-trap=array-bounds -emit-llvm -triple x86_64-apple-darwin10 -DNO_DYNAMIC %s -o - | FileCheck %s // CHECK-LABEL: @f double f(int b, int i) { diff --git a/test/CodeGen/builtins-arm.c b/test/CodeGen/builtins-arm.c index 9f3ed9a..2b81856 100644 --- a/test/CodeGen/builtins-arm.c +++ b/test/CodeGen/builtins-arm.c @@ -84,3 +84,42 @@ void prefetch(int i) { __builtin_arm_prefetch(&i, 1, 0); // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 0) } + +unsigned rsr() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !7) + // CHECK-NEXT: ret i32 [[V0]] + return __builtin_arm_rsr("cp1:2:c3:c4:5"); +} + +unsigned long long rsr64() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !8) + // CHECK-NEXT: ret i64 [[V0]] + return __builtin_arm_rsr64("cp1:2:c3"); +} + +void *rsrp() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !9) + // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8* + // CHECK-NEXT: ret i8* [[V1]] + return __builtin_arm_rsrp("sysreg"); +} + +void wsr(unsigned v) { + // CHECK: call void @llvm.write_register.i32(metadata !7, i32 %v) + __builtin_arm_wsr("cp1:2:c3:c4:5", v); +} + +void wsr64(unsigned long long v) { + // CHECK: call void @llvm.write_register.i64(metadata !8, i64 %v) + __builtin_arm_wsr64("cp1:2:c3", v); +} + +void wsrp(void *v) { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32 + // CHECK-NEXT: call void @llvm.write_register.i32(metadata !9, i32 [[V0]]) + __builtin_arm_wsrp("sysreg", v); +} + +// CHECK: !7 = !{!"cp1:2:c3:c4:5"} +// CHECK: !8 = !{!"cp1:2:c3"} +// CHECK: !9 = !{!"sysreg"} diff --git a/test/CodeGen/builtins-arm64.c b/test/CodeGen/builtins-arm64.c index cc1f547..f2c1c54 100644 --- a/test/CodeGen/builtins-arm64.c +++ b/test/CodeGen/builtins-arm64.c @@ -43,3 +43,39 @@ void prefetch() { __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) } + +unsigned rsr() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + // CHECK-NEXT: trunc i64 [[V0]] to i32 + return __builtin_arm_rsr("1:2:3:4:5"); +} + +unsigned long rsr64() { + // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + return __builtin_arm_rsr64("1:2:3:4:5"); +} + +void *rsrp() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + // CHECK-NEXT: inttoptr i64 [[V0]] to i8* + return __builtin_arm_rsrp("1:2:3:4:5"); +} + +void wsr(unsigned v) { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64 + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) + __builtin_arm_wsr("1:2:3:4:5", v); +} + +void wsr64(unsigned long v) { + // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v) + __builtin_arm_wsr64("1:2:3:4:5", v); +} + +void wsrp(void *v) { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64 + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) + __builtin_arm_wsrp("1:2:3:4:5", v); +} + +// CHECK: ![[M0]] = !{!"1:2:3:4:5"} diff --git a/test/CodeGen/builtins-ppc-p8vector.c b/test/CodeGen/builtins-ppc-p8vector.c index f74bbad..ac40790 100644 --- a/test/CodeGen/builtins-ppc-p8vector.c +++ b/test/CodeGen/builtins-ppc-p8vector.c @@ -3,6 +3,8 @@ // RUN: %clang_cc1 -faltivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE // RUN: not %clang_cc1 -faltivec -triple powerpc64-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC +vector signed char vsc = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5 }; +vector unsigned char vuc = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5 }; vector int vi = { -1, 2, -3, 4 }; vector unsigned int vui = { 1, 2, 3, 4 }; vector bool int vbi = {0, -1, -1, 0}; @@ -11,6 +13,8 @@ vector signed long long vsll = { 1, 2 }; vector unsigned long long vull = { 1, 2 }; int res_i; +vector signed char res_vsc; +vector unsigned char res_vuc; vector int res_vi; vector unsigned int res_vui; vector bool int res_vbi; @@ -737,4 +741,23 @@ void test1() { // CHECK: @llvm.ppc.altivec.vminud // CHECK-LE: @llvm.ppc.altivec.vminud + /* vec_vbpermq */ + res_vsll = vec_vbpermq(vsc, vsc); +// CHECK: llvm.ppc.altivec.vbpermq +// CHECK-LE: llvm.ppc.altivec.vbpermq + + res_vull = vec_vbpermq(vuc, vuc); +// CHECK: llvm.ppc.altivec.vbpermq +// CHECK-LE: llvm.ppc.altivec.vbpermq +// CHECK-PPC: warning: implicit declaration of function 'vec_vbpermq' + + /* vec_vgbbd */ + res_vsc = vec_vgbbd(vsc); +// CHECK: llvm.ppc.altivec.vgbbd +// CHECK-LE: llvm.ppc.altivec.vgbbd + + res_vuc = vec_vgbbd(vuc); +// CHECK: llvm.ppc.altivec.vgbbd +// CHECK-LE: llvm.ppc.altivec.vgbbd +// CHECK-PPC: warning: implicit declaration of function 'vec_vgbbd' } diff --git a/test/CodeGen/catch-undef-behavior.c b/test/CodeGen/catch-undef-behavior.c index 6695419..7875536 100644 --- a/test/CodeGen/catch-undef-behavior.c +++ b/test/CodeGen/catch-undef-behavior.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-UBSAN -// RUN: %clang_cc1 -fsanitize-undefined-trap-on-error -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP +// RUN: %clang_cc1 -fsanitize-trap=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP // RUN: %clang_cc1 -fsanitize=null -fsanitize-recover=null -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-NULL // RUN: %clang_cc1 -fsanitize=signed-integer-overflow -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-OVERFLOW // REQUIRES: asserts diff --git a/test/CodeGen/cleanup-destslot-simple.c b/test/CodeGen/cleanup-destslot-simple.c index bae97c8..b8328af 100644 --- a/test/CodeGen/cleanup-destslot-simple.c +++ b/test/CodeGen/cleanup-destslot-simple.c @@ -13,7 +13,9 @@ int test() { return *p; // CHECK: [[X:%.*]] = alloca i32 // CHECK: [[P:%.*]] = alloca i32* -// LIFETIME: call void @llvm.lifetime.start(i64 4, i8* %{{.*}}) -// LIFETIME: call void @llvm.lifetime.start(i64 8, i8* %{{.*}}) +// LIFETIME: call void @llvm.lifetime.start(i64 4, i8* %{{.*}}){{( #[0-9]+)?}}, !dbg +// LIFETIME: call void @llvm.lifetime.start(i64 8, i8* %{{.*}}){{( #[0-9]+)?}}, !dbg // CHECK-NOT: store i32 %{{.*}}, i32* %cleanup.dest.slot +// LIFETIME: call void @llvm.lifetime.end(i64 8, {{.*}}){{( #[0-9]+)?}}, !dbg +// LIFETIME: call void @llvm.lifetime.end(i64 4, {{.*}}){{( #[0-9]+)?}}, !dbg } diff --git a/test/CodeGen/exceptions-seh.c b/test/CodeGen/exceptions-seh.c index d8135e8..1b77ad6 100644 --- a/test/CodeGen/exceptions-seh.c +++ b/test/CodeGen/exceptions-seh.c @@ -19,12 +19,12 @@ int safe_div(int numerator, int denominator, int *res) { *res = myres; return success; } -// CHECK-LABEL: define i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) +// CHECK-LABEL: define i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) {{.*}} personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) #[[NOINLINE:[0-9]+]] // CHECK: to label %{{.*}} unwind label %[[lpad:[^ ]*]] // // CHECK: [[lpad]] -// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK: landingpad { i8*, i32 } // CHECK-NEXT: catch i8* null // CHECK-NOT: br i1 // CHECK: br label %[[except:[^ ]*]] @@ -46,7 +46,7 @@ int filter_expr_capture(void) { return r; } -// CHECK-LABEL: define i32 @filter_expr_capture() +// CHECK-LABEL: define i32 @filter_expr_capture() {{.*}} personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: call void (...) @llvm.frameescape(i32* %[[r:[^ ,]*]]) // CHECK: store i32 42, i32* %[[r]] // CHECK: invoke void @j() #[[NOINLINE]] @@ -77,7 +77,7 @@ int nested_try(void) { } return r; } -// CHECK-LABEL: define i32 @nested_try() +// CHECK-LABEL: define i32 @nested_try() {{.*}} personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: store i32 42, i32* %[[r:[^ ,]*]] // CHECK: invoke void @j() #[[NOINLINE]] // CHECK: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] @@ -87,7 +87,7 @@ int nested_try(void) { // CHECK: br label %[[inner_try_cont:[^ ]*]] // // CHECK: [[lpad]] -// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK: landingpad { i8*, i32 } // CHECK: catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$1@0@nested_try@@" to i8*) // CHECK: catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@nested_try@@" to i8*) // CHECK: store i8* %{{.*}}, i8** %[[ehptr_slot:[^ ]*]] @@ -125,7 +125,7 @@ void basic_finally(void) { --g; } } -// CHECK-LABEL: define void @basic_finally() +// CHECK-LABEL: define void @basic_finally() {{.*}} personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: load i32, i32* @g // CHECK: add i32 %{{.*}}, 1 // CHECK: store i32 %{{.*}}, i32* @g @@ -139,7 +139,7 @@ void basic_finally(void) { // CHECK: ret void // // CHECK: [[lpad]] -// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK: landingpad { i8*, i32 } // CHECK-NEXT: cleanup // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) // CHECK: call void @"\01?fin$0@0@basic_finally@@"(i8 1, i8* %[[fp]]) diff --git a/test/CodeGen/exceptions.c b/test/CodeGen/exceptions.c index ae0af4d..039ec84 100644 --- a/test/CodeGen/exceptions.c +++ b/test/CodeGen/exceptions.c @@ -5,8 +5,8 @@ void test1() { extern void test1_helper(void (^)(int)); - // CHECK-LABEL: define void @test1() - // CHECK-ARM-LABEL: define arm_aapcscc void @test1() + // CHECK-LABEL: define void @test1() {{.*}} personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) + // CHECK-ARM-LABEL: define arm_aapcscc void @test1() {{.*}} personality i8* bitcast (i32 (...)* @__gcc_personality_sj0 to i8*) __block int x = 10; @@ -14,9 +14,9 @@ void test1() { // CHECK-ARM: invoke arm_aapcscc void @test1_helper( test1_helper(^(int v) { x = v; }); - // CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) + // CHECK: landingpad { i8*, i32 } // CHECK-NEXT: cleanup - // CHECK-ARM: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gcc_personality_sj0 to i8*) + // CHECK-ARM: landingpad { i8*, i32 } // CHECK-ARM-NEXT: cleanup } diff --git a/test/CodeGen/inline-asm-immediate-ubsan.c b/test/CodeGen/inline-asm-immediate-ubsan.c new file mode 100644 index 0000000..77d5e4f --- /dev/null +++ b/test/CodeGen/inline-asm-immediate-ubsan.c @@ -0,0 +1,30 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s \ +// RUN: -fsanitize=signed-integer-overflow \ +// RUN: | FileCheck %s --check-prefix=CHECK + +// Verify we emit constants for "immediate" inline assembly arguments. +// Emitting a scalar expression can make the immediate be generated as +// overflow intrinsics, if the overflow sanitizer is enabled. + +// Check both 'i' and 'I': +// - 'i' accepts symbolic constants. +// - 'I' doesn't, and is really an immediate-required constraint. + +// See also PR23517. + +// CHECK-LABEL: @test_inlineasm_i +// CHECK: call void asm sideeffect "int $0", "i{{.*}}"(i32 2) +void test_inlineasm_i() { + __asm__ __volatile__("int %0" :: "i"(1 + 1)); +} + +// CHECK-LABEL: @test_inlineasm_I +// CHECK: call void asm sideeffect "int $0", "I{{.*}}"(i32 2) +// CHECK: call void asm sideeffect "int $0", "I{{.*}}"(i32 3) +void test_inlineasm_I() { + __asm__ __volatile__("int %0" :: "I"(1 + 1)); + + // Also check a C non-ICE. + static const int N = 1; + __asm__ __volatile__("int %0" :: "I"(N + 2)); +} diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c index a6f1b71..d98b498 100644 --- a/test/CodeGen/ms-inline-asm.c +++ b/test/CodeGen/ms-inline-asm.c @@ -432,6 +432,8 @@ void t37() { // CHECK: mov eax, $$4294967292 __asm mov eax, ~15 // CHECK: mov eax, $$4294967280 + __asm mov eax, 6 ^ 3 +// CHECK: mov eax, $$5 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"() } diff --git a/test/CodeGen/partial-reinitialization1.c b/test/CodeGen/partial-reinitialization1.c new file mode 100644 index 0000000..6a764b7 --- /dev/null +++ b/test/CodeGen/partial-reinitialization1.c @@ -0,0 +1,74 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -emit-llvm -o - | FileCheck %s + +struct P1 { + struct Q1 { + char a[6]; + char b[6]; + } q; +}; + +// CHECK: { [6 x i8] c"foo\00\00\00", [6 x i8] c"\00x\00\00\00\00" } +struct P1 l1 = { + (struct Q1){ "foo", "bar" }, + .q.b = { "boo" }, + .q.b = { [1] = 'x' } +}; + +// CHECK: { [6 x i8] c"foo\00\00\00", [6 x i8] c"bxo\00\00\00" } +struct P1 l1a = { + (struct Q1){ "foo", "bar" }, + .q.b = { "boo" }, + .q.b[1] = 'x' +}; + + +struct P2 { char x[6]; }; + +// CHECK: { [6 x i8] c"n\00\00\00\00\00" } +struct P2 l2 = { + .x = { [1] = 'o' }, + .x = { [0] = 'n' } +}; + +struct P3 { + struct Q3 { + struct R1 { + int a, b, c; + } r1; + + struct R2 { + int d, e, f; + } r2; + } q; +}; + +// CHECK: @l3 = global %struct.P3 { %struct.Q3 { %struct.R1 { i32 1, i32 2, i32 3 }, %struct.R2 { i32 0, i32 10, i32 0 } } } +struct P3 l3 = { + (struct Q3){ { 1, 2, 3 }, { 4, 5, 6 } }, + .q.r2 = { 7, 8, 9 }, + .q.r2 = { .e = 10 } +}; + +// This bit is taken from Sema/wchar.c so we can avoid the wchar.h include. +typedef __WCHAR_TYPE__ wchar_t; + +struct P4 { + wchar_t x[6]; +}; + +// CHECK: { [6 x i32] [i32 102, i32 111, i32 120, i32 0, i32 0, i32 0] } +struct P4 l4 = { { L"foo" }, .x[2] = L'x' }; + +struct P5 { + int x; + struct Q5 { + int a, b, c; + } q; + int y; +}; + +// A three-pass test +// CHECK: @l5 = global %struct.P5 { i32 1, %struct.Q5 { i32 6, i32 9, i32 8 }, i32 5 } +struct P5 l5 = { 1, { 2, 3, 4 }, 5, + .q = { 6, 7, 8 }, + .q.b = 9 }; diff --git a/test/CodeGen/partial-reinitialization2.c b/test/CodeGen/partial-reinitialization2.c new file mode 100644 index 0000000..c4f6567 --- /dev/null +++ b/test/CodeGen/partial-reinitialization2.c @@ -0,0 +1,108 @@ +// RUN: %clang_cc1 %s -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s + +struct P1 { char x[6]; } g1 = { "foo" }; +struct LP1 { struct P1 p1; }; + +struct P2 { int a, b, c; } g2 = { 1, 2, 3 }; +struct LP2 { struct P2 p2; }; +struct LP2P2 { struct P2 p1, p2; }; +union UP2 { struct P2 p2; }; + +struct LP3 { struct P1 p1[2]; } g3 = { { "dog" }, { "cat" } }; +struct LLP3 { struct LP3 l3; }; +union ULP3 { struct LP3 l3; }; + +// CHECK-LABEL: test1 +void test1(void) +{ + // CHECK: call void @llvm.memcpy{{.*}}%struct.P1, %struct.P1* @g1{{.*}}i64 6, i32 {{[0-9]}}, i1 false) + // CHECK: store i8 120, i8* % + + struct LP1 l = { .p1 = g1, .p1.x[2] = 'x' }; +} + +// CHECK-LABEL: test2 +void test2(void) +{ + // CHECK: call void @llvm.memcpy{{.*}}%struct.P1, %struct.P1* @g1{{.*}}i64 6, i32 {{[0-9]}}, i1 false) + // CHECK: store i8 114, i8* % + + struct LP1 l = { .p1 = g1, .p1.x[1] = 'r' }; +} + +// CHECK-LABEL: test3 +void test3(void) +{ + // CHECK: call void @llvm.memcpy{{.*}}%struct.P2* @g2{{.*}}i64 12, i32 {{[0-9]}}, i1 false) + // CHECK: store i32 10, i32* % + + struct LP2 l = { .p2 = g2, .p2.b = 10 }; +} + +// CHECK-LABEL: get235 +struct P2 get235() +{ + struct P2 p = { 2, 3, 5 }; + return p; +} + +// CHECK-LABEL: get456789 +struct LP2P2 get456789() +{ + struct LP2P2 l = { { 4, 5, 6 }, { 7, 8, 9 } }; + return l; +} + +// CHECK-LABEL: get123 +union UP2 get123() +{ + union UP2 u = { { 1, 2, 3 } }; + return u; +} + +// CHECK-LABEL: test4 +void test4(void) +{ + // CHECK: [[CALL:%[a-z0-9]+]] = call {{.*}}@get123() + // CHECK: store{{.*}}[[CALL]], {{.*}}[[TMP0:%[a-z0-9]+]] + // CHECK: [[TMP1:%[a-z0-9]+]] = bitcast {{.*}}[[TMP0]] + // CHECK: call void @llvm.memcpy{{.*}}[[TMP1]], i64 12, i32 {{[0-9]}}, i1 false) + // CHECK: store i32 100, i32* % + + struct LUP2 { union UP2 up; } var = { get123(), .up.p2.a = 100 }; +} + +// CHECK-LABEL: test5 +void test5(void) +{ + // .l3 = g3 + // CHECK: call void @llvm.memcpy{{.*}}%struct.LP3, %struct.LP3* @g3{{.*}}i64 12, i32 {{[0-9]}}, i1 false) + + // .l3.p1 = { [0] = g1 } implicitly sets [1] to zero + // CHECK: call void @llvm.memcpy{{.*}}%struct.P1, %struct.P1* @g1{{.*}}i64 6, i32 {{[0-9]}}, i1 false) + // CHECK: getelementptr{{.*}}%struct.P1, %struct.P1*{{.*}}i64 1 + // CHECK: call void @llvm.memset{{.*}}i8 0, i64 6, i32 {{[0-9]}}, i1 false) + + // .l3.p1[1].x[1] = 'x' + // CHECK: store i8 120, i8* % + + struct LLP3 var = { .l3 = g3, .l3.p1 = { [0] = g1 }, .l3.p1[1].x[1] = 'x' }; +} + +// CHECK-LABEL: test6 +void test6(void) +{ + // CHECK: [[LP:%[a-z0-9]+]] = getelementptr{{.*}}%struct.LLP2P2, %struct.LLP2P2*{{.*}}, i32 0, i32 0 + // CHECK: call {{.*}}get456789(%struct.LP2P2* {{.*}}[[LP]]) + + // CHECK: [[CALL:%[a-z0-9]+]] = call {{.*}}@get235() + // CHECK: store{{.*}}[[CALL]], {{.*}}[[TMP0:%[a-z0-9]+]] + // CHECK: [[TMP1:%[a-z0-9]+]] = bitcast {{.*}}[[TMP0]] + // CHECK: call void @llvm.memcpy{{.*}}[[TMP1]], i64 12, i32 {{[0-9]}}, i1 false) + + // CHECK: store i32 10, i32* % + + struct LLP2P2 { struct LP2P2 lp; } var = { get456789(), + .lp.p1 = get235(), + .lp.p1.b = 10 }; +} diff --git a/test/CodeGen/safestack-attr.cpp b/test/CodeGen/safestack-attr.cpp new file mode 100644 index 0000000..9d1ed0d --- /dev/null +++ b/test/CodeGen/safestack-attr.cpp @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple x86_64-linux-unknown -emit-llvm -o - %s -fsanitize=safe-stack | FileCheck -check-prefix=SP %s + +__attribute__((no_sanitize("safe-stack"))) +int foo(int *a) { return *a; } + +// SP-NOT: attributes #{{.*}} = { {{.*}}safestack{{.*}} } diff --git a/test/CodeGen/sanitize-trap.c b/test/CodeGen/sanitize-trap.c new file mode 100644 index 0000000..76ac1f0 --- /dev/null +++ b/test/CodeGen/sanitize-trap.c @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero -fsanitize-trap=integer-divide-by-zero | FileCheck %s + +int f(int x, int y) { + // CHECK: %[[B1:.*]] = icmp ne i32 %[[D:.*]], 0 + // CHECK: %[[B2:.*]] = icmp ne i32 %[[N:.*]], -2147483648 + // CHECK: %[[B3:.*]] = icmp ne i32 %[[D]], -1 + // CHECK: %[[B4:.*]] = or i1 %[[B2]], %[[B3]] + // CHECK: br i1 %[[B1]], label %[[L1:[0-9a-z_.]*]], label %[[L2:[0-9a-z_.]*]] + + // CHECK: [[L2]] + // CHECK-NEXT: call void @llvm.trap() + // CHECK-NEXT: unreachable + + // CHECK: [[L1]] + // CHECK-NEXT: br i1 %[[B4]], label %[[L3:[0-9a-z_.]*]], label %[[L4:[0-9a-z_.]*]] + + // CHECK: [[L4]] + // CHECK-NEXT: zext + // CHECK-NEXT: zext + // CHECK-NEXT: __ubsan_handle_divrem_overflow + + // CHECK: [[L3]] + // CHECK-NEXT: sdiv i32 %[[N]], %[[D]] + return x / y; +} diff --git a/test/CodeGen/stack-protector.c b/test/CodeGen/stack-protector.c index 2fb9b2c..8039b60 100644 --- a/test/CodeGen/stack-protector.c +++ b/test/CodeGen/stack-protector.c @@ -6,6 +6,8 @@ // SSPSTRONG: define void @test1(i8* %msg) #0 { // RUN: %clang_cc1 -emit-llvm -o - %s -stack-protector 3 | FileCheck -check-prefix=SSPREQ %s // SSPREQ: define void @test1(i8* %msg) #0 { +// RUN: %clang_cc1 -emit-llvm -o - %s -fsanitize=safe-stack | FileCheck -check-prefix=SAFESTACK %s +// SAFESTACK: define void @test1(i8* %msg) #0 { typedef __SIZE_TYPE__ size_t; @@ -26,3 +28,5 @@ void test1(const char *msg) { // SSPSTRONG: attributes #{{.*}} = { nounwind sspstrong{{.*}} } // SSPREQ: attributes #{{.*}} = { nounwind sspreq{{.*}} } + +// SAFESTACK: attributes #{{.*}} = { nounwind safestack{{.*}} } diff --git a/test/CodeGen/systemz-inline-asm.c b/test/CodeGen/systemz-inline-asm.c index 92ed4bb..7d5a6b2 100644 --- a/test/CodeGen/systemz-inline-asm.c +++ b/test/CodeGen/systemz-inline-asm.c @@ -6,31 +6,31 @@ unsigned long gl; void test_store_m(unsigned int i) { asm("st %1, %0" : "=m" (gi) : "r" (i)); // CHECK-LABEL: define void @test_store_m(i32 zeroext %i) -// CHECK: call void asm "st $1, $0", "=*m,r"(i32* @gi, i32 %i) +// CHECK: call void asm "st $1, $0", "=*m,r"(i32* nonnull @gi, i32 %i) } void test_store_Q(unsigned int i) { asm("st %1, %0" : "=Q" (gi) : "r" (i)); // CHECK-LABEL: define void @test_store_Q(i32 zeroext %i) -// CHECK: call void asm "st $1, $0", "=*Q,r"(i32* @gi, i32 %i) +// CHECK: call void asm "st $1, $0", "=*Q,r"(i32* nonnull @gi, i32 %i) } void test_store_R(unsigned int i) { asm("st %1, %0" : "=R" (gi) : "r" (i)); // CHECK-LABEL: define void @test_store_R(i32 zeroext %i) -// CHECK: call void asm "st $1, $0", "=*R,r"(i32* @gi, i32 %i) +// CHECK: call void asm "st $1, $0", "=*R,r"(i32* nonnull @gi, i32 %i) } void test_store_S(unsigned int i) { asm("st %1, %0" : "=S" (gi) : "r" (i)); // CHECK-LABEL: define void @test_store_S(i32 zeroext %i) -// CHECK: call void asm "st $1, $0", "=*S,r"(i32* @gi, i32 %i) +// CHECK: call void asm "st $1, $0", "=*S,r"(i32* nonnull @gi, i32 %i) } void test_store_T(unsigned int i) { asm("st %1, %0" : "=T" (gi) : "r" (i)); // CHECK-LABEL: define void @test_store_T(i32 zeroext %i) -// CHECK: call void asm "st $1, $0", "=*T,r"(i32* @gi, i32 %i) +// CHECK: call void asm "st $1, $0", "=*T,r"(i32* nonnull @gi, i32 %i) } int test_load_m() { @@ -38,7 +38,7 @@ int test_load_m() { asm("l %0, %1" : "=r" (i) : "m" (gi)); return i; // CHECK-LABEL: define signext i32 @test_load_m() -// CHECK: call i32 asm "l $0, $1", "=r,*m"(i32* @gi) +// CHECK: call i32 asm "l $0, $1", "=r,*m"(i32* nonnull @gi) } int test_load_Q() { @@ -46,7 +46,7 @@ int test_load_Q() { asm("l %0, %1" : "=r" (i) : "Q" (gi)); return i; // CHECK-LABEL: define signext i32 @test_load_Q() -// CHECK: call i32 asm "l $0, $1", "=r,*Q"(i32* @gi) +// CHECK: call i32 asm "l $0, $1", "=r,*Q"(i32* nonnull @gi) } int test_load_R() { @@ -54,7 +54,7 @@ int test_load_R() { asm("l %0, %1" : "=r" (i) : "R" (gi)); return i; // CHECK-LABEL: define signext i32 @test_load_R() -// CHECK: call i32 asm "l $0, $1", "=r,*R"(i32* @gi) +// CHECK: call i32 asm "l $0, $1", "=r,*R"(i32* nonnull @gi) } int test_load_S() { @@ -62,7 +62,7 @@ int test_load_S() { asm("l %0, %1" : "=r" (i) : "S" (gi)); return i; // CHECK-LABEL: define signext i32 @test_load_S() -// CHECK: call i32 asm "l $0, $1", "=r,*S"(i32* @gi) +// CHECK: call i32 asm "l $0, $1", "=r,*S"(i32* nonnull @gi) } int test_load_T() { @@ -70,7 +70,7 @@ int test_load_T() { asm("l %0, %1" : "=r" (i) : "T" (gi)); return i; // CHECK-LABEL: define signext i32 @test_load_T() -// CHECK: call i32 asm "l $0, $1", "=r,*T"(i32* @gi) +// CHECK: call i32 asm "l $0, $1", "=r,*T"(i32* nonnull @gi) } void test_mI(unsigned char *c) { diff --git a/test/CodeGen/target-data.c b/test/CodeGen/target-data.c index d601158..3c3ea04 100644 --- a/test/CodeGen/target-data.c +++ b/test/CodeGen/target-data.c @@ -174,3 +174,11 @@ // RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=SPIR64 // SPIR64: target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" + +// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \ +// RUN: FileCheck %s -check-prefix=BPFEL +// BPFEL: target datalayout = "e-m:e-p:64:64-i64:64-n32:64-S128" + +// RUN: %clang_cc1 -triple bpfeb -o - -emit-llvm %s | \ +// RUN: FileCheck %s -check-prefix=BPFEB +// BPFEB: target datalayout = "E-m:e-p:64:64-i64:64-n32:64-S128" |
