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Diffstat (limited to 'test/CodeGen/builtins-arm64.c')
-rw-r--r-- | test/CodeGen/builtins-arm64.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/CodeGen/builtins-arm64.c b/test/CodeGen/builtins-arm64.c index cc1f547..f2c1c54 100644 --- a/test/CodeGen/builtins-arm64.c +++ b/test/CodeGen/builtins-arm64.c @@ -43,3 +43,39 @@ void prefetch() { __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) } + +unsigned rsr() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + // CHECK-NEXT: trunc i64 [[V0]] to i32 + return __builtin_arm_rsr("1:2:3:4:5"); +} + +unsigned long rsr64() { + // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + return __builtin_arm_rsr64("1:2:3:4:5"); +} + +void *rsrp() { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) + // CHECK-NEXT: inttoptr i64 [[V0]] to i8* + return __builtin_arm_rsrp("1:2:3:4:5"); +} + +void wsr(unsigned v) { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64 + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) + __builtin_arm_wsr("1:2:3:4:5", v); +} + +void wsr64(unsigned long v) { + // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v) + __builtin_arm_wsr64("1:2:3:4:5", v); +} + +void wsrp(void *v) { + // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64 + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) + __builtin_arm_wsrp("1:2:3:4:5", v); +} + +// CHECK: ![[M0]] = !{!"1:2:3:4:5"} |