diff options
Diffstat (limited to 'sys/gnu/dts/include/dt-bindings')
33 files changed, 0 insertions, 3958 deletions
diff --git a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h b/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h deleted file mode 100644 index 04e8db2..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_ASM9260_H -#define _DT_BINDINGS_CLK_ASM9260_H - -/* ahb gate */ -#define CLKID_AHB_ROM 0 -#define CLKID_AHB_RAM 1 -#define CLKID_AHB_GPIO 2 -#define CLKID_AHB_MAC 3 -#define CLKID_AHB_EMI 4 -#define CLKID_AHB_USB0 5 -#define CLKID_AHB_USB1 6 -#define CLKID_AHB_DMA0 7 -#define CLKID_AHB_DMA1 8 -#define CLKID_AHB_UART0 9 -#define CLKID_AHB_UART1 10 -#define CLKID_AHB_UART2 11 -#define CLKID_AHB_UART3 12 -#define CLKID_AHB_UART4 13 -#define CLKID_AHB_UART5 14 -#define CLKID_AHB_UART6 15 -#define CLKID_AHB_UART7 16 -#define CLKID_AHB_UART8 17 -#define CLKID_AHB_UART9 18 -#define CLKID_AHB_I2S0 19 -#define CLKID_AHB_I2C0 20 -#define CLKID_AHB_I2C1 21 -#define CLKID_AHB_SSP0 22 -#define CLKID_AHB_IOCONFIG 23 -#define CLKID_AHB_WDT 24 -#define CLKID_AHB_CAN0 25 -#define CLKID_AHB_CAN1 26 -#define CLKID_AHB_MPWM 27 -#define CLKID_AHB_SPI0 28 -#define CLKID_AHB_SPI1 29 -#define CLKID_AHB_QEI 30 -#define CLKID_AHB_QUADSPI0 31 -#define CLKID_AHB_CAMIF 32 -#define CLKID_AHB_LCDIF 33 -#define CLKID_AHB_TIMER0 34 -#define CLKID_AHB_TIMER1 35 -#define CLKID_AHB_TIMER2 36 -#define CLKID_AHB_TIMER3 37 -#define CLKID_AHB_IRQ 38 -#define CLKID_AHB_RTC 39 -#define CLKID_AHB_NAND 40 -#define CLKID_AHB_ADC0 41 -#define CLKID_AHB_LED 42 -#define CLKID_AHB_DAC0 43 -#define CLKID_AHB_LCD 44 -#define CLKID_AHB_I2S1 45 -#define CLKID_AHB_MAC1 46 - -/* devider */ -#define CLKID_SYS_CPU 47 -#define CLKID_SYS_AHB 48 -#define CLKID_SYS_I2S0M 49 -#define CLKID_SYS_I2S0S 50 -#define CLKID_SYS_I2S1M 51 -#define CLKID_SYS_I2S1S 52 -#define CLKID_SYS_UART0 53 -#define CLKID_SYS_UART1 54 -#define CLKID_SYS_UART2 55 -#define CLKID_SYS_UART3 56 -#define CLKID_SYS_UART4 56 -#define CLKID_SYS_UART5 57 -#define CLKID_SYS_UART6 58 -#define CLKID_SYS_UART7 59 -#define CLKID_SYS_UART8 60 -#define CLKID_SYS_UART9 61 -#define CLKID_SYS_SPI0 62 -#define CLKID_SYS_SPI1 63 -#define CLKID_SYS_QUADSPI 64 -#define CLKID_SYS_SSP0 65 -#define CLKID_SYS_NAND 66 -#define CLKID_SYS_TRACE 67 -#define CLKID_SYS_CAMM 68 -#define CLKID_SYS_WDT 69 -#define CLKID_SYS_CLKOUT 70 -#define CLKID_SYS_MAC 71 -#define CLKID_SYS_LCD 72 -#define CLKID_SYS_ADCANA 73 - -#define MAX_CLKS 74 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h b/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h deleted file mode 100644 index beb41ac..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014 LSI Corporation - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - */ - -#ifndef _DT_BINDINGS_CLK_AXM5516_H -#define _DT_BINDINGS_CLK_AXM5516_H - -#define AXXIA_CLK_FAB_PLL 0 -#define AXXIA_CLK_CPU_PLL 1 -#define AXXIA_CLK_SYS_PLL 2 -#define AXXIA_CLK_SM0_PLL 3 -#define AXXIA_CLK_SM1_PLL 4 -#define AXXIA_CLK_FAB_DIV 5 -#define AXXIA_CLK_SYS_DIV 6 -#define AXXIA_CLK_NRCP_DIV 7 -#define AXXIA_CLK_CPU0_DIV 8 -#define AXXIA_CLK_CPU1_DIV 9 -#define AXXIA_CLK_CPU2_DIV 10 -#define AXXIA_CLK_CPU3_DIV 11 -#define AXXIA_CLK_PER_DIV 12 -#define AXXIA_CLK_MMC_DIV 13 -#define AXXIA_CLK_FAB 14 -#define AXXIA_CLK_SYS 15 -#define AXXIA_CLK_NRCP 16 -#define AXXIA_CLK_CPU0 17 -#define AXXIA_CLK_CPU1 18 -#define AXXIA_CLK_CPU2 19 -#define AXXIA_CLK_CPU3 20 -#define AXXIA_CLK_PER 21 -#define AXXIA_CLK_MMC 22 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h deleted file mode 100644 index 591f7fb..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef __DTS_MARVELL_MMP2_CLOCK_H -#define __DTS_MARVELL_MMP2_CLOCK_H - -/* fixed clocks and plls */ -#define MMP2_CLK_CLK32 1 -#define MMP2_CLK_VCTCXO 2 -#define MMP2_CLK_PLL1 3 -#define MMP2_CLK_PLL1_2 8 -#define MMP2_CLK_PLL1_4 9 -#define MMP2_CLK_PLL1_8 10 -#define MMP2_CLK_PLL1_16 11 -#define MMP2_CLK_PLL1_3 12 -#define MMP2_CLK_PLL1_6 13 -#define MMP2_CLK_PLL1_12 14 -#define MMP2_CLK_PLL1_20 15 -#define MMP2_CLK_PLL2 16 -#define MMP2_CLK_PLL2_2 17 -#define MMP2_CLK_PLL2_4 18 -#define MMP2_CLK_PLL2_8 19 -#define MMP2_CLK_PLL2_16 20 -#define MMP2_CLK_PLL2_3 21 -#define MMP2_CLK_PLL2_6 22 -#define MMP2_CLK_PLL2_12 23 -#define MMP2_CLK_VCTCXO_2 24 -#define MMP2_CLK_VCTCXO_4 25 -#define MMP2_CLK_UART_PLL 26 -#define MMP2_CLK_USB_PLL 27 - -/* apb periphrals */ -#define MMP2_CLK_TWSI0 60 -#define MMP2_CLK_TWSI1 61 -#define MMP2_CLK_TWSI2 62 -#define MMP2_CLK_TWSI3 63 -#define MMP2_CLK_TWSI4 64 -#define MMP2_CLK_TWSI5 65 -#define MMP2_CLK_GPIO 66 -#define MMP2_CLK_KPC 67 -#define MMP2_CLK_RTC 68 -#define MMP2_CLK_PWM0 69 -#define MMP2_CLK_PWM1 70 -#define MMP2_CLK_PWM2 71 -#define MMP2_CLK_PWM3 72 -#define MMP2_CLK_UART0 73 -#define MMP2_CLK_UART1 74 -#define MMP2_CLK_UART2 75 -#define MMP2_CLK_UART3 76 -#define MMP2_CLK_SSP0 77 -#define MMP2_CLK_SSP1 78 -#define MMP2_CLK_SSP2 79 -#define MMP2_CLK_SSP3 80 - -/* axi periphrals */ -#define MMP2_CLK_SDH0 101 -#define MMP2_CLK_SDH1 102 -#define MMP2_CLK_SDH2 103 -#define MMP2_CLK_SDH3 104 -#define MMP2_CLK_USB 105 -#define MMP2_CLK_DISP0 106 -#define MMP2_CLK_DISP0_MUX 107 -#define MMP2_CLK_DISP0_SPHY 108 -#define MMP2_CLK_DISP1 109 -#define MMP2_CLK_DISP1_MUX 110 -#define MMP2_CLK_CCIC_ARBITER 111 -#define MMP2_CLK_CCIC0 112 -#define MMP2_CLK_CCIC0_MIX 113 -#define MMP2_CLK_CCIC0_PHY 114 -#define MMP2_CLK_CCIC0_SPHY 115 -#define MMP2_CLK_CCIC1 116 -#define MMP2_CLK_CCIC1_MIX 117 -#define MMP2_CLK_CCIC1_PHY 118 -#define MMP2_CLK_CCIC1_SPHY 119 - -#define MMP2_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h deleted file mode 100644 index 79630b9..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __DTS_MARVELL_PXA168_CLOCK_H -#define __DTS_MARVELL_PXA168_CLOCK_H - -/* fixed clocks and plls */ -#define PXA168_CLK_CLK32 1 -#define PXA168_CLK_VCTCXO 2 -#define PXA168_CLK_PLL1 3 -#define PXA168_CLK_PLL1_2 8 -#define PXA168_CLK_PLL1_4 9 -#define PXA168_CLK_PLL1_8 10 -#define PXA168_CLK_PLL1_16 11 -#define PXA168_CLK_PLL1_6 12 -#define PXA168_CLK_PLL1_12 13 -#define PXA168_CLK_PLL1_24 14 -#define PXA168_CLK_PLL1_48 15 -#define PXA168_CLK_PLL1_96 16 -#define PXA168_CLK_PLL1_13 17 -#define PXA168_CLK_PLL1_13_1_5 18 -#define PXA168_CLK_PLL1_2_1_5 19 -#define PXA168_CLK_PLL1_3_16 20 -#define PXA168_CLK_UART_PLL 27 - -/* apb periphrals */ -#define PXA168_CLK_TWSI0 60 -#define PXA168_CLK_TWSI1 61 -#define PXA168_CLK_TWSI2 62 -#define PXA168_CLK_TWSI3 63 -#define PXA168_CLK_GPIO 64 -#define PXA168_CLK_KPC 65 -#define PXA168_CLK_RTC 66 -#define PXA168_CLK_PWM0 67 -#define PXA168_CLK_PWM1 68 -#define PXA168_CLK_PWM2 69 -#define PXA168_CLK_PWM3 70 -#define PXA168_CLK_UART0 71 -#define PXA168_CLK_UART1 72 -#define PXA168_CLK_UART2 73 -#define PXA168_CLK_SSP0 74 -#define PXA168_CLK_SSP1 75 -#define PXA168_CLK_SSP2 76 -#define PXA168_CLK_SSP3 77 -#define PXA168_CLK_SSP4 78 - -/* axi periphrals */ -#define PXA168_CLK_DFC 100 -#define PXA168_CLK_SDH0 101 -#define PXA168_CLK_SDH1 102 -#define PXA168_CLK_SDH2 103 -#define PXA168_CLK_USB 104 -#define PXA168_CLK_SPH 105 -#define PXA168_CLK_DISP0 106 -#define PXA168_CLK_CCIC0 107 -#define PXA168_CLK_CCIC0_PHY 108 -#define PXA168_CLK_CCIC0_SPHY 109 - -#define PXA168_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h deleted file mode 100644 index 719cffb..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __DTS_MARVELL_PXA910_CLOCK_H -#define __DTS_MARVELL_PXA910_CLOCK_H - -/* fixed clocks and plls */ -#define PXA910_CLK_CLK32 1 -#define PXA910_CLK_VCTCXO 2 -#define PXA910_CLK_PLL1 3 -#define PXA910_CLK_PLL1_2 8 -#define PXA910_CLK_PLL1_4 9 -#define PXA910_CLK_PLL1_8 10 -#define PXA910_CLK_PLL1_16 11 -#define PXA910_CLK_PLL1_6 12 -#define PXA910_CLK_PLL1_12 13 -#define PXA910_CLK_PLL1_24 14 -#define PXA910_CLK_PLL1_48 15 -#define PXA910_CLK_PLL1_96 16 -#define PXA910_CLK_PLL1_13 17 -#define PXA910_CLK_PLL1_13_1_5 18 -#define PXA910_CLK_PLL1_2_1_5 19 -#define PXA910_CLK_PLL1_3_16 20 -#define PXA910_CLK_UART_PLL 27 - -/* apb periphrals */ -#define PXA910_CLK_TWSI0 60 -#define PXA910_CLK_TWSI1 61 -#define PXA910_CLK_TWSI2 62 -#define PXA910_CLK_TWSI3 63 -#define PXA910_CLK_GPIO 64 -#define PXA910_CLK_KPC 65 -#define PXA910_CLK_RTC 66 -#define PXA910_CLK_PWM0 67 -#define PXA910_CLK_PWM1 68 -#define PXA910_CLK_PWM2 69 -#define PXA910_CLK_PWM3 70 -#define PXA910_CLK_UART0 71 -#define PXA910_CLK_UART1 72 -#define PXA910_CLK_UART2 73 -#define PXA910_CLK_SSP0 74 -#define PXA910_CLK_SSP1 75 - -/* axi periphrals */ -#define PXA910_CLK_DFC 100 -#define PXA910_CLK_SDH0 101 -#define PXA910_CLK_SDH1 102 -#define PXA910_CLK_SDH2 103 -#define PXA910_CLK_USB 104 -#define PXA910_CLK_SPH 105 -#define PXA910_CLK_DISP0 106 -#define PXA910_CLK_CCIC0 107 -#define PXA910_CLK_CCIC0_PHY 108 -#define PXA910_CLK_CCIC0_SPHY 109 - -#define PXA910_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h deleted file mode 100644 index 7b28b09..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77686 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77686_CLK_AP 0 -#define MAX77686_CLK_CP 1 -#define MAX77686_CLK_PMIC 2 - -/* Total number of clocks. */ -#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 997312e..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h deleted file mode 100644 index 2c0da56..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H -#define _DT_BINDINGS_CLK_APQ_GCC_8084_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define GPLL1 2 -#define GPLL1_VOTE 3 -#define GPLL2 4 -#define GPLL2_VOTE 5 -#define GPLL3 6 -#define GPLL3_VOTE 7 -#define GPLL4 8 -#define GPLL4_VOTE 9 -#define CONFIG_NOC_CLK_SRC 10 -#define PERIPH_NOC_CLK_SRC 11 -#define SYSTEM_NOC_CLK_SRC 12 -#define BLSP_UART_SIM_CLK_SRC 13 -#define QDSS_TSCTR_CLK_SRC 14 -#define UFS_AXI_CLK_SRC 15 -#define RPM_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define BIMC_DDR_CLK_SRC 19 -#define USB30_MASTER_CLK_SRC 20 -#define USB30_SEC_MASTER_CLK_SRC 21 -#define USB_HSIC_AHB_CLK_SRC 22 -#define MMSS_BIMC_GFX_CLK_SRC 23 -#define QDSS_STM_CLK_SRC 24 -#define ACC_CLK_SRC 25 -#define SEC_CTRL_CLK_SRC 26 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 -#define BLSP1_UART1_APPS_CLK_SRC 39 -#define BLSP1_UART2_APPS_CLK_SRC 40 -#define BLSP1_UART3_APPS_CLK_SRC 41 -#define BLSP1_UART4_APPS_CLK_SRC 42 -#define BLSP1_UART5_APPS_CLK_SRC 43 -#define BLSP1_UART6_APPS_CLK_SRC 44 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 -#define BLSP2_UART1_APPS_CLK_SRC 57 -#define BLSP2_UART2_APPS_CLK_SRC 58 -#define BLSP2_UART3_APPS_CLK_SRC 59 -#define BLSP2_UART4_APPS_CLK_SRC 60 -#define BLSP2_UART5_APPS_CLK_SRC 61 -#define BLSP2_UART6_APPS_CLK_SRC 62 -#define CE1_CLK_SRC 63 -#define CE2_CLK_SRC 64 -#define CE3_CLK_SRC 65 -#define GP1_CLK_SRC 66 -#define GP2_CLK_SRC 67 -#define GP3_CLK_SRC 68 -#define PDM2_CLK_SRC 69 -#define QDSS_TRACECLKIN_CLK_SRC 70 -#define RBCPR_CLK_SRC 71 -#define SATA_ASIC0_CLK_SRC 72 -#define SATA_PMALIVE_CLK_SRC 73 -#define SATA_RX_CLK_SRC 74 -#define SATA_RX_OOB_CLK_SRC 75 -#define SDCC1_APPS_CLK_SRC 76 -#define SDCC2_APPS_CLK_SRC 77 -#define SDCC3_APPS_CLK_SRC 78 -#define SDCC4_APPS_CLK_SRC 79 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 -#define SPMI_AHB_CLK_SRC 81 -#define SPMI_SER_CLK_SRC 82 -#define TSIF_REF_CLK_SRC 83 -#define USB30_MOCK_UTMI_CLK_SRC 84 -#define USB30_SEC_MOCK_UTMI_CLK_SRC 85 -#define USB_HS_SYSTEM_CLK_SRC 86 -#define USB_HSIC_CLK_SRC 87 -#define USB_HSIC_IO_CAL_CLK_SRC 88 -#define USB_HSIC_MOCK_UTMI_CLK_SRC 89 -#define USB_HSIC_SYSTEM_CLK_SRC 90 -#define GCC_BAM_DMA_AHB_CLK 91 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 -#define DDR_CLK_SRC 93 -#define GCC_BIMC_CFG_AHB_CLK 94 -#define GCC_BIMC_CLK 95 -#define GCC_BIMC_KPSS_AXI_CLK 96 -#define GCC_BIMC_SLEEP_CLK 97 -#define GCC_BIMC_SYSNOC_AXI_CLK 98 -#define GCC_BIMC_XO_CLK 99 -#define GCC_BLSP1_AHB_CLK 100 -#define GCC_BLSP1_SLEEP_CLK 101 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 -#define GCC_BLSP1_UART1_APPS_CLK 114 -#define GCC_BLSP1_UART1_SIM_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_UART2_SIM_CLK 117 -#define GCC_BLSP1_UART3_APPS_CLK 118 -#define GCC_BLSP1_UART3_SIM_CLK 119 -#define GCC_BLSP1_UART4_APPS_CLK 120 -#define GCC_BLSP1_UART4_SIM_CLK 121 -#define GCC_BLSP1_UART5_APPS_CLK 122 -#define GCC_BLSP1_UART5_SIM_CLK 123 -#define GCC_BLSP1_UART6_APPS_CLK 124 -#define GCC_BLSP1_UART6_SIM_CLK 125 -#define GCC_BLSP2_AHB_CLK 126 -#define GCC_BLSP2_SLEEP_CLK 127 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 -#define GCC_BLSP2_UART1_APPS_CLK 140 -#define GCC_BLSP2_UART1_SIM_CLK 141 -#define GCC_BLSP2_UART2_APPS_CLK 142 -#define GCC_BLSP2_UART2_SIM_CLK 143 -#define GCC_BLSP2_UART3_APPS_CLK 144 -#define GCC_BLSP2_UART3_SIM_CLK 145 -#define GCC_BLSP2_UART4_APPS_CLK 146 -#define GCC_BLSP2_UART4_SIM_CLK 147 -#define GCC_BLSP2_UART5_APPS_CLK 148 -#define GCC_BLSP2_UART5_SIM_CLK 149 -#define GCC_BLSP2_UART6_APPS_CLK 150 -#define GCC_BLSP2_UART6_SIM_CLK 151 -#define GCC_BOOT_ROM_AHB_CLK 152 -#define GCC_CE1_AHB_CLK 153 -#define GCC_CE1_AXI_CLK 154 -#define GCC_CE1_CLK 155 -#define GCC_CE2_AHB_CLK 156 -#define GCC_CE2_AXI_CLK 157 -#define GCC_CE2_CLK 158 -#define GCC_CE3_AHB_CLK 159 -#define GCC_CE3_AXI_CLK 160 -#define GCC_CE3_CLK 161 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 -#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 -#define GCC_CFG_NOC_AHB_CLK 170 -#define GCC_CFG_NOC_DDR_CFG_CLK 171 -#define GCC_CFG_NOC_RPM_AHB_CLK 172 -#define GCC_COPSS_SMMU_AHB_CLK 173 -#define GCC_COPSS_SMMU_AXI_CLK 174 -#define GCC_DCD_XO_CLK 175 -#define GCC_BIMC_DDR_CH0_CLK 176 -#define GCC_BIMC_DDR_CH1_CLK 177 -#define GCC_BIMC_DDR_CPLL0_CLK 178 -#define GCC_BIMC_DDR_CPLL1_CLK 179 -#define GCC_BIMC_GFX_CLK 180 -#define GCC_DDR_DIM_CFG_CLK 181 -#define GCC_DDR_DIM_SLEEP_CLK 182 -#define GCC_DEHR_CLK 183 -#define GCC_AHB_CLK 184 -#define GCC_IM_SLEEP_CLK 185 -#define GCC_XO_CLK 186 -#define GCC_XO_DIV4_CLK 187 -#define GCC_GP1_CLK 188 -#define GCC_GP2_CLK 189 -#define GCC_GP3_CLK 190 -#define GCC_IMEM_AXI_CLK 191 -#define GCC_IMEM_CFG_AHB_CLK 192 -#define GCC_KPSS_AHB_CLK 193 -#define GCC_KPSS_AXI_CLK 194 -#define GCC_LPASS_MPORT_AXI_CLK 195 -#define GCC_LPASS_Q6_AXI_CLK 196 -#define GCC_LPASS_SWAY_CLK 197 -#define GCC_MMSS_BIMC_GFX_CLK 198 -#define GCC_MMSS_NOC_AT_CLK 199 -#define GCC_MMSS_NOC_CFG_AHB_CLK 200 -#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 202 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 203 -#define GCC_MPM_AHB_CLK 204 -#define GCC_MSG_RAM_AHB_CLK 205 -#define GCC_NOC_CONF_XPU_AHB_CLK 206 -#define GCC_PDM2_CLK 207 -#define GCC_PDM_AHB_CLK 208 -#define GCC_PDM_XO4_CLK 209 -#define GCC_PERIPH_NOC_AHB_CLK 210 -#define GCC_PERIPH_NOC_AT_CLK 211 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 212 -#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 -#define GCC_PERIPH_XPU_AHB_CLK 215 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 -#define GCC_PRNG_AHB_CLK 221 -#define GCC_QDSS_AT_CLK 222 -#define GCC_QDSS_CFG_AHB_CLK 223 -#define GCC_QDSS_DAP_AHB_CLK 224 -#define GCC_QDSS_DAP_CLK 225 -#define GCC_QDSS_ETR_USB_CLK 226 -#define GCC_QDSS_STM_CLK 227 -#define GCC_QDSS_TRACECLKIN_CLK 228 -#define GCC_QDSS_TSCTR_DIV16_CLK 229 -#define GCC_QDSS_TSCTR_DIV2_CLK 230 -#define GCC_QDSS_TSCTR_DIV3_CLK 231 -#define GCC_QDSS_TSCTR_DIV4_CLK 232 -#define GCC_QDSS_TSCTR_DIV8_CLK 233 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 -#define GCC_RBCPR_AHB_CLK 235 -#define GCC_RBCPR_CLK 236 -#define GCC_RPM_BUS_AHB_CLK 237 -#define GCC_RPM_PROC_HCLK 238 -#define GCC_RPM_SLEEP_CLK 239 -#define GCC_RPM_TIMER_CLK 240 -#define GCC_SATA_ASIC0_CLK 241 -#define GCC_SATA_AXI_CLK 242 -#define GCC_SATA_CFG_AHB_CLK 243 -#define GCC_SATA_PMALIVE_CLK 244 -#define GCC_SATA_RX_CLK 245 -#define GCC_SATA_RX_OOB_CLK 246 -#define GCC_SDCC1_AHB_CLK 247 -#define GCC_SDCC1_APPS_CLK 248 -#define GCC_SDCC1_CDCCAL_FF_CLK 249 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 -#define GCC_SDCC2_AHB_CLK 251 -#define GCC_SDCC2_APPS_CLK 252 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 -#define GCC_SDCC3_AHB_CLK 254 -#define GCC_SDCC3_APPS_CLK 255 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 -#define GCC_SDCC4_AHB_CLK 257 -#define GCC_SDCC4_APPS_CLK 258 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 -#define GCC_SEC_CTRL_ACC_CLK 260 -#define GCC_SEC_CTRL_AHB_CLK 261 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 -#define GCC_SEC_CTRL_CLK 263 -#define GCC_SEC_CTRL_SENSE_CLK 264 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 -#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 -#define GCC_SPDM_BIMC_CY_CLK 267 -#define GCC_SPDM_CFG_AHB_CLK 268 -#define GCC_SPDM_DEBUG_CY_CLK 269 -#define GCC_SPDM_FF_CLK 270 -#define GCC_SPDM_MSTR_AHB_CLK 271 -#define GCC_SPDM_PNOC_CY_CLK 272 -#define GCC_SPDM_RPM_CY_CLK 273 -#define GCC_SPDM_SNOC_CY_CLK 274 -#define GCC_SPMI_AHB_CLK 275 -#define GCC_SPMI_CNOC_AHB_CLK 276 -#define GCC_SPMI_SER_CLK 277 -#define GCC_SPSS_AHB_CLK 278 -#define GCC_SNOC_CNOC_AHB_CLK 279 -#define GCC_SNOC_PNOC_AHB_CLK 280 -#define GCC_SYS_NOC_AT_CLK 281 -#define GCC_SYS_NOC_AXI_CLK 282 -#define GCC_SYS_NOC_KPSS_AHB_CLK 283 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 -#define GCC_SYS_NOC_UFS_AXI_CLK 285 -#define GCC_SYS_NOC_USB3_AXI_CLK 286 -#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 -#define GCC_TCSR_AHB_CLK 288 -#define GCC_TLMM_AHB_CLK 289 -#define GCC_TLMM_CLK 290 -#define GCC_TSIF_AHB_CLK 291 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 -#define GCC_TSIF_REF_CLK 293 -#define GCC_UFS_AHB_CLK 294 -#define GCC_UFS_AXI_CLK 295 -#define GCC_UFS_RX_CFG_CLK 296 -#define GCC_UFS_RX_SYMBOL_0_CLK 297 -#define GCC_UFS_RX_SYMBOL_1_CLK 298 -#define GCC_UFS_TX_CFG_CLK 299 -#define GCC_UFS_TX_SYMBOL_0_CLK 300 -#define GCC_UFS_TX_SYMBOL_1_CLK 301 -#define GCC_USB2A_PHY_SLEEP_CLK 302 -#define GCC_USB2B_PHY_SLEEP_CLK 303 -#define GCC_USB30_MASTER_CLK 304 -#define GCC_USB30_MOCK_UTMI_CLK 305 -#define GCC_USB30_SLEEP_CLK 306 -#define GCC_USB30_SEC_MASTER_CLK 307 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 308 -#define GCC_USB30_SEC_SLEEP_CLK 309 -#define GCC_USB_HS_AHB_CLK 310 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 -#define GCC_USB_HS_SYSTEM_CLK 312 -#define GCC_USB_HSIC_AHB_CLK 313 -#define GCC_USB_HSIC_CLK 314 -#define GCC_USB_HSIC_IO_CAL_CLK 315 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 -#define GCC_USB_HSIC_MOCK_UTMI_CLK 317 -#define GCC_USB_HSIC_SYSTEM_CLK 318 -#define PCIE_0_AUX_CLK_SRC 319 -#define PCIE_0_PIPE_CLK_SRC 320 -#define PCIE_1_AUX_CLK_SRC 321 -#define PCIE_1_PIPE_CLK_SRC 322 -#define GCC_PCIE_0_AUX_CLK 323 -#define GCC_PCIE_0_CFG_AHB_CLK 324 -#define GCC_PCIE_0_MSTR_AXI_CLK 325 -#define GCC_PCIE_0_PIPE_CLK 326 -#define GCC_PCIE_0_SLV_AXI_CLK 327 -#define GCC_PCIE_1_AUX_CLK 328 -#define GCC_PCIE_1_CFG_AHB_CLK 329 -#define GCC_PCIE_1_MSTR_AXI_CLK 330 -#define GCC_PCIE_1_PIPE_CLK 331 -#define GCC_PCIE_1_SLV_AXI_CLK 332 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h deleted file mode 100644 index 04fb29a..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H -#define _DT_BINDINGS_CLK_GCC_IPQ806X_H - -#define AFAB_CLK_SRC 0 -#define QDSS_STM_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define AFAB_CORE_CLK 4 -#define SCSS_XO_SRC_CLK 5 -#define AFAB_EBI1_CH0_A_CLK 6 -#define AFAB_EBI1_CH1_A_CLK 7 -#define AFAB_AXI_S0_FCLK 8 -#define AFAB_AXI_S1_FCLK 9 -#define AFAB_AXI_S2_FCLK 10 -#define AFAB_AXI_S3_FCLK 11 -#define AFAB_AXI_S4_FCLK 12 -#define SFAB_CORE_CLK 13 -#define SFAB_AXI_S0_FCLK 14 -#define SFAB_AXI_S1_FCLK 15 -#define SFAB_AXI_S2_FCLK 16 -#define SFAB_AXI_S3_FCLK 17 -#define SFAB_AXI_S4_FCLK 18 -#define SFAB_AXI_S5_FCLK 19 -#define SFAB_AHB_S0_FCLK 20 -#define SFAB_AHB_S1_FCLK 21 -#define SFAB_AHB_S2_FCLK 22 -#define SFAB_AHB_S3_FCLK 23 -#define SFAB_AHB_S4_FCLK 24 -#define SFAB_AHB_S5_FCLK 25 -#define SFAB_AHB_S6_FCLK 26 -#define SFAB_AHB_S7_FCLK 27 -#define QDSS_AT_CLK_SRC 28 -#define QDSS_AT_CLK 29 -#define QDSS_TRACECLKIN_CLK_SRC 30 -#define QDSS_TRACECLKIN_CLK 31 -#define QDSS_TSCTR_CLK_SRC 32 -#define QDSS_TSCTR_CLK 33 -#define SFAB_ADM0_M0_A_CLK 34 -#define SFAB_ADM0_M1_A_CLK 35 -#define SFAB_ADM0_M2_H_CLK 36 -#define ADM0_CLK 37 -#define ADM0_PBUS_CLK 38 -#define IMEM0_A_CLK 39 -#define QDSS_H_CLK 40 -#define PCIE_A_CLK 41 -#define PCIE_AUX_CLK 42 -#define PCIE_H_CLK 43 -#define PCIE_PHY_CLK 44 -#define SFAB_CLK_SRC 45 -#define SFAB_LPASS_Q6_A_CLK 46 -#define SFAB_AFAB_M_A_CLK 47 -#define AFAB_SFAB_M0_A_CLK 48 -#define AFAB_SFAB_M1_A_CLK 49 -#define SFAB_SATA_S_H_CLK 50 -#define DFAB_CLK_SRC 51 -#define DFAB_CLK 52 -#define SFAB_DFAB_M_A_CLK 53 -#define DFAB_SFAB_M_A_CLK 54 -#define DFAB_SWAY0_H_CLK 55 -#define DFAB_SWAY1_H_CLK 56 -#define DFAB_ARB0_H_CLK 57 -#define DFAB_ARB1_H_CLK 58 -#define PPSS_H_CLK 59 -#define PPSS_PROC_CLK 60 -#define PPSS_TIMER0_CLK 61 -#define PPSS_TIMER1_CLK 62 -#define PMEM_A_CLK 63 -#define DMA_BAM_H_CLK 64 -#define SIC_H_CLK 65 -#define SPS_TIC_H_CLK 66 -#define CFPB_2X_CLK_SRC 67 -#define CFPB_CLK 68 -#define CFPB0_H_CLK 69 -#define CFPB1_H_CLK 70 -#define CFPB2_H_CLK 71 -#define SFAB_CFPB_M_H_CLK 72 -#define CFPB_MASTER_H_CLK 73 -#define SFAB_CFPB_S_H_CLK 74 -#define CFPB_SPLITTER_H_CLK 75 -#define TSIF_H_CLK 76 -#define TSIF_INACTIVITY_TIMERS_CLK 77 -#define TSIF_REF_SRC 78 -#define TSIF_REF_CLK 79 -#define CE1_H_CLK 80 -#define CE1_CORE_CLK 81 -#define CE1_SLEEP_CLK 82 -#define CE2_H_CLK 83 -#define CE2_CORE_CLK 84 -#define SFPB_H_CLK_SRC 85 -#define SFPB_H_CLK 86 -#define SFAB_SFPB_M_H_CLK 87 -#define SFAB_SFPB_S_H_CLK 88 -#define RPM_PROC_CLK 89 -#define RPM_BUS_H_CLK 90 -#define RPM_SLEEP_CLK 91 -#define RPM_TIMER_CLK 92 -#define RPM_MSG_RAM_H_CLK 93 -#define PMIC_ARB0_H_CLK 94 -#define PMIC_ARB1_H_CLK 95 -#define PMIC_SSBI2_SRC 96 -#define PMIC_SSBI2_CLK 97 -#define SDC1_H_CLK 98 -#define SDC2_H_CLK 99 -#define SDC3_H_CLK 100 -#define SDC4_H_CLK 101 -#define SDC1_SRC 102 -#define SDC1_CLK 103 -#define SDC2_SRC 104 -#define SDC2_CLK 105 -#define SDC3_SRC 106 -#define SDC3_CLK 107 -#define SDC4_SRC 108 -#define SDC4_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HSIC_H_CLK 113 -#define USB_HSIC_XCVR_SRC 114 -#define USB_HSIC_XCVR_CLK 115 -#define USB_HSIC_SYSTEM_CLK_SRC 116 -#define USB_HSIC_SYSTEM_CLK 117 -#define CFPB0_C0_H_CLK 118 -#define CFPB0_D0_H_CLK 119 -#define CFPB0_C1_H_CLK 120 -#define CFPB0_D1_H_CLK 121 -#define USB_FS1_H_CLK 122 -#define USB_FS1_XCVR_SRC 123 -#define USB_FS1_XCVR_CLK 124 -#define USB_FS1_SYSTEM_CLK 125 -#define GSBI_COMMON_SIM_SRC 126 -#define GSBI1_H_CLK 127 -#define GSBI2_H_CLK 128 -#define GSBI3_H_CLK 129 -#define GSBI4_H_CLK 130 -#define GSBI5_H_CLK 131 -#define GSBI6_H_CLK 132 -#define GSBI7_H_CLK 133 -#define GSBI1_QUP_SRC 134 -#define GSBI1_QUP_CLK 135 -#define GSBI2_QUP_SRC 136 -#define GSBI2_QUP_CLK 137 -#define GSBI3_QUP_SRC 138 -#define GSBI3_QUP_CLK 139 -#define GSBI4_QUP_SRC 140 -#define GSBI4_QUP_CLK 141 -#define GSBI5_QUP_SRC 142 -#define GSBI5_QUP_CLK 143 -#define GSBI6_QUP_SRC 144 -#define GSBI6_QUP_CLK 145 -#define GSBI7_QUP_SRC 146 -#define GSBI7_QUP_CLK 147 -#define GSBI1_UART_SRC 148 -#define GSBI1_UART_CLK 149 -#define GSBI2_UART_SRC 150 -#define GSBI2_UART_CLK 151 -#define GSBI3_UART_SRC 152 -#define GSBI3_UART_CLK 153 -#define GSBI4_UART_SRC 154 -#define GSBI4_UART_CLK 155 -#define GSBI5_UART_SRC 156 -#define GSBI5_UART_CLK 157 -#define GSBI6_UART_SRC 158 -#define GSBI6_UART_CLK 159 -#define GSBI7_UART_SRC 160 -#define GSBI7_UART_CLK 161 -#define GSBI1_SIM_CLK 162 -#define GSBI2_SIM_CLK 163 -#define GSBI3_SIM_CLK 164 -#define GSBI4_SIM_CLK 165 -#define GSBI5_SIM_CLK 166 -#define GSBI6_SIM_CLK 167 -#define GSBI7_SIM_CLK 168 -#define USB_HSIC_HSIC_CLK_SRC 169 -#define USB_HSIC_HSIC_CLK 170 -#define USB_HSIC_HSIO_CAL_CLK 171 -#define SPDM_CFG_H_CLK 172 -#define SPDM_MSTR_H_CLK 173 -#define SPDM_FF_CLK_SRC 174 -#define SPDM_FF_CLK 175 -#define SEC_CTRL_CLK 176 -#define SEC_CTRL_ACC_CLK_SRC 177 -#define SEC_CTRL_ACC_CLK 178 -#define TLMM_H_CLK 179 -#define TLMM_CLK 180 -#define SATA_H_CLK 181 -#define SATA_CLK_SRC 182 -#define SATA_RXOOB_CLK 183 -#define SATA_PMALIVE_CLK 184 -#define SATA_PHY_REF_CLK 185 -#define SATA_A_CLK 186 -#define SATA_PHY_CFG_CLK 187 -#define TSSC_CLK_SRC 188 -#define TSSC_CLK 189 -#define PDM_SRC 190 -#define PDM_CLK 191 -#define GP0_SRC 192 -#define GP0_CLK 193 -#define GP1_SRC 194 -#define GP1_CLK 195 -#define GP2_SRC 196 -#define GP2_CLK 197 -#define MPM_CLK 198 -#define EBI1_CLK_SRC 199 -#define EBI1_CH0_CLK 200 -#define EBI1_CH1_CLK 201 -#define EBI1_2X_CLK 202 -#define EBI1_CH0_DQ_CLK 203 -#define EBI1_CH1_DQ_CLK 204 -#define EBI1_CH0_CA_CLK 205 -#define EBI1_CH1_CA_CLK 206 -#define EBI1_XO_CLK 207 -#define SFAB_SMPSS_S_H_CLK 208 -#define PRNG_SRC 209 -#define PRNG_CLK 210 -#define PXO_SRC 211 -#define SPDM_CY_PORT0_CLK 212 -#define SPDM_CY_PORT1_CLK 213 -#define SPDM_CY_PORT2_CLK 214 -#define SPDM_CY_PORT3_CLK 215 -#define SPDM_CY_PORT4_CLK 216 -#define SPDM_CY_PORT5_CLK 217 -#define SPDM_CY_PORT6_CLK 218 -#define SPDM_CY_PORT7_CLK 219 -#define PLL0 220 -#define PLL0_VOTE 221 -#define PLL3 222 -#define PLL3_VOTE 223 -#define PLL4_VOTE 225 -#define PLL8 226 -#define PLL8_VOTE 227 -#define PLL9 228 -#define PLL10 229 -#define PLL11 230 -#define PLL12 231 -#define PLL14 232 -#define PLL14_VOTE 233 -#define PLL18 234 -#define CE5_SRC 235 -#define CE5_H_CLK 236 -#define CE5_CORE_CLK 237 -#define CE3_SLEEP_CLK 238 -#define SFAB_AHB_S8_FCLK 239 -#define SPDM_CY_PORT8_CLK 246 -#define PCIE_ALT_REF_SRC 247 -#define PCIE_ALT_REF_CLK 248 -#define PCIE_1_A_CLK 249 -#define PCIE_1_AUX_CLK 250 -#define PCIE_1_H_CLK 251 -#define PCIE_1_PHY_CLK 252 -#define PCIE_1_ALT_REF_SRC 253 -#define PCIE_1_ALT_REF_CLK 254 -#define PCIE_2_A_CLK 255 -#define PCIE_2_AUX_CLK 256 -#define PCIE_2_H_CLK 257 -#define PCIE_2_PHY_CLK 258 -#define PCIE_2_ALT_REF_SRC 259 -#define PCIE_2_ALT_REF_CLK 260 -#define EBI2_CLK 261 -#define USB30_SLEEP_CLK 262 -#define USB30_UTMI_SRC 263 -#define USB30_0_UTMI_CLK 264 -#define USB30_1_UTMI_CLK 265 -#define USB30_MASTER_SRC 266 -#define USB30_0_MASTER_CLK 267 -#define USB30_1_MASTER_CLK 268 -#define GMAC_CORE1_CLK_SRC 269 -#define GMAC_CORE2_CLK_SRC 270 -#define GMAC_CORE3_CLK_SRC 271 -#define GMAC_CORE4_CLK_SRC 272 -#define GMAC_CORE1_CLK 273 -#define GMAC_CORE2_CLK 274 -#define GMAC_CORE3_CLK 275 -#define GMAC_CORE4_CLK 276 -#define UBI32_CORE1_CLK_SRC 277 -#define UBI32_CORE2_CLK_SRC 278 -#define UBI32_CORE1_CLK 279 -#define UBI32_CORE2_CLK 280 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h deleted file mode 100644 index 67665f6..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H -#define _DT_BINDINGS_CLK_MSM_GCC_8660_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define SCSS_XO_SRC_CLK 4 -#define AFAB_EBI1_CH0_A_CLK 5 -#define AFAB_EBI1_CH1_A_CLK 6 -#define AFAB_AXI_S0_FCLK 7 -#define AFAB_AXI_S1_FCLK 8 -#define AFAB_AXI_S2_FCLK 9 -#define AFAB_AXI_S3_FCLK 10 -#define AFAB_AXI_S4_FCLK 11 -#define SFAB_CORE_CLK 12 -#define SFAB_AXI_S0_FCLK 13 -#define SFAB_AXI_S1_FCLK 14 -#define SFAB_AXI_S2_FCLK 15 -#define SFAB_AXI_S3_FCLK 16 -#define SFAB_AXI_S4_FCLK 17 -#define SFAB_AHB_S0_FCLK 18 -#define SFAB_AHB_S1_FCLK 19 -#define SFAB_AHB_S2_FCLK 20 -#define SFAB_AHB_S3_FCLK 21 -#define SFAB_AHB_S4_FCLK 22 -#define SFAB_AHB_S5_FCLK 23 -#define SFAB_AHB_S6_FCLK 24 -#define SFAB_ADM0_M0_A_CLK 25 -#define SFAB_ADM0_M1_A_CLK 26 -#define SFAB_ADM0_M2_A_CLK 27 -#define ADM0_CLK 28 -#define ADM0_PBUS_CLK 29 -#define SFAB_ADM1_M0_A_CLK 30 -#define SFAB_ADM1_M1_A_CLK 31 -#define SFAB_ADM1_M2_A_CLK 32 -#define MMFAB_ADM1_M3_A_CLK 33 -#define ADM1_CLK 34 -#define ADM1_PBUS_CLK 35 -#define IMEM0_A_CLK 36 -#define MAHB0_CLK 37 -#define SFAB_LPASS_Q6_A_CLK 38 -#define SFAB_AFAB_M_A_CLK 39 -#define AFAB_SFAB_M0_A_CLK 40 -#define AFAB_SFAB_M1_A_CLK 41 -#define DFAB_CLK_SRC 42 -#define DFAB_CLK 43 -#define DFAB_CORE_CLK 44 -#define SFAB_DFAB_M_A_CLK 45 -#define DFAB_SFAB_M_A_CLK 46 -#define DFAB_SWAY0_H_CLK 47 -#define DFAB_SWAY1_H_CLK 48 -#define DFAB_ARB0_H_CLK 49 -#define DFAB_ARB1_H_CLK 50 -#define PPSS_H_CLK 51 -#define PPSS_PROC_CLK 52 -#define PPSS_TIMER0_CLK 53 -#define PPSS_TIMER1_CLK 54 -#define PMEM_A_CLK 55 -#define DMA_BAM_H_CLK 56 -#define SIC_H_CLK 57 -#define SPS_TIC_H_CLK 58 -#define SLIMBUS_H_CLK 59 -#define SLIMBUS_XO_SRC_CLK 60 -#define CFPB_2X_CLK_SRC 61 -#define CFPB_CLK 62 -#define CFPB0_H_CLK 63 -#define CFPB1_H_CLK 64 -#define CFPB2_H_CLK 65 -#define EBI2_2X_CLK 66 -#define EBI2_CLK 67 -#define SFAB_CFPB_M_H_CLK 68 -#define CFPB_MASTER_H_CLK 69 -#define SFAB_CFPB_S_HCLK 70 -#define CFPB_SPLITTER_H_CLK 71 -#define TSIF_H_CLK 72 -#define TSIF_INACTIVITY_TIMERS_CLK 73 -#define TSIF_REF_SRC 74 -#define TSIF_REF_CLK 75 -#define CE1_H_CLK 76 -#define CE2_H_CLK 77 -#define SFPB_H_CLK_SRC 78 -#define SFPB_H_CLK 79 -#define SFAB_SFPB_M_H_CLK 80 -#define SFAB_SFPB_S_H_CLK 81 -#define RPM_PROC_CLK 82 -#define RPM_BUS_H_CLK 83 -#define RPM_SLEEP_CLK 84 -#define RPM_TIMER_CLK 85 -#define MODEM_AHB1_H_CLK 86 -#define MODEM_AHB2_H_CLK 87 -#define RPM_MSG_RAM_H_CLK 88 -#define SC_H_CLK 89 -#define SC_A_CLK 90 -#define PMIC_ARB0_H_CLK 91 -#define PMIC_ARB1_H_CLK 92 -#define PMIC_SSBI2_SRC 93 -#define PMIC_SSBI2_CLK 94 -#define SDC1_H_CLK 95 -#define SDC2_H_CLK 96 -#define SDC3_H_CLK 97 -#define SDC4_H_CLK 98 -#define SDC5_H_CLK 99 -#define SDC1_SRC 100 -#define SDC2_SRC 101 -#define SDC3_SRC 102 -#define SDC4_SRC 103 -#define SDC5_SRC 104 -#define SDC1_CLK 105 -#define SDC2_CLK 106 -#define SDC3_CLK 107 -#define SDC4_CLK 108 -#define SDC5_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HS2_H_CLK 113 -#define USB_HS2_XCVR_SRC 114 -#define USB_HS2_XCVR_CLK 115 -#define USB_FS1_H_CLK 116 -#define USB_FS1_XCVR_FS_SRC 117 -#define USB_FS1_XCVR_FS_CLK 118 -#define USB_FS1_SYSTEM_CLK 119 -#define USB_FS2_H_CLK 120 -#define USB_FS2_XCVR_FS_SRC 121 -#define USB_FS2_XCVR_FS_CLK 122 -#define USB_FS2_SYSTEM_CLK 123 -#define GSBI_COMMON_SIM_SRC 124 -#define GSBI1_H_CLK 125 -#define GSBI2_H_CLK 126 -#define GSBI3_H_CLK 127 -#define GSBI4_H_CLK 128 -#define GSBI5_H_CLK 129 -#define GSBI6_H_CLK 130 -#define GSBI7_H_CLK 131 -#define GSBI8_H_CLK 132 -#define GSBI9_H_CLK 133 -#define GSBI10_H_CLK 134 -#define GSBI11_H_CLK 135 -#define GSBI12_H_CLK 136 -#define GSBI1_UART_SRC 137 -#define GSBI1_UART_CLK 138 -#define GSBI2_UART_SRC 139 -#define GSBI2_UART_CLK 140 -#define GSBI3_UART_SRC 141 -#define GSBI3_UART_CLK 142 -#define GSBI4_UART_SRC 143 -#define GSBI4_UART_CLK 144 -#define GSBI5_UART_SRC 145 -#define GSBI5_UART_CLK 146 -#define GSBI6_UART_SRC 147 -#define GSBI6_UART_CLK 148 -#define GSBI7_UART_SRC 149 -#define GSBI7_UART_CLK 150 -#define GSBI8_UART_SRC 151 -#define GSBI8_UART_CLK 152 -#define GSBI9_UART_SRC 153 -#define GSBI9_UART_CLK 154 -#define GSBI10_UART_SRC 155 -#define GSBI10_UART_CLK 156 -#define GSBI11_UART_SRC 157 -#define GSBI11_UART_CLK 158 -#define GSBI12_UART_SRC 159 -#define GSBI12_UART_CLK 160 -#define GSBI1_QUP_SRC 161 -#define GSBI1_QUP_CLK 162 -#define GSBI2_QUP_SRC 163 -#define GSBI2_QUP_CLK 164 -#define GSBI3_QUP_SRC 165 -#define GSBI3_QUP_CLK 166 -#define GSBI4_QUP_SRC 167 -#define GSBI4_QUP_CLK 168 -#define GSBI5_QUP_SRC 169 -#define GSBI5_QUP_CLK 170 -#define GSBI6_QUP_SRC 171 -#define GSBI6_QUP_CLK 172 -#define GSBI7_QUP_SRC 173 -#define GSBI7_QUP_CLK 174 -#define GSBI8_QUP_SRC 175 -#define GSBI8_QUP_CLK 176 -#define GSBI9_QUP_SRC 177 -#define GSBI9_QUP_CLK 178 -#define GSBI10_QUP_SRC 179 -#define GSBI10_QUP_CLK 180 -#define GSBI11_QUP_SRC 181 -#define GSBI11_QUP_CLK 182 -#define GSBI12_QUP_SRC 183 -#define GSBI12_QUP_CLK 184 -#define GSBI1_SIM_CLK 185 -#define GSBI2_SIM_CLK 186 -#define GSBI3_SIM_CLK 187 -#define GSBI4_SIM_CLK 188 -#define GSBI5_SIM_CLK 189 -#define GSBI6_SIM_CLK 190 -#define GSBI7_SIM_CLK 191 -#define GSBI8_SIM_CLK 192 -#define GSBI9_SIM_CLK 193 -#define GSBI10_SIM_CLK 194 -#define GSBI11_SIM_CLK 195 -#define GSBI12_SIM_CLK 196 -#define SPDM_CFG_H_CLK 197 -#define SPDM_MSTR_H_CLK 198 -#define SPDM_FF_CLK_SRC 199 -#define SPDM_FF_CLK 200 -#define SEC_CTRL_CLK 201 -#define SEC_CTRL_ACC_CLK_SRC 202 -#define SEC_CTRL_ACC_CLK 203 -#define TLMM_H_CLK 204 -#define TLMM_CLK 205 -#define MARM_CLK_SRC 206 -#define MARM_CLK 207 -#define MAHB1_SRC 208 -#define MAHB1_CLK 209 -#define SFAB_MSS_S_H_CLK 210 -#define MAHB2_SRC 211 -#define MAHB2_CLK 212 -#define MSS_MODEM_CLK_SRC 213 -#define MSS_MODEM_CXO_CLK 214 -#define MSS_SLP_CLK 215 -#define MSS_SYS_REF_CLK 216 -#define TSSC_CLK_SRC 217 -#define TSSC_CLK 218 -#define PDM_SRC 219 -#define PDM_CLK 220 -#define GP0_SRC 221 -#define GP0_CLK 222 -#define GP1_SRC 223 -#define GP1_CLK 224 -#define GP2_SRC 225 -#define GP2_CLK 226 -#define PMEM_CLK 227 -#define MPM_CLK 228 -#define EBI1_ASFAB_SRC 229 -#define EBI1_CLK_SRC 230 -#define EBI1_CH0_CLK 231 -#define EBI1_CH1_CLK 232 -#define SFAB_SMPSS_S_H_CLK 233 -#define PRNG_SRC 234 -#define PRNG_CLK 235 -#define PXO_SRC 236 -#define LPASS_CXO_CLK 237 -#define LPASS_PXO_CLK 238 -#define SPDM_CY_PORT0_CLK 239 -#define SPDM_CY_PORT1_CLK 240 -#define SPDM_CY_PORT2_CLK 241 -#define SPDM_CY_PORT3_CLK 242 -#define SPDM_CY_PORT4_CLK 243 -#define SPDM_CY_PORT5_CLK 244 -#define SPDM_CY_PORT6_CLK 245 -#define SPDM_CY_PORT7_CLK 246 -#define PLL0 247 -#define PLL0_VOTE 248 -#define PLL5 249 -#define PLL6 250 -#define PLL6_VOTE 251 -#define PLL8 252 -#define PLL8_VOTE 253 -#define PLL9 254 -#define PLL10 255 -#define PLL11 256 -#define PLL12 257 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h deleted file mode 100644 index 7d20eed..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H -#define _DT_BINDINGS_CLK_MSM_GCC_8960_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SFAB_MSS_Q6_SW_A_CLK 2 -#define SFAB_MSS_Q6_FW_A_CLK 3 -#define QDSS_STM_CLK 4 -#define SCSS_A_CLK 5 -#define SCSS_H_CLK 6 -#define SCSS_XO_SRC_CLK 7 -#define AFAB_EBI1_CH0_A_CLK 8 -#define AFAB_EBI1_CH1_A_CLK 9 -#define AFAB_AXI_S0_FCLK 10 -#define AFAB_AXI_S1_FCLK 11 -#define AFAB_AXI_S2_FCLK 12 -#define AFAB_AXI_S3_FCLK 13 -#define AFAB_AXI_S4_FCLK 14 -#define SFAB_CORE_CLK 15 -#define SFAB_AXI_S0_FCLK 16 -#define SFAB_AXI_S1_FCLK 17 -#define SFAB_AXI_S2_FCLK 18 -#define SFAB_AXI_S3_FCLK 19 -#define SFAB_AXI_S4_FCLK 20 -#define SFAB_AHB_S0_FCLK 21 -#define SFAB_AHB_S1_FCLK 22 -#define SFAB_AHB_S2_FCLK 23 -#define SFAB_AHB_S3_FCLK 24 -#define SFAB_AHB_S4_FCLK 25 -#define SFAB_AHB_S5_FCLK 26 -#define SFAB_AHB_S6_FCLK 27 -#define SFAB_AHB_S7_FCLK 28 -#define QDSS_AT_CLK_SRC 29 -#define QDSS_AT_CLK 30 -#define QDSS_TRACECLKIN_CLK_SRC 31 -#define QDSS_TRACECLKIN_CLK 32 -#define QDSS_TSCTR_CLK_SRC 33 -#define QDSS_TSCTR_CLK 34 -#define SFAB_ADM0_M0_A_CLK 35 -#define SFAB_ADM0_M1_A_CLK 36 -#define SFAB_ADM0_M2_H_CLK 37 -#define ADM0_CLK 38 -#define ADM0_PBUS_CLK 39 -#define MSS_XPU_CLK 40 -#define IMEM0_A_CLK 41 -#define QDSS_H_CLK 42 -#define PCIE_A_CLK 43 -#define PCIE_AUX_CLK 44 -#define PCIE_PHY_REF_CLK 45 -#define PCIE_H_CLK 46 -#define SFAB_CLK_SRC 47 -#define MAHB0_CLK 48 -#define Q6SW_CLK_SRC 49 -#define Q6SW_CLK 50 -#define Q6FW_CLK_SRC 51 -#define Q6FW_CLK 52 -#define SFAB_MSS_M_A_CLK 53 -#define SFAB_USB3_M_A_CLK 54 -#define SFAB_LPASS_Q6_A_CLK 55 -#define SFAB_AFAB_M_A_CLK 56 -#define AFAB_SFAB_M0_A_CLK 57 -#define AFAB_SFAB_M1_A_CLK 58 -#define SFAB_SATA_S_H_CLK 59 -#define DFAB_CLK_SRC 60 -#define DFAB_CLK 61 -#define SFAB_DFAB_M_A_CLK 62 -#define DFAB_SFAB_M_A_CLK 63 -#define DFAB_SWAY0_H_CLK 64 -#define DFAB_SWAY1_H_CLK 65 -#define DFAB_ARB0_H_CLK 66 -#define DFAB_ARB1_H_CLK 67 -#define PPSS_H_CLK 68 -#define PPSS_PROC_CLK 69 -#define PPSS_TIMER0_CLK 70 -#define PPSS_TIMER1_CLK 71 -#define PMEM_A_CLK 72 -#define DMA_BAM_H_CLK 73 -#define SIC_H_CLK 74 -#define SPS_TIC_H_CLK 75 -#define SLIMBUS_H_CLK 76 -#define SLIMBUS_XO_SRC_CLK 77 -#define CFPB_2X_CLK_SRC 78 -#define CFPB_CLK 79 -#define CFPB0_H_CLK 80 -#define CFPB1_H_CLK 81 -#define CFPB2_H_CLK 82 -#define SFAB_CFPB_M_H_CLK 83 -#define CFPB_MASTER_H_CLK 84 -#define SFAB_CFPB_S_H_CLK 85 -#define CFPB_SPLITTER_H_CLK 86 -#define TSIF_H_CLK 87 -#define TSIF_INACTIVITY_TIMERS_CLK 88 -#define TSIF_REF_SRC 89 -#define TSIF_REF_CLK 90 -#define CE1_H_CLK 91 -#define CE1_CORE_CLK 92 -#define CE1_SLEEP_CLK 93 -#define CE2_H_CLK 94 -#define CE2_CORE_CLK 95 -#define SFPB_H_CLK_SRC 97 -#define SFPB_H_CLK 98 -#define SFAB_SFPB_M_H_CLK 99 -#define SFAB_SFPB_S_H_CLK 100 -#define RPM_PROC_CLK 101 -#define RPM_BUS_H_CLK 102 -#define RPM_SLEEP_CLK 103 -#define RPM_TIMER_CLK 104 -#define RPM_MSG_RAM_H_CLK 105 -#define PMIC_ARB0_H_CLK 106 -#define PMIC_ARB1_H_CLK 107 -#define PMIC_SSBI2_SRC 108 -#define PMIC_SSBI2_CLK 109 -#define SDC1_H_CLK 110 -#define SDC2_H_CLK 111 -#define SDC3_H_CLK 112 -#define SDC4_H_CLK 113 -#define SDC5_H_CLK 114 -#define SDC1_SRC 115 -#define SDC2_SRC 116 -#define SDC3_SRC 117 -#define SDC4_SRC 118 -#define SDC5_SRC 119 -#define SDC1_CLK 120 -#define SDC2_CLK 121 -#define SDC3_CLK 122 -#define SDC4_CLK 123 -#define SDC5_CLK 124 -#define DFAB_A2_H_CLK 125 -#define USB_HS1_H_CLK 126 -#define USB_HS1_XCVR_SRC 127 -#define USB_HS1_XCVR_CLK 128 -#define USB_HSIC_H_CLK 129 -#define USB_HSIC_XCVR_FS_SRC 130 -#define USB_HSIC_XCVR_FS_CLK 131 -#define USB_HSIC_SYSTEM_CLK_SRC 132 -#define USB_HSIC_SYSTEM_CLK 133 -#define CFPB0_C0_H_CLK 134 -#define CFPB0_C1_H_CLK 135 -#define CFPB0_D0_H_CLK 136 -#define CFPB0_D1_H_CLK 137 -#define USB_FS1_H_CLK 138 -#define USB_FS1_XCVR_FS_SRC 139 -#define USB_FS1_XCVR_FS_CLK 140 -#define USB_FS1_SYSTEM_CLK 141 -#define USB_FS2_H_CLK 142 -#define USB_FS2_XCVR_FS_SRC 143 -#define USB_FS2_XCVR_FS_CLK 144 -#define USB_FS2_SYSTEM_CLK 145 -#define GSBI_COMMON_SIM_SRC 146 -#define GSBI1_H_CLK 147 -#define GSBI2_H_CLK 148 -#define GSBI3_H_CLK 149 -#define GSBI4_H_CLK 150 -#define GSBI5_H_CLK 151 -#define GSBI6_H_CLK 152 -#define GSBI7_H_CLK 153 -#define GSBI8_H_CLK 154 -#define GSBI9_H_CLK 155 -#define GSBI10_H_CLK 156 -#define GSBI11_H_CLK 157 -#define GSBI12_H_CLK 158 -#define GSBI1_UART_SRC 159 -#define GSBI1_UART_CLK 160 -#define GSBI2_UART_SRC 161 -#define GSBI2_UART_CLK 162 -#define GSBI3_UART_SRC 163 -#define GSBI3_UART_CLK 164 -#define GSBI4_UART_SRC 165 -#define GSBI4_UART_CLK 166 -#define GSBI5_UART_SRC 167 -#define GSBI5_UART_CLK 168 -#define GSBI6_UART_SRC 169 -#define GSBI6_UART_CLK 170 -#define GSBI7_UART_SRC 171 -#define GSBI7_UART_CLK 172 -#define GSBI8_UART_SRC 173 -#define GSBI8_UART_CLK 174 -#define GSBI9_UART_SRC 175 -#define GSBI9_UART_CLK 176 -#define GSBI10_UART_SRC 177 -#define GSBI10_UART_CLK 178 -#define GSBI11_UART_SRC 179 -#define GSBI11_UART_CLK 180 -#define GSBI12_UART_SRC 181 -#define GSBI12_UART_CLK 182 -#define GSBI1_QUP_SRC 183 -#define GSBI1_QUP_CLK 184 -#define GSBI2_QUP_SRC 185 -#define GSBI2_QUP_CLK 186 -#define GSBI3_QUP_SRC 187 -#define GSBI3_QUP_CLK 188 -#define GSBI4_QUP_SRC 189 -#define GSBI4_QUP_CLK 190 -#define GSBI5_QUP_SRC 191 -#define GSBI5_QUP_CLK 192 -#define GSBI6_QUP_SRC 193 -#define GSBI6_QUP_CLK 194 -#define GSBI7_QUP_SRC 195 -#define GSBI7_QUP_CLK 196 -#define GSBI8_QUP_SRC 197 -#define GSBI8_QUP_CLK 198 -#define GSBI9_QUP_SRC 199 -#define GSBI9_QUP_CLK 200 -#define GSBI10_QUP_SRC 201 -#define GSBI10_QUP_CLK 202 -#define GSBI11_QUP_SRC 203 -#define GSBI11_QUP_CLK 204 -#define GSBI12_QUP_SRC 205 -#define GSBI12_QUP_CLK 206 -#define GSBI1_SIM_CLK 207 -#define GSBI2_SIM_CLK 208 -#define GSBI3_SIM_CLK 209 -#define GSBI4_SIM_CLK 210 -#define GSBI5_SIM_CLK 211 -#define GSBI6_SIM_CLK 212 -#define GSBI7_SIM_CLK 213 -#define GSBI8_SIM_CLK 214 -#define GSBI9_SIM_CLK 215 -#define GSBI10_SIM_CLK 216 -#define GSBI11_SIM_CLK 217 -#define GSBI12_SIM_CLK 218 -#define USB_HSIC_HSIC_CLK_SRC 219 -#define USB_HSIC_HSIC_CLK 220 -#define USB_HSIC_HSIO_CAL_CLK 221 -#define SPDM_CFG_H_CLK 222 -#define SPDM_MSTR_H_CLK 223 -#define SPDM_FF_CLK_SRC 224 -#define SPDM_FF_CLK 225 -#define SEC_CTRL_CLK 226 -#define SEC_CTRL_ACC_CLK_SRC 227 -#define SEC_CTRL_ACC_CLK 228 -#define TLMM_H_CLK 229 -#define TLMM_CLK 230 -#define SFAB_MSS_S_H_CLK 231 -#define MSS_SLP_CLK 232 -#define MSS_Q6SW_JTAG_CLK 233 -#define MSS_Q6FW_JTAG_CLK 234 -#define MSS_S_H_CLK 235 -#define MSS_CXO_SRC_CLK 236 -#define SATA_H_CLK 237 -#define SATA_CLK_SRC 238 -#define SATA_RXOOB_CLK 239 -#define SATA_PMALIVE_CLK 240 -#define SATA_PHY_REF_CLK 241 -#define TSSC_CLK_SRC 242 -#define TSSC_CLK 243 -#define PDM_SRC 244 -#define PDM_CLK 245 -#define GP0_SRC 246 -#define GP0_CLK 247 -#define GP1_SRC 248 -#define GP1_CLK 249 -#define GP2_SRC 250 -#define GP2_CLK 251 -#define MPM_CLK 252 -#define EBI1_CLK_SRC 253 -#define EBI1_CH0_CLK 254 -#define EBI1_CH1_CLK 255 -#define EBI1_2X_CLK 256 -#define EBI1_CH0_DQ_CLK 257 -#define EBI1_CH1_DQ_CLK 258 -#define EBI1_CH0_CA_CLK 259 -#define EBI1_CH1_CA_CLK 260 -#define EBI1_XO_CLK 261 -#define SFAB_SMPSS_S_H_CLK 262 -#define PRNG_SRC 263 -#define PRNG_CLK 264 -#define PXO_SRC 265 -#define LPASS_CXO_CLK 266 -#define LPASS_PXO_CLK 267 -#define SPDM_CY_PORT0_CLK 268 -#define SPDM_CY_PORT1_CLK 269 -#define SPDM_CY_PORT2_CLK 270 -#define SPDM_CY_PORT3_CLK 271 -#define SPDM_CY_PORT4_CLK 272 -#define SPDM_CY_PORT5_CLK 273 -#define SPDM_CY_PORT6_CLK 274 -#define SPDM_CY_PORT7_CLK 275 -#define PLL0 276 -#define PLL0_VOTE 277 -#define PLL3 278 -#define PLL3_VOTE 279 -#define PLL4_VOTE 280 -#define PLL5 281 -#define PLL5_VOTE 282 -#define PLL6 283 -#define PLL6_VOTE 284 -#define PLL7_VOTE 285 -#define PLL8 286 -#define PLL8_VOTE 287 -#define PLL9 288 -#define PLL10 289 -#define PLL11 290 -#define PLL12 291 -#define PLL13 292 -#define PLL14 293 -#define PLL14_VOTE 294 -#define USB_HS3_H_CLK 295 -#define USB_HS3_XCVR_SRC 296 -#define USB_HS3_XCVR_CLK 297 -#define USB_HS4_H_CLK 298 -#define USB_HS4_XCVR_SRC 299 -#define USB_HS4_XCVR_CLK 300 -#define SATA_PHY_CFG_CLK 301 -#define SATA_A_CLK 302 -#define CE3_SRC 303 -#define CE3_CORE_CLK 304 -#define CE3_H_CLK 305 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h deleted file mode 100644 index 51e51c8..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H -#define _DT_BINDINGS_CLK_MSM_GCC_8974_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define CONFIG_NOC_CLK_SRC 2 -#define GPLL2 3 -#define GPLL2_VOTE 4 -#define GPLL3 5 -#define GPLL3_VOTE 6 -#define PERIPH_NOC_CLK_SRC 7 -#define BLSP_UART_SIM_CLK_SRC 8 -#define QDSS_TSCTR_CLK_SRC 9 -#define BIMC_DDR_CLK_SRC 10 -#define SYSTEM_NOC_CLK_SRC 11 -#define GPLL1 12 -#define GPLL1_VOTE 13 -#define RPM_CLK_SRC 14 -#define GCC_BIMC_CLK 15 -#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define USB30_MASTER_CLK_SRC 19 -#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 -#define QDSS_STM_CLK_SRC 21 -#define ACC_CLK_SRC 22 -#define SEC_CTRL_CLK_SRC 23 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 -#define BLSP1_UART1_APPS_CLK_SRC 36 -#define BLSP1_UART2_APPS_CLK_SRC 37 -#define BLSP1_UART3_APPS_CLK_SRC 38 -#define BLSP1_UART4_APPS_CLK_SRC 39 -#define BLSP1_UART5_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 -#define BLSP2_UART1_APPS_CLK_SRC 54 -#define BLSP2_UART2_APPS_CLK_SRC 55 -#define BLSP2_UART3_APPS_CLK_SRC 56 -#define BLSP2_UART4_APPS_CLK_SRC 57 -#define BLSP2_UART5_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define CE1_CLK_SRC 60 -#define CE2_CLK_SRC 61 -#define GP1_CLK_SRC 62 -#define GP2_CLK_SRC 63 -#define GP3_CLK_SRC 64 -#define PDM2_CLK_SRC 65 -#define QDSS_TRACECLKIN_CLK_SRC 66 -#define RBCPR_CLK_SRC 67 -#define SDCC1_APPS_CLK_SRC 68 -#define SDCC2_APPS_CLK_SRC 69 -#define SDCC3_APPS_CLK_SRC 70 -#define SDCC4_APPS_CLK_SRC 71 -#define SPMI_AHB_CLK_SRC 72 -#define SPMI_SER_CLK_SRC 73 -#define TSIF_REF_CLK_SRC 74 -#define USB30_MOCK_UTMI_CLK_SRC 75 -#define USB_HS_SYSTEM_CLK_SRC 76 -#define USB_HSIC_CLK_SRC 77 -#define USB_HSIC_IO_CAL_CLK_SRC 78 -#define USB_HSIC_SYSTEM_CLK_SRC 79 -#define GCC_BAM_DMA_AHB_CLK 80 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 -#define GCC_BIMC_CFG_AHB_CLK 82 -#define GCC_BIMC_KPSS_AXI_CLK 83 -#define GCC_BIMC_SLEEP_CLK 84 -#define GCC_BIMC_SYSNOC_AXI_CLK 85 -#define GCC_BIMC_XO_CLK 86 -#define GCC_BLSP1_AHB_CLK 87 -#define GCC_BLSP1_SLEEP_CLK 88 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 -#define GCC_BLSP1_UART1_APPS_CLK 101 -#define GCC_BLSP1_UART1_SIM_CLK 102 -#define GCC_BLSP1_UART2_APPS_CLK 103 -#define GCC_BLSP1_UART2_SIM_CLK 104 -#define GCC_BLSP1_UART3_APPS_CLK 105 -#define GCC_BLSP1_UART3_SIM_CLK 106 -#define GCC_BLSP1_UART4_APPS_CLK 107 -#define GCC_BLSP1_UART4_SIM_CLK 108 -#define GCC_BLSP1_UART5_APPS_CLK 109 -#define GCC_BLSP1_UART5_SIM_CLK 110 -#define GCC_BLSP1_UART6_APPS_CLK 111 -#define GCC_BLSP1_UART6_SIM_CLK 112 -#define GCC_BLSP2_AHB_CLK 113 -#define GCC_BLSP2_SLEEP_CLK 114 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP2_UART1_APPS_CLK 127 -#define GCC_BLSP2_UART1_SIM_CLK 128 -#define GCC_BLSP2_UART2_APPS_CLK 129 -#define GCC_BLSP2_UART2_SIM_CLK 130 -#define GCC_BLSP2_UART3_APPS_CLK 131 -#define GCC_BLSP2_UART3_SIM_CLK 132 -#define GCC_BLSP2_UART4_APPS_CLK 133 -#define GCC_BLSP2_UART4_SIM_CLK 134 -#define GCC_BLSP2_UART5_APPS_CLK 135 -#define GCC_BLSP2_UART5_SIM_CLK 136 -#define GCC_BLSP2_UART6_APPS_CLK 137 -#define GCC_BLSP2_UART6_SIM_CLK 138 -#define GCC_BOOT_ROM_AHB_CLK 139 -#define GCC_CE1_AHB_CLK 140 -#define GCC_CE1_AXI_CLK 141 -#define GCC_CE1_CLK 142 -#define GCC_CE2_AHB_CLK 143 -#define GCC_CE2_AXI_CLK 144 -#define GCC_CE2_CLK 145 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 -#define GCC_CFG_NOC_AHB_CLK 153 -#define GCC_CFG_NOC_DDR_CFG_CLK 154 -#define GCC_CFG_NOC_RPM_AHB_CLK 155 -#define GCC_BIMC_DDR_CPLL0_CLK 156 -#define GCC_BIMC_DDR_CPLL1_CLK 157 -#define GCC_DDR_DIM_CFG_CLK 158 -#define GCC_DDR_DIM_SLEEP_CLK 159 -#define GCC_DEHR_CLK 160 -#define GCC_AHB_CLK 161 -#define GCC_IM_SLEEP_CLK 162 -#define GCC_XO_CLK 163 -#define GCC_XO_DIV4_CLK 164 -#define GCC_GP1_CLK 165 -#define GCC_GP2_CLK 166 -#define GCC_GP3_CLK 167 -#define GCC_IMEM_AXI_CLK 168 -#define GCC_IMEM_CFG_AHB_CLK 169 -#define GCC_KPSS_AHB_CLK 170 -#define GCC_KPSS_AXI_CLK 171 -#define GCC_LPASS_Q6_AXI_CLK 172 -#define GCC_MMSS_NOC_AT_CLK 173 -#define GCC_MMSS_NOC_CFG_AHB_CLK 174 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 -#define GCC_MPM_AHB_CLK 177 -#define GCC_MSG_RAM_AHB_CLK 178 -#define GCC_MSS_CFG_AHB_CLK 179 -#define GCC_MSS_Q6_BIMC_AXI_CLK 180 -#define GCC_NOC_CONF_XPU_AHB_CLK 181 -#define GCC_PDM2_CLK 182 -#define GCC_PDM_AHB_CLK 183 -#define GCC_PDM_XO4_CLK 184 -#define GCC_PERIPH_NOC_AHB_CLK 185 -#define GCC_PERIPH_NOC_AT_CLK 186 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 -#define GCC_PERIPH_XPU_AHB_CLK 189 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 -#define GCC_PRNG_AHB_CLK 195 -#define GCC_QDSS_AT_CLK 196 -#define GCC_QDSS_CFG_AHB_CLK 197 -#define GCC_QDSS_DAP_AHB_CLK 198 -#define GCC_QDSS_DAP_CLK 199 -#define GCC_QDSS_ETR_USB_CLK 200 -#define GCC_QDSS_STM_CLK 201 -#define GCC_QDSS_TRACECLKIN_CLK 202 -#define GCC_QDSS_TSCTR_DIV16_CLK 203 -#define GCC_QDSS_TSCTR_DIV2_CLK 204 -#define GCC_QDSS_TSCTR_DIV3_CLK 205 -#define GCC_QDSS_TSCTR_DIV4_CLK 206 -#define GCC_QDSS_TSCTR_DIV8_CLK 207 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 -#define GCC_RBCPR_AHB_CLK 209 -#define GCC_RBCPR_CLK 210 -#define GCC_RPM_BUS_AHB_CLK 211 -#define GCC_RPM_PROC_HCLK 212 -#define GCC_RPM_SLEEP_CLK 213 -#define GCC_RPM_TIMER_CLK 214 -#define GCC_SDCC1_AHB_CLK 215 -#define GCC_SDCC1_APPS_CLK 216 -#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 -#define GCC_SDCC2_AHB_CLK 218 -#define GCC_SDCC2_APPS_CLK 219 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 -#define GCC_SDCC3_AHB_CLK 221 -#define GCC_SDCC3_APPS_CLK 222 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 -#define GCC_SDCC4_AHB_CLK 224 -#define GCC_SDCC4_APPS_CLK 225 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 -#define GCC_SEC_CTRL_ACC_CLK 227 -#define GCC_SEC_CTRL_AHB_CLK 228 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 -#define GCC_SEC_CTRL_CLK 230 -#define GCC_SEC_CTRL_SENSE_CLK 231 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 -#define GCC_SPDM_BIMC_CY_CLK 234 -#define GCC_SPDM_CFG_AHB_CLK 235 -#define GCC_SPDM_DEBUG_CY_CLK 236 -#define GCC_SPDM_FF_CLK 237 -#define GCC_SPDM_MSTR_AHB_CLK 238 -#define GCC_SPDM_PNOC_CY_CLK 239 -#define GCC_SPDM_RPM_CY_CLK 240 -#define GCC_SPDM_SNOC_CY_CLK 241 -#define GCC_SPMI_AHB_CLK 242 -#define GCC_SPMI_CNOC_AHB_CLK 243 -#define GCC_SPMI_SER_CLK 244 -#define GCC_SNOC_CNOC_AHB_CLK 245 -#define GCC_SNOC_PNOC_AHB_CLK 246 -#define GCC_SYS_NOC_AT_CLK 247 -#define GCC_SYS_NOC_AXI_CLK 248 -#define GCC_SYS_NOC_KPSS_AHB_CLK 249 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 -#define GCC_SYS_NOC_USB3_AXI_CLK 251 -#define GCC_TCSR_AHB_CLK 252 -#define GCC_TLMM_AHB_CLK 253 -#define GCC_TLMM_CLK 254 -#define GCC_TSIF_AHB_CLK 255 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 -#define GCC_TSIF_REF_CLK 257 -#define GCC_USB2A_PHY_SLEEP_CLK 258 -#define GCC_USB2B_PHY_SLEEP_CLK 259 -#define GCC_USB30_MASTER_CLK 260 -#define GCC_USB30_MOCK_UTMI_CLK 261 -#define GCC_USB30_SLEEP_CLK 262 -#define GCC_USB_HS_AHB_CLK 263 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 -#define GCC_USB_HS_SYSTEM_CLK 265 -#define GCC_USB_HSIC_AHB_CLK 266 -#define GCC_USB_HSIC_CLK 267 -#define GCC_USB_HSIC_IO_CAL_CLK 268 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 -#define GCC_USB_HSIC_SYSTEM_CLK 270 -#define GCC_WCSS_GPLL1_CLK_SRC 271 -#define GCC_MMSS_GPLL0_CLK_SRC 272 -#define GCC_LPASS_GPLL0_CLK_SRC 273 -#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 -#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 -#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 -#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 -#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 -#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 -#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 -#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 -#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 -#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 -#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 -#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 -#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 -#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 -#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 -#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 -#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 -#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 -#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 -#define GCC_TLMM_CLK_SLEEP_ENA 294 -#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 -#define GCC_CE1_CLK_SLEEP_ENA 296 -#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 -#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 -#define GCC_CE2_CLK_SLEEP_ENA 299 -#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 -#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 -#define GPLL4 302 -#define GPLL4_VOTE 303 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 -#define GCC_SDCC1_CDCCAL_FF_CLK 305 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h deleted file mode 100644 index 4e944b8..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H -#define _DT_BINDINGS_CLK_LCC_IPQ806X_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SPDIF_SRC 9 -#define SPDIF_CLK 10 -#define AHBIX_CLK 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h deleted file mode 100644 index 4fb2aa6..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H -#define _DT_BINDINGS_CLK_LCC_MSM8960_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h deleted file mode 100644 index d72b5b3..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H -#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define MMPLL4 8 -#define CSI0_CLK_SRC 9 -#define CSI1_CLK_SRC 10 -#define CSI2_CLK_SRC 11 -#define CSI3_CLK_SRC 12 -#define VCODEC0_CLK_SRC 13 -#define VFE0_CLK_SRC 14 -#define VFE1_CLK_SRC 15 -#define MDP_CLK_SRC 16 -#define PCLK0_CLK_SRC 17 -#define PCLK1_CLK_SRC 18 -#define OCMEMNOC_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define JPEG0_CLK_SRC 21 -#define JPEG1_CLK_SRC 22 -#define JPEG2_CLK_SRC 23 -#define EDPPIXEL_CLK_SRC 24 -#define EXTPCLK_CLK_SRC 25 -#define VP_CLK_SRC 26 -#define CCI_CLK_SRC 27 -#define CAMSS_GP0_CLK_SRC 28 -#define CAMSS_GP1_CLK_SRC 29 -#define MCLK0_CLK_SRC 30 -#define MCLK1_CLK_SRC 31 -#define MCLK2_CLK_SRC 32 -#define MCLK3_CLK_SRC 33 -#define CSI0PHYTIMER_CLK_SRC 34 -#define CSI1PHYTIMER_CLK_SRC 35 -#define CSI2PHYTIMER_CLK_SRC 36 -#define CPP_CLK_SRC 37 -#define BYTE0_CLK_SRC 38 -#define BYTE1_CLK_SRC 39 -#define EDPAUX_CLK_SRC 40 -#define EDPLINK_CLK_SRC 41 -#define ESC0_CLK_SRC 42 -#define ESC1_CLK_SRC 43 -#define HDMI_CLK_SRC 44 -#define VSYNC_CLK_SRC 45 -#define MMSS_RBCPR_CLK_SRC 46 -#define RBBMTIMER_CLK_SRC 47 -#define MAPLE_CLK_SRC 48 -#define VDP_CLK_SRC 49 -#define VPU_BUS_CLK_SRC 50 -#define MMSS_CXO_CLK 51 -#define MMSS_SLEEPCLK_CLK 52 -#define AVSYNC_AHB_CLK 53 -#define AVSYNC_EDPPIXEL_CLK 54 -#define AVSYNC_EXTPCLK_CLK 55 -#define AVSYNC_PCLK0_CLK 56 -#define AVSYNC_PCLK1_CLK 57 -#define AVSYNC_VP_CLK 58 -#define CAMSS_AHB_CLK 59 -#define CAMSS_CCI_CCI_AHB_CLK 60 -#define CAMSS_CCI_CCI_CLK 61 -#define CAMSS_CSI0_AHB_CLK 62 -#define CAMSS_CSI0_CLK 63 -#define CAMSS_CSI0PHY_CLK 64 -#define CAMSS_CSI0PIX_CLK 65 -#define CAMSS_CSI0RDI_CLK 66 -#define CAMSS_CSI1_AHB_CLK 67 -#define CAMSS_CSI1_CLK 68 -#define CAMSS_CSI1PHY_CLK 69 -#define CAMSS_CSI1PIX_CLK 70 -#define CAMSS_CSI1RDI_CLK 71 -#define CAMSS_CSI2_AHB_CLK 72 -#define CAMSS_CSI2_CLK 73 -#define CAMSS_CSI2PHY_CLK 74 -#define CAMSS_CSI2PIX_CLK 75 -#define CAMSS_CSI2RDI_CLK 76 -#define CAMSS_CSI3_AHB_CLK 77 -#define CAMSS_CSI3_CLK 78 -#define CAMSS_CSI3PHY_CLK 79 -#define CAMSS_CSI3PIX_CLK 80 -#define CAMSS_CSI3RDI_CLK 81 -#define CAMSS_CSI_VFE0_CLK 82 -#define CAMSS_CSI_VFE1_CLK 83 -#define CAMSS_GP0_CLK 84 -#define CAMSS_GP1_CLK 85 -#define CAMSS_ISPIF_AHB_CLK 86 -#define CAMSS_JPEG_JPEG0_CLK 87 -#define CAMSS_JPEG_JPEG1_CLK 88 -#define CAMSS_JPEG_JPEG2_CLK 89 -#define CAMSS_JPEG_JPEG_AHB_CLK 90 -#define CAMSS_JPEG_JPEG_AXI_CLK 91 -#define CAMSS_MCLK0_CLK 92 -#define CAMSS_MCLK1_CLK 93 -#define CAMSS_MCLK2_CLK 94 -#define CAMSS_MCLK3_CLK 95 -#define CAMSS_MICRO_AHB_CLK 96 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 -#define CAMSS_TOP_AHB_CLK 100 -#define CAMSS_VFE_CPP_AHB_CLK 101 -#define CAMSS_VFE_CPP_CLK 102 -#define CAMSS_VFE_VFE0_CLK 103 -#define CAMSS_VFE_VFE1_CLK 104 -#define CAMSS_VFE_VFE_AHB_CLK 105 -#define CAMSS_VFE_VFE_AXI_CLK 106 -#define MDSS_AHB_CLK 107 -#define MDSS_AXI_CLK 108 -#define MDSS_BYTE0_CLK 109 -#define MDSS_BYTE1_CLK 110 -#define MDSS_EDPAUX_CLK 111 -#define MDSS_EDPLINK_CLK 112 -#define MDSS_EDPPIXEL_CLK 113 -#define MDSS_ESC0_CLK 114 -#define MDSS_ESC1_CLK 115 -#define MDSS_EXTPCLK_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_HDMI_CLK 118 -#define MDSS_MDP_CLK 119 -#define MDSS_MDP_LUT_CLK 120 -#define MDSS_PCLK0_CLK 121 -#define MDSS_PCLK1_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MMSS_RBCPR_AHB_CLK 124 -#define MMSS_RBCPR_CLK 125 -#define MMSS_SPDM_AHB_CLK 126 -#define MMSS_SPDM_AXI_CLK 127 -#define MMSS_SPDM_CSI0_CLK 128 -#define MMSS_SPDM_GFX3D_CLK 129 -#define MMSS_SPDM_JPEG0_CLK 130 -#define MMSS_SPDM_JPEG1_CLK 131 -#define MMSS_SPDM_JPEG2_CLK 132 -#define MMSS_SPDM_MDP_CLK 133 -#define MMSS_SPDM_PCLK0_CLK 134 -#define MMSS_SPDM_PCLK1_CLK 135 -#define MMSS_SPDM_VCODEC0_CLK 136 -#define MMSS_SPDM_VFE0_CLK 137 -#define MMSS_SPDM_VFE1_CLK 138 -#define MMSS_SPDM_RM_AXI_CLK 139 -#define MMSS_SPDM_RM_OCMEMNOC_CLK 140 -#define MMSS_MISC_AHB_CLK 141 -#define MMSS_MMSSNOC_AHB_CLK 142 -#define MMSS_MMSSNOC_BTO_AHB_CLK 143 -#define MMSS_MMSSNOC_AXI_CLK 144 -#define MMSS_S0_AXI_CLK 145 -#define OCMEMCX_AHB_CLK 146 -#define OCMEMCX_OCMEMNOC_CLK 147 -#define OXILI_OCMEMGX_CLK 148 -#define OXILI_GFX3D_CLK 149 -#define OXILI_RBBMTIMER_CLK 150 -#define OXILICX_AHB_CLK 151 -#define VENUS0_AHB_CLK 152 -#define VENUS0_AXI_CLK 153 -#define VENUS0_CORE0_VCODEC_CLK 154 -#define VENUS0_CORE1_VCODEC_CLK 155 -#define VENUS0_OCMEMNOC_CLK 156 -#define VENUS0_VCODEC0_CLK 157 -#define VPU_AHB_CLK 158 -#define VPU_AXI_CLK 159 -#define VPU_BUS_CLK 160 -#define VPU_CXO_CLK 161 -#define VPU_MAPLE_CLK 162 -#define VPU_SLEEP_CLK 163 -#define VPU_VDP_CLK 164 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h deleted file mode 100644 index 85041b2..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H - -#define MMSS_AHB_SRC 0 -#define FAB_AHB_CLK 1 -#define APU_AHB_CLK 2 -#define TV_ENC_AHB_CLK 3 -#define AMP_AHB_CLK 4 -#define DSI2_S_AHB_CLK 5 -#define JPEGD_AHB_CLK 6 -#define GFX2D0_AHB_CLK 7 -#define DSI_S_AHB_CLK 8 -#define DSI2_M_AHB_CLK 9 -#define VPE_AHB_CLK 10 -#define SMMU_AHB_CLK 11 -#define HDMI_M_AHB_CLK 12 -#define VFE_AHB_CLK 13 -#define ROT_AHB_CLK 14 -#define VCODEC_AHB_CLK 15 -#define MDP_AHB_CLK 16 -#define DSI_M_AHB_CLK 17 -#define CSI_AHB_CLK 18 -#define MMSS_IMEM_AHB_CLK 19 -#define IJPEG_AHB_CLK 20 -#define HDMI_S_AHB_CLK 21 -#define GFX3D_AHB_CLK 22 -#define GFX2D1_AHB_CLK 23 -#define MMSS_FPB_CLK 24 -#define MMSS_AXI_SRC 25 -#define MMSS_FAB_CORE 26 -#define FAB_MSP_AXI_CLK 27 -#define JPEGD_AXI_CLK 28 -#define GMEM_AXI_CLK 29 -#define MDP_AXI_CLK 30 -#define MMSS_IMEM_AXI_CLK 31 -#define IJPEG_AXI_CLK 32 -#define GFX3D_AXI_CLK 33 -#define VCODEC_AXI_CLK 34 -#define VFE_AXI_CLK 35 -#define VPE_AXI_CLK 36 -#define ROT_AXI_CLK 37 -#define VCODEC_AXI_A_CLK 38 -#define VCODEC_AXI_B_CLK 39 -#define MM_AXI_S3_FCLK 40 -#define MM_AXI_S2_FCLK 41 -#define MM_AXI_S1_FCLK 42 -#define MM_AXI_S0_FCLK 43 -#define MM_AXI_S2_CLK 44 -#define MM_AXI_S1_CLK 45 -#define MM_AXI_S0_CLK 46 -#define CSI0_SRC 47 -#define CSI0_CLK 48 -#define CSI0_PHY_CLK 49 -#define CSI1_SRC 50 -#define CSI1_CLK 51 -#define CSI1_PHY_CLK 52 -#define CSI2_SRC 53 -#define CSI2_CLK 54 -#define CSI2_PHY_CLK 55 -#define DSI_SRC 56 -#define DSI_CLK 57 -#define CSI_PIX_CLK 58 -#define CSI_RDI_CLK 59 -#define MDP_VSYNC_CLK 60 -#define HDMI_DIV_CLK 61 -#define HDMI_APP_CLK 62 -#define CSI_PIX1_CLK 63 -#define CSI_RDI2_CLK 64 -#define CSI_RDI1_CLK 65 -#define GFX2D0_SRC 66 -#define GFX2D0_CLK 67 -#define GFX2D1_SRC 68 -#define GFX2D1_CLK 69 -#define GFX3D_SRC 70 -#define GFX3D_CLK 71 -#define IJPEG_SRC 72 -#define IJPEG_CLK 73 -#define JPEGD_SRC 74 -#define JPEGD_CLK 75 -#define MDP_SRC 76 -#define MDP_CLK 77 -#define MDP_LUT_CLK 78 -#define DSI2_PIXEL_SRC 79 -#define DSI2_PIXEL_CLK 80 -#define DSI2_SRC 81 -#define DSI2_CLK 82 -#define DSI1_BYTE_SRC 83 -#define DSI1_BYTE_CLK 84 -#define DSI2_BYTE_SRC 85 -#define DSI2_BYTE_CLK 86 -#define DSI1_ESC_SRC 87 -#define DSI1_ESC_CLK 88 -#define DSI2_ESC_SRC 89 -#define DSI2_ESC_CLK 90 -#define ROT_SRC 91 -#define ROT_CLK 92 -#define TV_ENC_CLK 93 -#define TV_DAC_CLK 94 -#define HDMI_TV_CLK 95 -#define MDP_TV_CLK 96 -#define TV_SRC 97 -#define VCODEC_SRC 98 -#define VCODEC_CLK 99 -#define VFE_SRC 100 -#define VFE_CLK 101 -#define VFE_CSI_CLK 102 -#define VPE_SRC 103 -#define VPE_CLK 104 -#define DSI_PIXEL_SRC 105 -#define DSI_PIXEL_CLK 106 -#define CAMCLK0_SRC 107 -#define CAMCLK0_CLK 108 -#define CAMCLK1_SRC 109 -#define CAMCLK1_CLK 110 -#define CAMCLK2_SRC 111 -#define CAMCLK2_CLK 112 -#define CSIPHYTIMER_SRC 113 -#define CSIPHY2_TIMER_CLK 114 -#define CSIPHY1_TIMER_CLK 115 -#define CSIPHY0_TIMER_CLK 116 -#define PLL1 117 -#define PLL2 118 -#define RGB_TV_CLK 119 -#define NPL_TV_CLK 120 -#define VCAP_AHB_CLK 121 -#define VCAP_AXI_CLK 122 -#define VCAP_SRC 123 -#define VCAP_CLK 124 -#define VCAP_NPL_CLK 125 -#define PLL15 126 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h deleted file mode 100644 index 032ed87..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define CSI0_CLK_SRC 8 -#define CSI1_CLK_SRC 9 -#define CSI2_CLK_SRC 10 -#define CSI3_CLK_SRC 11 -#define VFE0_CLK_SRC 12 -#define VFE1_CLK_SRC 13 -#define MDP_CLK_SRC 14 -#define GFX3D_CLK_SRC 15 -#define JPEG0_CLK_SRC 16 -#define JPEG1_CLK_SRC 17 -#define JPEG2_CLK_SRC 18 -#define PCLK0_CLK_SRC 19 -#define PCLK1_CLK_SRC 20 -#define VCODEC0_CLK_SRC 21 -#define CCI_CLK_SRC 22 -#define CAMSS_GP0_CLK_SRC 23 -#define CAMSS_GP1_CLK_SRC 24 -#define MCLK0_CLK_SRC 25 -#define MCLK1_CLK_SRC 26 -#define MCLK2_CLK_SRC 27 -#define MCLK3_CLK_SRC 28 -#define CSI0PHYTIMER_CLK_SRC 29 -#define CSI1PHYTIMER_CLK_SRC 30 -#define CSI2PHYTIMER_CLK_SRC 31 -#define CPP_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define EDPAUX_CLK_SRC 35 -#define EDPLINK_CLK_SRC 36 -#define EDPPIXEL_CLK_SRC 37 -#define ESC0_CLK_SRC 38 -#define ESC1_CLK_SRC 39 -#define EXTPCLK_CLK_SRC 40 -#define HDMI_CLK_SRC 41 -#define VSYNC_CLK_SRC 42 -#define MMSS_RBCPR_CLK_SRC 43 -#define CAMSS_CCI_CCI_AHB_CLK 44 -#define CAMSS_CCI_CCI_CLK 45 -#define CAMSS_CSI0_AHB_CLK 46 -#define CAMSS_CSI0_CLK 47 -#define CAMSS_CSI0PHY_CLK 48 -#define CAMSS_CSI0PIX_CLK 49 -#define CAMSS_CSI0RDI_CLK 50 -#define CAMSS_CSI1_AHB_CLK 51 -#define CAMSS_CSI1_CLK 52 -#define CAMSS_CSI1PHY_CLK 53 -#define CAMSS_CSI1PIX_CLK 54 -#define CAMSS_CSI1RDI_CLK 55 -#define CAMSS_CSI2_AHB_CLK 56 -#define CAMSS_CSI2_CLK 57 -#define CAMSS_CSI2PHY_CLK 58 -#define CAMSS_CSI2PIX_CLK 59 -#define CAMSS_CSI2RDI_CLK 60 -#define CAMSS_CSI3_AHB_CLK 61 -#define CAMSS_CSI3_CLK 62 -#define CAMSS_CSI3PHY_CLK 63 -#define CAMSS_CSI3PIX_CLK 64 -#define CAMSS_CSI3RDI_CLK 65 -#define CAMSS_CSI_VFE0_CLK 66 -#define CAMSS_CSI_VFE1_CLK 67 -#define CAMSS_GP0_CLK 68 -#define CAMSS_GP1_CLK 69 -#define CAMSS_ISPIF_AHB_CLK 70 -#define CAMSS_JPEG_JPEG0_CLK 71 -#define CAMSS_JPEG_JPEG1_CLK 72 -#define CAMSS_JPEG_JPEG2_CLK 73 -#define CAMSS_JPEG_JPEG_AHB_CLK 74 -#define CAMSS_JPEG_JPEG_AXI_CLK 75 -#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76 -#define CAMSS_MCLK0_CLK 77 -#define CAMSS_MCLK1_CLK 78 -#define CAMSS_MCLK2_CLK 79 -#define CAMSS_MCLK3_CLK 80 -#define CAMSS_MICRO_AHB_CLK 81 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 82 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 83 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 84 -#define CAMSS_TOP_AHB_CLK 85 -#define CAMSS_VFE_CPP_AHB_CLK 86 -#define CAMSS_VFE_CPP_CLK 87 -#define CAMSS_VFE_VFE0_CLK 88 -#define CAMSS_VFE_VFE1_CLK 89 -#define CAMSS_VFE_VFE_AHB_CLK 90 -#define CAMSS_VFE_VFE_AXI_CLK 91 -#define CAMSS_VFE_VFE_OCMEMNOC_CLK 92 -#define MDSS_AHB_CLK 93 -#define MDSS_AXI_CLK 94 -#define MDSS_BYTE0_CLK 95 -#define MDSS_BYTE1_CLK 96 -#define MDSS_EDPAUX_CLK 97 -#define MDSS_EDPLINK_CLK 98 -#define MDSS_EDPPIXEL_CLK 99 -#define MDSS_ESC0_CLK 100 -#define MDSS_ESC1_CLK 101 -#define MDSS_EXTPCLK_CLK 102 -#define MDSS_HDMI_AHB_CLK 103 -#define MDSS_HDMI_CLK 104 -#define MDSS_MDP_CLK 105 -#define MDSS_MDP_LUT_CLK 106 -#define MDSS_PCLK0_CLK 107 -#define MDSS_PCLK1_CLK 108 -#define MDSS_VSYNC_CLK 109 -#define MMSS_MISC_AHB_CLK 110 -#define MMSS_MMSSNOC_AHB_CLK 111 -#define MMSS_MMSSNOC_BTO_AHB_CLK 112 -#define MMSS_MMSSNOC_AXI_CLK 113 -#define MMSS_S0_AXI_CLK 114 -#define OCMEMCX_AHB_CLK 115 -#define OCMEMCX_OCMEMNOC_CLK 116 -#define OXILI_OCMEMGX_CLK 117 -#define OCMEMNOC_CLK 118 -#define OXILI_GFX3D_CLK 119 -#define OXILICX_AHB_CLK 120 -#define OXILICX_AXI_CLK 121 -#define VENUS0_AHB_CLK 122 -#define VENUS0_AXI_CLK 123 -#define VENUS0_OCMEMNOC_CLK 124 -#define VENUS0_VCODEC0_CLK 125 -#define OCMEMNOC_CLK_SRC 126 -#define SPDM_JPEG0 127 -#define SPDM_JPEG1 128 -#define SPDM_MDP 129 -#define SPDM_AXI 130 -#define SPDM_VCODEC0 131 -#define SPDM_VFE0 132 -#define SPDM_VFE1 133 -#define SPDM_JPEG2 134 -#define SPDM_PCLK1 135 -#define SPDM_GFX3D 136 -#define SPDM_AHB 137 -#define SPDM_PCLK0 138 -#define SPDM_OCMEMNOC 139 -#define SPDM_CSI0 140 -#define SPDM_RM_AXI 141 -#define SPDM_RM_OCMEMNOC 142 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h b/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a87343..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h deleted file mode 100644 index ad95c7f..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Samsung S3C64xx clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ -#define CLK27M 1 -#define CLK48M 2 -#define FOUT_APLL 3 -#define FOUT_MPLL 4 -#define FOUT_EPLL 5 -#define ARMCLK 6 -#define HCLKX2 7 -#define HCLK 8 -#define PCLK 9 - -/* HCLK bus clocks. */ -#define HCLK_3DSE 16 -#define HCLK_UHOST 17 -#define HCLK_SECUR 18 -#define HCLK_SDMA1 19 -#define HCLK_SDMA0 20 -#define HCLK_IROM 21 -#define HCLK_DDR1 22 -#define HCLK_MEM1 23 -#define HCLK_MEM0 24 -#define HCLK_USB 25 -#define HCLK_HSMMC2 26 -#define HCLK_HSMMC1 27 -#define HCLK_HSMMC0 28 -#define HCLK_MDP 29 -#define HCLK_DHOST 30 -#define HCLK_IHOST 31 -#define HCLK_DMA1 32 -#define HCLK_DMA0 33 -#define HCLK_JPEG 34 -#define HCLK_CAMIF 35 -#define HCLK_SCALER 36 -#define HCLK_2D 37 -#define HCLK_TV 38 -#define HCLK_POST0 39 -#define HCLK_ROT 40 -#define HCLK_LCD 41 -#define HCLK_TZIC 42 -#define HCLK_INTC 43 -#define HCLK_MFC 44 -#define HCLK_DDR0 45 - -/* PCLK bus clocks. */ -#define PCLK_IIC1 48 -#define PCLK_IIS2 49 -#define PCLK_SKEY 50 -#define PCLK_CHIPID 51 -#define PCLK_SPI1 52 -#define PCLK_SPI0 53 -#define PCLK_HSIRX 54 -#define PCLK_HSITX 55 -#define PCLK_GPIO 56 -#define PCLK_IIC0 57 -#define PCLK_IIS1 58 -#define PCLK_IIS0 59 -#define PCLK_AC97 60 -#define PCLK_TZPC 61 -#define PCLK_TSADC 62 -#define PCLK_KEYPAD 63 -#define PCLK_IRDA 64 -#define PCLK_PCM1 65 -#define PCLK_PCM0 66 -#define PCLK_PWM 67 -#define PCLK_RTC 68 -#define PCLK_WDT 69 -#define PCLK_UART3 70 -#define PCLK_UART2 71 -#define PCLK_UART1 72 -#define PCLK_UART0 73 -#define PCLK_MFC 74 - -/* Special clocks. */ -#define SCLK_UHOST 80 -#define SCLK_MMC2_48 81 -#define SCLK_MMC1_48 82 -#define SCLK_MMC0_48 83 -#define SCLK_MMC2 84 -#define SCLK_MMC1 85 -#define SCLK_MMC0 86 -#define SCLK_SPI1_48 87 -#define SCLK_SPI0_48 88 -#define SCLK_SPI1 89 -#define SCLK_SPI0 90 -#define SCLK_DAC27 91 -#define SCLK_TV27 92 -#define SCLK_SCALER27 93 -#define SCLK_SCALER 94 -#define SCLK_LCD27 95 -#define SCLK_LCD 96 -#define SCLK_FIMC 97 -#define SCLK_POST0_27 98 -#define SCLK_AUDIO2 99 -#define SCLK_POST0 100 -#define SCLK_AUDIO1 101 -#define SCLK_AUDIO0 102 -#define SCLK_SECUR 103 -#define SCLK_IRDA 104 -#define SCLK_UART 105 -#define SCLK_MFC 106 -#define SCLK_CAM 107 -#define SCLK_JPEG 108 -#define SCLK_ONENAND 109 - -/* MEM0 bus clocks - S3C6410-specific. */ -#define MEM0_CFCON 112 -#define MEM0_ONENAND1 113 -#define MEM0_ONENAND0 114 -#define MEM0_NFCON 115 -#define MEM0_SROM 116 - -/* Muxes. */ -#define MOUT_APLL 128 -#define MOUT_MPLL 129 -#define MOUT_EPLL 130 -#define MOUT_MFC 131 -#define MOUT_AUDIO0 132 -#define MOUT_AUDIO1 133 -#define MOUT_UART 134 -#define MOUT_SPI0 135 -#define MOUT_SPI1 136 -#define MOUT_MMC0 137 -#define MOUT_MMC1 138 -#define MOUT_MMC2 139 -#define MOUT_UHOST 140 -#define MOUT_IRDA 141 -#define MOUT_LCD 142 -#define MOUT_SCALER 143 -#define MOUT_DAC27 144 -#define MOUT_TV27 145 -#define MOUT_AUDIO2 146 - -/* Dividers. */ -#define DOUT_MPLL 160 -#define DOUT_SECUR 161 -#define DOUT_CAM 162 -#define DOUT_JPEG 163 -#define DOUT_MFC 164 -#define DOUT_MMC0 165 -#define DOUT_MMC1 166 -#define DOUT_MMC2 167 -#define DOUT_LCD 168 -#define DOUT_SCALER 169 -#define DOUT_UHOST 170 -#define DOUT_SPI0 171 -#define DOUT_SPI1 172 -#define DOUT_AUDIO0 173 -#define DOUT_AUDIO1 174 -#define DOUT_UART 175 -#define DOUT_IRDA 176 -#define DOUT_FIMC 177 -#define DOUT_AUDIO2 178 - -/* Total number of clocks. */ -#define NR_CLKS (DOUT_AUDIO2 + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h b/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index 42121fa..0000000 --- a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h deleted file mode 100644 index fa74d7c..0000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This header provides constants for the Qualcomm PMIC GPIO binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H - -#define PMIC_GPIO_PULL_UP_30 0 -#define PMIC_GPIO_PULL_UP_1P5 1 -#define PMIC_GPIO_PULL_UP_31P5 2 -#define PMIC_GPIO_PULL_UP_1P5_30 3 - -#define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 -#define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 - -/* - * Note: PM8018 GPIO3 and GPIO4 are supporting - * only S3 and L2 options (1.8V) - */ -#define PM8018_GPIO_L6 0 -#define PM8018_GPIO_L5 1 -#define PM8018_GPIO_S3 2 -#define PM8018_GPIO_L14 3 -#define PM8018_GPIO_L2 4 -#define PM8018_GPIO_L4 5 -#define PM8018_GPIO_VDD 6 - -/* - * Note: PM8038 GPIO7 and GPIO8 are supporting - * only L11 and L4 options (1.8V) - */ -#define PM8038_GPIO_VPH 0 -#define PM8038_GPIO_BB 1 -#define PM8038_GPIO_L11 2 -#define PM8038_GPIO_L15 3 -#define PM8038_GPIO_L4 4 -#define PM8038_GPIO_L3 5 -#define PM8038_GPIO_L17 6 - -#define PM8058_GPIO_VPH 0 -#define PM8058_GPIO_BB 1 -#define PM8058_GPIO_S3 2 -#define PM8058_GPIO_L3 3 -#define PM8058_GPIO_L7 4 -#define PM8058_GPIO_L6 5 -#define PM8058_GPIO_L5 6 -#define PM8058_GPIO_L2 7 - -#define PM8917_GPIO_VPH 0 -#define PM8917_GPIO_S4 2 -#define PM8917_GPIO_L15 3 -#define PM8917_GPIO_L4 4 -#define PM8917_GPIO_L3 5 -#define PM8917_GPIO_L17 6 - -#define PM8921_GPIO_VPH 0 -#define PM8921_GPIO_BB 1 -#define PM8921_GPIO_S4 2 -#define PM8921_GPIO_L15 3 -#define PM8921_GPIO_L4 4 -#define PM8921_GPIO_L3 5 -#define PM8921_GPIO_L17 6 - -/* - * Note: PM8941 gpios from 15 to 18 are supporting - * only S3 and L6 options (1.8V) - */ -#define PM8941_GPIO_VPH 0 -#define PM8941_GPIO_L1 1 -#define PM8941_GPIO_S3 2 -#define PM8941_GPIO_L6 3 - -/* - * Note: PMA8084 gpios from 15 to 18 are supporting - * only S4 and L6 options (1.8V) - */ -#define PMA8084_GPIO_VPH 0 -#define PMA8084_GPIO_L1 1 -#define PMA8084_GPIO_S4 2 -#define PMA8084_GPIO_L6 3 - -/* To be used with "function" */ -#define PMIC_GPIO_FUNC_NORMAL "normal" -#define PMIC_GPIO_FUNC_PAIRED "paired" -#define PMIC_GPIO_FUNC_FUNC1 "func1" -#define PMIC_GPIO_FUNC_FUNC2 "func2" -#define PMIC_GPIO_FUNC_DTEST1 "dtest1" -#define PMIC_GPIO_FUNC_DTEST2 "dtest2" -#define PMIC_GPIO_FUNC_DTEST3 "dtest3" -#define PMIC_GPIO_FUNC_DTEST4 "dtest4" - -#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 - -#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 - -#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 - -#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h deleted file mode 100644 index d2c7dab..0000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This header provides constants for the Qualcomm PMIC's - * Multi-Purpose Pin binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H - -/* power-source */ -#define PM8841_MPP_VPH 0 -#define PM8841_MPP_S3 2 - -#define PM8941_MPP_VPH 0 -#define PM8941_MPP_L1 1 -#define PM8941_MPP_S3 2 -#define PM8941_MPP_L6 3 - -#define PMA8084_MPP_VPH 0 -#define PMA8084_MPP_L1 1 -#define PMA8084_MPP_S4 2 -#define PMA8084_MPP_L6 3 - -/* - * Analog Input - Set the source for analog input. - * To be used with "qcom,amux-route" property - */ -#define PMIC_MPP_AMUX_ROUTE_CH5 0 -#define PMIC_MPP_AMUX_ROUTE_CH6 1 -#define PMIC_MPP_AMUX_ROUTE_CH7 2 -#define PMIC_MPP_AMUX_ROUTE_CH8 3 -#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 -#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 -#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 -#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 - -/* To be used with "function" */ -#define PMIC_MPP_FUNC_NORMAL "normal" -#define PMIC_MPP_FUNC_PAIRED "paired" -#define PMIC_MPP_FUNC_DTEST1 "dtest1" -#define PMIC_MPP_FUNC_DTEST2 "dtest2" -#define PMIC_MPP_FUNC_DTEST3 "dtest3" -#define PMIC_MPP_FUNC_DTEST4 "dtest4" - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h deleted file mode 100644 index cf28631..0000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for the Maxim 77802 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H -#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H - -/* Regulator operating modes */ -#define MAX77802_OPMODE_LP 1 -#define MAX77802_OPMODE_NORMAL 3 - -#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 3f04908..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h deleted file mode 100644 index 527caaf..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H -#define _DT_BINDINGS_RESET_APQ_GCC_8084_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_BAM_DMA_BCR 44 -#define GCC_TSIF_BCR 45 -#define GCC_TCSR_BCR 46 -#define GCC_BOOT_ROM_BCR 47 -#define GCC_MSG_RAM_BCR 48 -#define GCC_TLMM_BCR 49 -#define GCC_MPM_BCR 50 -#define GCC_MPM_AHB_RESET 51 -#define GCC_MPM_NON_AHB_RESET 52 -#define GCC_SEC_CTRL_BCR 53 -#define GCC_SPMI_BCR 54 -#define GCC_SPDM_BCR 55 -#define GCC_CE1_BCR 56 -#define GCC_CE2_BCR 57 -#define GCC_BIMC_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 -#define GCC_DEHR_BCR 73 -#define GCC_RBCPR_BCR 74 -#define GCC_MSS_RESTART 75 -#define GCC_LPASS_RESTART 76 -#define GCC_WCSS_RESTART 77 -#define GCC_VENUS_RESTART 78 -#define GCC_COPSS_SMMU_BCR 79 -#define GCC_SPSS_BCR 80 -#define GCC_PCIE_0_BCR 81 -#define GCC_PCIE_0_PHY_BCR 82 -#define GCC_PCIE_1_BCR 83 -#define GCC_PCIE_1_PHY_BCR 84 -#define GCC_USB_30_SEC_BCR 85 -#define GCC_USB3_SEC_PHY_BCR 86 -#define GCC_SATA_BCR 87 -#define GCC_CE3_BCR 88 -#define GCC_UFS_BCR 89 -#define GCC_USB30_PHY_COM_BCR 90 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h deleted file mode 100644 index 0ad5ef9..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_806X_H -#define _DT_BINDINGS_RESET_IPQ_806X_H - -#define QDSS_STM_RESET 0 -#define AFAB_SMPSS_S_RESET 1 -#define AFAB_SMPSS_M1_RESET 2 -#define AFAB_SMPSS_M0_RESET 3 -#define AFAB_EBI1_CH0_RESET 4 -#define AFAB_EBI1_CH1_RESET 5 -#define SFAB_ADM0_M0_RESET 6 -#define SFAB_ADM0_M1_RESET 7 -#define SFAB_ADM0_M2_RESET 8 -#define ADM0_C2_RESET 9 -#define ADM0_C1_RESET 10 -#define ADM0_C0_RESET 11 -#define ADM0_PBUS_RESET 12 -#define ADM0_RESET 13 -#define QDSS_CLKS_SW_RESET 14 -#define QDSS_POR_RESET 15 -#define QDSS_TSCTR_RESET 16 -#define QDSS_HRESET_RESET 17 -#define QDSS_AXI_RESET 18 -#define QDSS_DBG_RESET 19 -#define SFAB_PCIE_M_RESET 20 -#define SFAB_PCIE_S_RESET 21 -#define PCIE_EXT_RESET 22 -#define PCIE_PHY_RESET 23 -#define PCIE_PCI_RESET 24 -#define PCIE_POR_RESET 25 -#define PCIE_HCLK_RESET 26 -#define PCIE_ACLK_RESET 27 -#define SFAB_LPASS_RESET 28 -#define SFAB_AFAB_M_RESET 29 -#define AFAB_SFAB_M0_RESET 30 -#define AFAB_SFAB_M1_RESET 31 -#define SFAB_SATA_S_RESET 32 -#define SFAB_DFAB_M_RESET 33 -#define DFAB_SFAB_M_RESET 34 -#define DFAB_SWAY0_RESET 35 -#define DFAB_SWAY1_RESET 36 -#define DFAB_ARB0_RESET 37 -#define DFAB_ARB1_RESET 38 -#define PPSS_PROC_RESET 39 -#define PPSS_RESET 40 -#define DMA_BAM_RESET 41 -#define SPS_TIC_H_RESET 42 -#define SFAB_CFPB_M_RESET 43 -#define SFAB_CFPB_S_RESET 44 -#define TSIF_H_RESET 45 -#define CE1_H_RESET 46 -#define CE1_CORE_RESET 47 -#define CE1_SLEEP_RESET 48 -#define CE2_H_RESET 49 -#define CE2_CORE_RESET 50 -#define SFAB_SFPB_M_RESET 51 -#define SFAB_SFPB_S_RESET 52 -#define RPM_PROC_RESET 53 -#define PMIC_SSBI2_RESET 54 -#define SDC1_RESET 55 -#define SDC2_RESET 56 -#define SDC3_RESET 57 -#define SDC4_RESET 58 -#define USB_HS1_RESET 59 -#define USB_HSIC_RESET 60 -#define USB_FS1_XCVR_RESET 61 -#define USB_FS1_RESET 62 -#define GSBI1_RESET 63 -#define GSBI2_RESET 64 -#define GSBI3_RESET 65 -#define GSBI4_RESET 66 -#define GSBI5_RESET 67 -#define GSBI6_RESET 68 -#define GSBI7_RESET 69 -#define SPDM_RESET 70 -#define SEC_CTRL_RESET 71 -#define TLMM_H_RESET 72 -#define SFAB_SATA_M_RESET 73 -#define SATA_RESET 74 -#define TSSC_RESET 75 -#define PDM_RESET 76 -#define MPM_H_RESET 77 -#define MPM_RESET 78 -#define SFAB_SMPSS_S_RESET 79 -#define PRNG_RESET 80 -#define SFAB_CE3_M_RESET 81 -#define SFAB_CE3_S_RESET 82 -#define CE3_SLEEP_RESET 83 -#define PCIE_1_M_RESET 84 -#define PCIE_1_S_RESET 85 -#define PCIE_1_EXT_RESET 86 -#define PCIE_1_PHY_RESET 87 -#define PCIE_1_PCI_RESET 88 -#define PCIE_1_POR_RESET 89 -#define PCIE_1_HCLK_RESET 90 -#define PCIE_1_ACLK_RESET 91 -#define PCIE_2_M_RESET 92 -#define PCIE_2_S_RESET 93 -#define PCIE_2_EXT_RESET 94 -#define PCIE_2_PHY_RESET 95 -#define PCIE_2_PCI_RESET 96 -#define PCIE_2_POR_RESET 97 -#define PCIE_2_HCLK_RESET 98 -#define PCIE_2_ACLK_RESET 99 -#define SFAB_USB30_S_RESET 100 -#define SFAB_USB30_M_RESET 101 -#define USB30_0_PORT2_HS_PHY_RESET 102 -#define USB30_0_MASTER_RESET 103 -#define USB30_0_SLEEP_RESET 104 -#define USB30_0_UTMI_PHY_RESET 105 -#define USB30_0_POWERON_RESET 106 -#define USB30_0_PHY_RESET 107 -#define USB30_1_MASTER_RESET 108 -#define USB30_1_SLEEP_RESET 109 -#define USB30_1_UTMI_PHY_RESET 110 -#define USB30_1_POWERON_RESET 111 -#define USB30_1_PHY_RESET 112 -#define NSSFB0_RESET 113 -#define NSSFB1_RESET 114 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h deleted file mode 100644 index a83282f..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H -#define _DT_BINDINGS_RESET_MSM_GCC_8660_H - -#define AFAB_CORE_RESET 0 -#define SCSS_SYS_RESET 1 -#define SCSS_SYS_POR_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_S_RESET 6 -#define SFAB_CORE_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define SFAB_ADM1_M0_RESET 16 -#define SFAB_ADM1_M1_RESET 17 -#define SFAB_ADM1_M2_RESET 18 -#define MMFAB_ADM1_M3_RESET 19 -#define ADM1_C3_RESET 20 -#define ADM1_C2_RESET 21 -#define ADM1_C1_RESET 22 -#define ADM1_C0_RESET 23 -#define ADM1_PBUS_RESET 24 -#define ADM1_RESET 25 -#define IMEM0_RESET 26 -#define SFAB_LPASS_Q6_RESET 27 -#define SFAB_AFAB_M_RESET 28 -#define AFAB_SFAB_M0_RESET 29 -#define AFAB_SFAB_M1_RESET 30 -#define DFAB_CORE_RESET 31 -#define SFAB_DFAB_M_RESET 32 -#define DFAB_SFAB_M_RESET 33 -#define DFAB_SWAY0_RESET 34 -#define DFAB_SWAY1_RESET 35 -#define DFAB_ARB0_RESET 36 -#define DFAB_ARB1_RESET 37 -#define PPSS_PROC_RESET 38 -#define PPSS_RESET 39 -#define PMEM_RESET 40 -#define DMA_BAM_RESET 41 -#define SIC_RESET 42 -#define SPS_TIC_RESET 43 -#define CFBP0_RESET 44 -#define CFBP1_RESET 45 -#define CFBP2_RESET 46 -#define EBI2_RESET 47 -#define SFAB_CFPB_M_RESET 48 -#define CFPB_MASTER_RESET 49 -#define SFAB_CFPB_S_RESET 50 -#define CFPB_SPLITTER_RESET 51 -#define TSIF_RESET 52 -#define CE1_RESET 53 -#define CE2_RESET 54 -#define SFAB_SFPB_M_RESET 55 -#define SFAB_SFPB_S_RESET 56 -#define RPM_PROC_RESET 57 -#define RPM_BUS_RESET 58 -#define RPM_MSG_RAM_RESET 59 -#define PMIC_ARB0_RESET 60 -#define PMIC_ARB1_RESET 61 -#define PMIC_SSBI2_RESET 62 -#define SDC1_RESET 63 -#define SDC2_RESET 64 -#define SDC3_RESET 65 -#define SDC4_RESET 66 -#define SDC5_RESET 67 -#define USB_HS1_RESET 68 -#define USB_HS2_XCVR_RESET 69 -#define USB_HS2_RESET 70 -#define USB_FS1_XCVR_RESET 71 -#define USB_FS1_RESET 72 -#define USB_FS2_XCVR_RESET 73 -#define USB_FS2_RESET 74 -#define GSBI1_RESET 75 -#define GSBI2_RESET 76 -#define GSBI3_RESET 77 -#define GSBI4_RESET 78 -#define GSBI5_RESET 79 -#define GSBI6_RESET 80 -#define GSBI7_RESET 81 -#define GSBI8_RESET 82 -#define GSBI9_RESET 83 -#define GSBI10_RESET 84 -#define GSBI11_RESET 85 -#define GSBI12_RESET 86 -#define SPDM_RESET 87 -#define SEC_CTRL_RESET 88 -#define TLMM_H_RESET 89 -#define TLMM_RESET 90 -#define MARRM_PWRON_RESET 91 -#define MARM_RESET 92 -#define MAHB1_RESET 93 -#define SFAB_MSS_S_RESET 94 -#define MAHB2_RESET 95 -#define MODEM_SW_AHB_RESET 96 -#define MODEM_RESET 97 -#define SFAB_MSS_MDM1_RESET 98 -#define SFAB_MSS_MDM0_RESET 99 -#define MSS_SLP_RESET 100 -#define MSS_MARM_SAW_RESET 101 -#define MSS_WDOG_RESET 102 -#define TSSC_RESET 103 -#define PDM_RESET 104 -#define SCSS_CORE0_RESET 105 -#define SCSS_CORE0_POR_RESET 106 -#define SCSS_CORE1_RESET 107 -#define SCSS_CORE1_POR_RESET 108 -#define MPM_RESET 109 -#define EBI1_1X_DIV_RESET 110 -#define EBI1_RESET 111 -#define SFAB_SMPSS_S_RESET 112 -#define USB_PHY0_RESET 113 -#define USB_PHY1_RESET 114 -#define PRNG_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h deleted file mode 100644 index 47c8686..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H -#define _DT_BINDINGS_RESET_MSM_GCC_8960_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h deleted file mode 100644 index 9bdf543..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H -#define _DT_BINDINGS_RESET_MSM_GCC_8974_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_BAM_DMA_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_CE2_BCR 54 -#define GCC_BIMC_BCR 55 -#define GCC_MPM_NON_AHB_RESET 56 -#define GCC_MPM_AHB_RESET 57 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_DEHR_BCR 72 -#define GCC_RBCPR_BCR 73 -#define GCC_MSS_RESTART 74 -#define GCC_LPASS_RESTART 75 -#define GCC_WCSS_RESTART 76 -#define GCC_VENUS_RESTART 77 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h deleted file mode 100644 index c167139..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H -#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H - -#define MMSS_SPDM_RESET 0 -#define MMSS_SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define VPU_RESET 3 -#define MDSS_RESET 4 -#define AVSYNC_RESET 5 -#define CAMSS_PHY0_RESET 6 -#define CAMSS_PHY1_RESET 7 -#define CAMSS_PHY2_RESET 8 -#define CAMSS_CSI0_RESET 9 -#define CAMSS_CSI0PHY_RESET 10 -#define CAMSS_CSI0RDI_RESET 11 -#define CAMSS_CSI0PIX_RESET 12 -#define CAMSS_CSI1_RESET 13 -#define CAMSS_CSI1PHY_RESET 14 -#define CAMSS_CSI1RDI_RESET 15 -#define CAMSS_CSI1PIX_RESET 16 -#define CAMSS_CSI2_RESET 17 -#define CAMSS_CSI2PHY_RESET 18 -#define CAMSS_CSI2RDI_RESET 19 -#define CAMSS_CSI2PIX_RESET 20 -#define CAMSS_CSI3_RESET 21 -#define CAMSS_CSI3PHY_RESET 22 -#define CAMSS_CSI3RDI_RESET 23 -#define CAMSS_CSI3PIX_RESET 24 -#define CAMSS_ISPIF_RESET 25 -#define CAMSS_CCI_RESET 26 -#define CAMSS_MCLK0_RESET 27 -#define CAMSS_MCLK1_RESET 28 -#define CAMSS_MCLK2_RESET 29 -#define CAMSS_MCLK3_RESET 30 -#define CAMSS_GP0_RESET 31 -#define CAMSS_GP1_RESET 32 -#define CAMSS_TOP_RESET 33 -#define CAMSS_AHB_RESET 34 -#define CAMSS_MICRO_RESET 35 -#define CAMSS_JPEG_RESET 36 -#define CAMSS_VFE_RESET 37 -#define CAMSS_CSI_VFE0_RESET 38 -#define CAMSS_CSI_VFE1_RESET 39 -#define OXILI_RESET 40 -#define OXILICX_RESET 41 -#define OCMEMCX_RESET 42 -#define MMSS_RBCRP_RESET 43 -#define MMSSNOCAHB_RESET 44 -#define MMSSNOCAXI_RESET 45 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h deleted file mode 100644 index 1174111..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H - -#define VPE_AXI_RESET 0 -#define IJPEG_AXI_RESET 1 -#define MPD_AXI_RESET 2 -#define VFE_AXI_RESET 3 -#define SP_AXI_RESET 4 -#define VCODEC_AXI_RESET 5 -#define ROT_AXI_RESET 6 -#define VCODEC_AXI_A_RESET 7 -#define VCODEC_AXI_B_RESET 8 -#define FAB_S3_AXI_RESET 9 -#define FAB_S2_AXI_RESET 10 -#define FAB_S1_AXI_RESET 11 -#define FAB_S0_AXI_RESET 12 -#define SMMU_GFX3D_ABH_RESET 13 -#define SMMU_VPE_AHB_RESET 14 -#define SMMU_VFE_AHB_RESET 15 -#define SMMU_ROT_AHB_RESET 16 -#define SMMU_VCODEC_B_AHB_RESET 17 -#define SMMU_VCODEC_A_AHB_RESET 18 -#define SMMU_MDP1_AHB_RESET 19 -#define SMMU_MDP0_AHB_RESET 20 -#define SMMU_JPEGD_AHB_RESET 21 -#define SMMU_IJPEG_AHB_RESET 22 -#define SMMU_GFX2D0_AHB_RESET 23 -#define SMMU_GFX2D1_AHB_RESET 24 -#define APU_AHB_RESET 25 -#define CSI_AHB_RESET 26 -#define TV_ENC_AHB_RESET 27 -#define VPE_AHB_RESET 28 -#define FABRIC_AHB_RESET 29 -#define GFX2D0_AHB_RESET 30 -#define GFX2D1_AHB_RESET 31 -#define GFX3D_AHB_RESET 32 -#define HDMI_AHB_RESET 33 -#define MSSS_IMEM_AHB_RESET 34 -#define IJPEG_AHB_RESET 35 -#define DSI_M_AHB_RESET 36 -#define DSI_S_AHB_RESET 37 -#define JPEGD_AHB_RESET 38 -#define MDP_AHB_RESET 39 -#define ROT_AHB_RESET 40 -#define VCODEC_AHB_RESET 41 -#define VFE_AHB_RESET 42 -#define DSI2_M_AHB_RESET 43 -#define DSI2_S_AHB_RESET 44 -#define CSIPHY2_RESET 45 -#define CSI_PIX1_RESET 46 -#define CSIPHY0_RESET 47 -#define CSIPHY1_RESET 48 -#define DSI2_RESET 49 -#define VFE_CSI_RESET 50 -#define MDP_RESET 51 -#define AMP_RESET 52 -#define JPEGD_RESET 53 -#define CSI1_RESET 54 -#define VPE_RESET 55 -#define MMSS_FABRIC_RESET 56 -#define VFE_RESET 57 -#define GFX2D0_RESET 58 -#define GFX2D1_RESET 59 -#define GFX3D_RESET 60 -#define HDMI_RESET 61 -#define MMSS_IMEM_RESET 62 -#define IJPEG_RESET 63 -#define CSI0_RESET 64 -#define DSI_RESET 65 -#define VCODEC_RESET 66 -#define MDP_TV_RESET 67 -#define MDP_VSYNC_RESET 68 -#define ROT_RESET 69 -#define TV_HDMI_RESET 70 -#define TV_ENC_RESET 71 -#define CSI2_RESET 72 -#define CSI_RDI1_RESET 73 -#define CSI_RDI2_RESET 74 -#define GFX3D_AXI_RESET 75 -#define VCAP_AXI_RESET 76 -#define SMMU_VCAP_AHB_RESET 77 -#define VCAP_AHB_RESET 78 -#define CSI_RDI_RESET 79 -#define CSI_PIX_RESET 80 -#define VCAP_NPL_RESET 81 -#define VCAP_RESET 82 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h deleted file mode 100644 index da3ec37..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H - -#define SPDM_RESET 0 -#define SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define MDSS_RESET 3 -#define CAMSS_PHY0_RESET 4 -#define CAMSS_PHY1_RESET 5 -#define CAMSS_PHY2_RESET 6 -#define CAMSS_CSI0_RESET 7 -#define CAMSS_CSI0PHY_RESET 8 -#define CAMSS_CSI0RDI_RESET 9 -#define CAMSS_CSI0PIX_RESET 10 -#define CAMSS_CSI1_RESET 11 -#define CAMSS_CSI1PHY_RESET 12 -#define CAMSS_CSI1RDI_RESET 13 -#define CAMSS_CSI1PIX_RESET 14 -#define CAMSS_CSI2_RESET 15 -#define CAMSS_CSI2PHY_RESET 16 -#define CAMSS_CSI2RDI_RESET 17 -#define CAMSS_CSI2PIX_RESET 18 -#define CAMSS_CSI3_RESET 19 -#define CAMSS_CSI3PHY_RESET 20 -#define CAMSS_CSI3RDI_RESET 21 -#define CAMSS_CSI3PIX_RESET 22 -#define CAMSS_ISPIF_RESET 23 -#define CAMSS_CCI_RESET 24 -#define CAMSS_MCLK0_RESET 25 -#define CAMSS_MCLK1_RESET 26 -#define CAMSS_MCLK2_RESET 27 -#define CAMSS_MCLK3_RESET 28 -#define CAMSS_GP0_RESET 29 -#define CAMSS_GP1_RESET 30 -#define CAMSS_TOP_RESET 31 -#define CAMSS_MICRO_RESET 32 -#define CAMSS_JPEG_RESET 33 -#define CAMSS_VFE_RESET 34 -#define CAMSS_CSI_VFE0_RESET 35 -#define CAMSS_CSI_VFE1_RESET 36 -#define OXILI_RESET 37 -#define OXILICX_RESET 38 -#define OCMEMCX_RESET 39 -#define MMSS_RBCRP_RESET 40 -#define MMSSNOCAHB_RESET 41 -#define MMSSNOCAXI_RESET 42 -#define OCMEMNOC_RESET 43 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h deleted file mode 100644 index 7ac4292..0000000 --- a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_QCOM_GSBI_H -#define __DT_BINDINGS_QCOM_GSBI_H - -#define GSBI_PROT_IDLE 0 -#define GSBI_PROT_I2C_UIM 1 -#define GSBI_PROT_I2C 2 -#define GSBI_PROT_SPI 3 -#define GSBI_PROT_UART_W_FC 4 -#define GSBI_PROT_UIM 5 -#define GSBI_PROT_I2C_UART 6 - -#define GSBI_CRCI_QUP 0 -#define GSBI_CRCI_UART 1 - -#endif |
