diff options
Diffstat (limited to 'sys/arm/include/armreg.h')
| -rw-r--r-- | sys/arm/include/armreg.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 05b3846..35fe6d7 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -146,6 +146,7 @@ #define CPU_ID_ARM1026EJS 0x4106a260 #define CPU_ID_ARM1136JS 0x4107b360 #define CPU_ID_ARM1136JSR1 0x4117b360 +#define CPU_ID_ARM1176JZS 0x410fb760 #define CPU_ID_CORTEXA8R1 0x411fc080 #define CPU_ID_CORTEXA8R2 0x412fc080 #define CPU_ID_CORTEXA8R3 0x413fc080 @@ -284,11 +285,36 @@ #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ +#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ +#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE +/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ +#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ +#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ +#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ +#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ +#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ +#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ +#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ + +/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ + /* This is an undocumented flag + * used to work around a cache bug + * in r0 steppings. See errata + * 364296. + */ +/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ +#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ +#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ +#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ + /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ |
