Wire the kernel using TLB1 entry 0 rather than entry 1. A more recent

U-Boot as found on the P1020RDB doesn't like it when we use entry 1
(for some reason) whereas an older U-Boot doesn't mind if we use entry
0. If anything else, this simplifies the code a bit.

2 files changed, 10 insertions, 23 deletions

diff --git a/sys/powerpc/booke/locore.S b/sys/powerpc/booke/locore.S
index 3ac4a1a..47ac353 100644
--- a/sys/powerpc/booke/locore.S
+++ b/sys/powerpc/booke/locore.S
@@ -148,7 +148,7 @@ __start:
  */
 	/* Final kernel mapping, map in 16 MB of RAM */
 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
-	li	%r4, 1			/* Entry 1 */
+	li	%r4, 0			/* Entry 0 */
 	rlwimi	%r3, %r4, 16, 12, 15
 	mtspr	SPR_MAS0, %r3
 	isync
@@ -318,7 +318,7 @@ kernload_ap:
  */
 	/* Final kernel mapping, map in 16 MB of RAM */
 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
-	li	%r4, 1			/* Entry 1 */
+	li	%r4, 0			/* Entry 0 */
 	rlwimi	%r3, %r4, 16, 4, 15
 	mtspr	SPR_MAS0, %r3
 	isync
@@ -490,11 +490,7 @@ tlb1_temp_mapping_as1:
 	 */
 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
 	addi	%r29, %r30, 1		/* Use next entry. */
-	li	%r4, 1
-	cmpw	%r4, %r29
-	bne	1f
-	addi	%r29, %r29, 1
-1:	rlwimi	%r3, %r29, 16, 12, 15	/* Select temp entry */
+	rlwimi	%r3, %r29, 16, 12, 15	/* Select temp entry */
 	mtspr	SPR_MAS0, %r3
 	isync
 	mfspr	%r5, SPR_MAS1
diff --git a/sys/powerpc/booke/pmap.c b/sys/powerpc/booke/pmap.c
index 2fffa3f..4a279af 100644
--- a/sys/powerpc/booke/pmap.c
+++ b/sys/powerpc/booke/pmap.c
@@ -91,9 +91,6 @@ __FBSDID("$FreeBSD$");
 
 #include "mmu_if.h"
 
-#define DEBUG
-#undef DEBUG
-
 #ifdef  DEBUG
 #define debugf(fmt, args...) printf(fmt, ##args)
 #else
@@ -3019,24 +3016,18 @@ tlb1_init(vm_offset_t ccsrbar)
 {
 	uint32_t mas0;
 
-	/* TLB1[1] is used to map the kernel. Save that entry. */
-	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1);
+	/* TLB1[0] is used to map the kernel. Save that entry. */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
 	mtspr(SPR_MAS0, mas0);
 	__asm __volatile("isync; tlbre");
 
-	tlb1[1].mas1 = mfspr(SPR_MAS1);
-	tlb1[1].mas2 = mfspr(SPR_MAS2);
-	tlb1[1].mas3 = mfspr(SPR_MAS3);
+	tlb1[0].mas1 = mfspr(SPR_MAS1);
+	tlb1[0].mas2 = mfspr(SPR_MAS2);
+	tlb1[0].mas3 = mfspr(SPR_MAS3);
 
-	/* Map in CCSRBAR in TLB1[0] */
-	tlb1_idx = 0;
+	/* Map in CCSRBAR in TLB1[1] */
+	tlb1_idx = 1;
 	tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
-	/*
-	 * Set the next available TLB1 entry index. Note TLB[1] is reserved
-	 * for initial mapping of kernel text+data, which was set early in
-	 * locore, we need to skip this [busy] entry.
-	 */
-	tlb1_idx = 2;
 
 	/* Setup TLB miss defaults */
 	set_mas4_defaults();