diff options
| author | mbr <mbr@FreeBSD.org> | 2003-01-10 08:09:58 +0000 |
|---|---|---|
| committer | mbr <mbr@FreeBSD.org> | 2003-01-10 08:09:58 +0000 |
| commit | 9f1243940bfab5bf1006a5d8a39c39a8d688f28e (patch) | |
| tree | f2496f3c07328af9a2edd5ddb808e004161522c4 /sys/pci/if_vr.c | |
| parent | 92b8a62ce5f67fa00bad3929c26f8d1a19458541 (diff) | |
| download | FreeBSD-src-9f1243940bfab5bf1006a5d8a39c39a8d688f28e.zip FreeBSD-src-9f1243940bfab5bf1006a5d8a39c39a8d688f28e.tar.gz | |
When reading PHY regs over the i2c bus, the turnaround ACK bit
is read one clock edge too late. This bit is driven low by
slave (as any other input data bits from slave) when the clock
is LOW. The current code did read the bit after the clock was
driven high again.
Reviewed by: luoqi
MFC after: 2 weeks
Diffstat (limited to 'sys/pci/if_vr.c')
| -rw-r--r-- | sys/pci/if_vr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/pci/if_vr.c b/sys/pci/if_vr.c index 81e00b5..407abf1 100644 --- a/sys/pci/if_vr.c +++ b/sys/pci/if_vr.c @@ -329,9 +329,9 @@ vr_mii_readreg(sc, frame) /* Check for ack */ SIO_CLR(VR_MIICMD_CLK); DELAY(1); + ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; SIO_SET(VR_MIICMD_CLK); DELAY(1); - ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; /* * Now try reading data bits. If the ack failed, we still |
