From 9f1243940bfab5bf1006a5d8a39c39a8d688f28e Mon Sep 17 00:00:00 2001 From: mbr Date: Fri, 10 Jan 2003 08:09:58 +0000 Subject: When reading PHY regs over the i2c bus, the turnaround ACK bit is read one clock edge too late. This bit is driven low by slave (as any other input data bits from slave) when the clock is LOW. The current code did read the bit after the clock was driven high again. Reviewed by: luoqi MFC after: 2 weeks --- sys/pci/if_vr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sys/pci/if_vr.c') diff --git a/sys/pci/if_vr.c b/sys/pci/if_vr.c index 81e00b5..407abf1 100644 --- a/sys/pci/if_vr.c +++ b/sys/pci/if_vr.c @@ -329,9 +329,9 @@ vr_mii_readreg(sc, frame) /* Check for ack */ SIO_CLR(VR_MIICMD_CLK); DELAY(1); + ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; SIO_SET(VR_MIICMD_CLK); DELAY(1); - ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; /* * Now try reading data bits. If the ack failed, we still -- cgit v1.1