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| author | kato <kato@FreeBSD.org> | 2000-06-13 09:10:37 +0000 |
|---|---|---|
| committer | kato <kato@FreeBSD.org> | 2000-06-13 09:10:37 +0000 |
| commit | dba64e78dce3c311cc00033f8c0af84575139b1e (patch) | |
| tree | 68cdff74dadfaa03aedcd1abb3d1b6dcca20362a /sys/nfs/bootp_subr.c | |
| parent | 5eb5ab57a68e51da29c881cfe66d953a4a707aa7 (diff) | |
| download | FreeBSD-src-dba64e78dce3c311cc00033f8c0af84575139b1e.zip FreeBSD-src-dba64e78dce3c311cc00033f8c0af84575139b1e.tar.gz | |
Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support
Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is
defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is
enabled through MSR 0x11e. The L2 cache latency value can be
specified by CPU_L2_LATENCY option. Default value of L2 cache latency
is 5.
These options are useful if you use Socket 8 to Socket 370 converter
(e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2
cache of Mendocino Celeron CPUs because they don't know Celeron CPUs.
These options are needles if you use a Coppermine (FCPGA) Celeron or
PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache
is always enabled.
Diffstat (limited to 'sys/nfs/bootp_subr.c')
0 files changed, 0 insertions, 0 deletions
