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-rw-r--r--sys/amd64/amd64/initcpu.c55
-rw-r--r--sys/conf/NOTES10
-rw-r--r--sys/conf/options.i3862
-rw-r--r--sys/conf/options.pc982
-rw-r--r--sys/i386/conf/LINT10
-rw-r--r--sys/i386/conf/NOTES10
-rw-r--r--sys/i386/i386/initcpu.c55
7 files changed, 138 insertions, 6 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index a56bb36..37ab866 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -60,6 +60,7 @@ static void init_6x86(void);
#ifdef I686_CPU
static void init_6x86MX(void);
static void init_ppro(void);
+static void init_mendocino(void);
#endif
#ifdef I486_CPU
@@ -450,6 +451,47 @@ init_ppro(void)
wrmsr(0x1b, apicbase);
#endif
}
+
+/*
+ * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
+ * L2 cache).
+ */
+void
+init_mendocino(void)
+{
+#ifdef CPU_PPRO2CELERON
+ u_long eflags;
+ u_int64_t bbl_cr_ctl3;
+
+ eflags = read_eflags();
+ disable_intr();
+
+ load_cr0(rcr0() | CR0_CD | CR0_NW);
+ wbinvd();
+
+ bbl_cr_ctl3 = rdmsr(0x11e);
+
+ /* If the L2 cache is configured, do nothing. */
+ if (!(bbl_cr_ctl3 & 1)) {
+ bbl_cr_ctl3 = 0x134052bLL;
+
+ /* Set L2 Cache Latency (Default: 5). */
+#ifdef CPU_CELERON_L2_LATENCY
+#if CPU_L2_LATENCY > 15
+#error invalid CPU_L2_LATENCY.
+#endif
+ bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
+#else
+ bbl_cr_ctl3 |= 5 << 1;
+#endif
+ wrmsr(0x11e, bbl_cr_ctl3);
+ }
+
+ load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
+ write_eflags(eflags);
+#endif /* CPU_PPRO2CELERON */
+}
+
#endif /* I686_CPU */
void
@@ -484,9 +526,16 @@ initializecpu(void)
init_6x86MX();
break;
case CPU_686:
- if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
- (cpu_id & 0xff0) == 0x610)
- init_ppro();
+ if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
+ switch (cpu_id & 0xff0) {
+ case 0x610:
+ init_ppro();
+ break;
+ case 0x660:
+ init_mendocino();
+ break;
+ }
+ }
break;
#endif
default:
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index dd6023f..c60f78e 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
+# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
+# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
+# The default value is 5.
+#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
+# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
+# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
+# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
+#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
+options CPU_L2_LATENCY=5
options CPU_LOOP_EN
+options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC
diff --git a/sys/conf/options.i386 b/sys/conf/options.i386
index cc28b45..4cceb8b 100644
--- a/sys/conf/options.i386
+++ b/sys/conf/options.i386
@@ -51,7 +51,9 @@ CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
+CPU_L2_LATENCY opt_cpu.h
CPU_LOOP_EN opt_cpu.h
+CPU_PPRO2CELERON opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
diff --git a/sys/conf/options.pc98 b/sys/conf/options.pc98
index ce08963..570a73e 100644
--- a/sys/conf/options.pc98
+++ b/sys/conf/options.pc98
@@ -50,7 +50,9 @@ CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
+CPU_L2_LATENCY opt_cpu.h
CPU_LOOP_EN opt_cpu.h
+CPU_PPRO2CELERON opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT
index dd6023f..c60f78e 100644
--- a/sys/i386/conf/LINT
+++ b/sys/i386/conf/LINT
@@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
+# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
+# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
+# The default value is 5.
+#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
+# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
+# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
+# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
+#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
+options CPU_L2_LATENCY=5
options CPU_LOOP_EN
+options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index dd6023f..c60f78e 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
+# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
+# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
+# The default value is 5.
+#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
+# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
+# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
+# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
+#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
+options CPU_L2_LATENCY=5
options CPU_LOOP_EN
+options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index a56bb36..37ab866 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -60,6 +60,7 @@ static void init_6x86(void);
#ifdef I686_CPU
static void init_6x86MX(void);
static void init_ppro(void);
+static void init_mendocino(void);
#endif
#ifdef I486_CPU
@@ -450,6 +451,47 @@ init_ppro(void)
wrmsr(0x1b, apicbase);
#endif
}
+
+/*
+ * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
+ * L2 cache).
+ */
+void
+init_mendocino(void)
+{
+#ifdef CPU_PPRO2CELERON
+ u_long eflags;
+ u_int64_t bbl_cr_ctl3;
+
+ eflags = read_eflags();
+ disable_intr();
+
+ load_cr0(rcr0() | CR0_CD | CR0_NW);
+ wbinvd();
+
+ bbl_cr_ctl3 = rdmsr(0x11e);
+
+ /* If the L2 cache is configured, do nothing. */
+ if (!(bbl_cr_ctl3 & 1)) {
+ bbl_cr_ctl3 = 0x134052bLL;
+
+ /* Set L2 Cache Latency (Default: 5). */
+#ifdef CPU_CELERON_L2_LATENCY
+#if CPU_L2_LATENCY > 15
+#error invalid CPU_L2_LATENCY.
+#endif
+ bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
+#else
+ bbl_cr_ctl3 |= 5 << 1;
+#endif
+ wrmsr(0x11e, bbl_cr_ctl3);
+ }
+
+ load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
+ write_eflags(eflags);
+#endif /* CPU_PPRO2CELERON */
+}
+
#endif /* I686_CPU */
void
@@ -484,9 +526,16 @@ initializecpu(void)
init_6x86MX();
break;
case CPU_686:
- if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
- (cpu_id & 0xff0) == 0x610)
- init_ppro();
+ if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
+ switch (cpu_id & 0xff0) {
+ case 0x610:
+ init_ppro();
+ break;
+ case 0x660:
+ init_mendocino();
+ break;
+ }
+ }
break;
#endif
default:
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