Add some style(9) touch ups; style(9) states that new code should follow

these conventions and, well, this is a new driver.

Tested on:	i386, sparc64
Reviewed by:	scottl

6 files changed, 67 insertions, 68 deletions

diff --git a/sys/dev/esp/esp_sbus.c b/sys/dev/esp/esp_sbus.c
index 7df02ae..ec1e037 100644
--- a/sys/dev/esp/esp_sbus.c
+++ b/sys/dev/esp/esp_sbus.c
@@ -108,7 +108,7 @@ struct esp_softc {
 	struct resource		*sc_irqres;
 	void			*sc_irq;
 
-	struct lsi64854_softc	*sc_dma;	/* pointer to my dma */
+	struct lsi64854_softc	*sc_dma;	/* pointer to my DMA */
 
 	int	sc_pri;				/* SBUS priority */
 };
@@ -202,7 +202,7 @@ esp_sbus_attach(device_t dev)
 
 	/*
 	 * allocate space for dma, in SUNW,fas there are no separate
-	 * dma device
+	 * dma devices
 	 */
 	lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
 
@@ -568,7 +568,7 @@ void
 esp_dma_stop(struct ncr53c9x_softc *sc)
 {
 	struct esp_softc *esc = (struct esp_softc *)sc;
-	u_int32_t csr;
+	uint32_t csr;
 
 	csr = L64854_GCSR(esc->sc_dma);
 	csr &= ~D_EN_DMA;
diff --git a/sys/dev/esp/lsi64854.c b/sys/dev/esp/lsi64854.c
index dca8526f7..6216560 100644
--- a/sys/dev/esp/lsi64854.c
+++ b/sys/dev/esp/lsi64854.c
@@ -116,7 +116,7 @@ int lsi64854debug = 0;
 void
 lsi64854_attach(struct lsi64854_softc *sc)
 {
-	u_int32_t csr;
+	uint32_t csr;
 
 	sc->dv_name = device_get_nameunit(sc->sc_dev);
 
@@ -205,7 +205,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
 } while (0)
 
 #define DMA_DRAIN(sc, dontpanic) do {					\
-	u_int32_t csr;							\
+	uint32_t csr;							\
 	/*								\
 	 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush"	\
 	 *     and "drain" bits while it is still thinking about a	\
@@ -228,13 +228,13 @@ lsi64854_attach(struct lsi64854_softc *sc)
 	}								\
 	/*								\
 	 * Wait for draining to finish					\
-	 *  rev0 & rev1 call this PACKCNT				\
+	 * rev0 & rev1 call this PACKCNT				\
 	 */								\
 	DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
 } while(0)
 
 #define DMA_FLUSH(sc, dontpanic) do {					\
-	u_int32_t csr;							\
+	uint32_t csr;							\
 	/*								\
 	 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush"	\
 	 *     and "drain" bits while it is still thinking about a	\
@@ -251,7 +251,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
 void
 lsi64854_reset(struct lsi64854_softc *sc)
 {
-	u_int32_t csr;
+	uint32_t csr;
 
 	DMA_FLUSH(sc, 1);
 	csr = L64854_GCSR(sc);
@@ -346,7 +346,7 @@ int
 lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
 	       int datain, size_t *dmasize)
 {
-	u_int32_t csr;
+	uint32_t csr;
 
 	DMA_FLUSH(sc, 0);
 
@@ -358,7 +358,7 @@ lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
 	sc->sc_datain = datain;
 
 	/*
-	 * the rules say we cannot transfer more than the limit
+	 * The rules say we cannot transfer more than the limit
 	 * of this DMA chip (64k for old and 16Mb for new),
 	 * and we cannot cross a 16Mb boundary.
 	 */
@@ -427,7 +427,7 @@ lsi64854_scsi_intr(void *arg)
 	struct lsi64854_softc *sc = arg;
 	struct ncr53c9x_softc *nsc = sc->sc_client;
 	int trans, resid;
-	u_int32_t csr;
+	uint32_t csr;
 
 	csr = L64854_GCSR(sc);
 
@@ -550,7 +550,7 @@ int
 lsi64854_enet_intr(void *arg)
 {
 	struct lsi64854_softc *sc = arg;
-	u_int32_t csr;
+	uint32_t csr;
 	static int dodrain = 0;
 	int rv;
 
@@ -608,7 +608,7 @@ int
 lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
 		  int datain, size_t *dmasize)
 {
-	u_int32_t csr;
+	uint32_t csr;
 
 	DMA_FLUSH(sc, 0);
 
@@ -668,7 +668,7 @@ lsi64854_pp_intr(void *arg)
 {
 	struct lsi64854_softc *sc = arg;
 	int ret, trans, resid = 0;
-	u_int32_t csr;
+	uint32_t csr;
 
 	csr = L64854_GCSR(sc);
 
diff --git a/sys/dev/esp/lsi64854var.h b/sys/dev/esp/lsi64854var.h
index 04b2297..03e1d7d 100644
--- a/sys/dev/esp/lsi64854var.h
+++ b/sys/dev/esp/lsi64854var.h
@@ -93,7 +93,7 @@ struct lsi64854_softc {
 #define DMA_ISACTIVE(sc)		((sc)->sc_active)
 
 #define DMA_ENINTR(sc) do {			\
-	u_int32_t csr = L64854_GCSR(sc);	\
+	uint32_t csr = L64854_GCSR(sc);		\
 	csr |= L64854_INT_EN;			\
 	L64854_SCSR(sc, csr);			\
 } while (0)
@@ -101,7 +101,7 @@ struct lsi64854_softc {
 #define DMA_ISINTR(sc)	(L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
 
 #define DMA_GO(sc) do {				\
-	u_int32_t csr = L64854_GCSR(sc);	\
+	uint32_t csr = L64854_GCSR(sc);		\
 	csr |= D_EN_DMA;			\
 	L64854_SCSR(sc, csr);			\
 	sc->sc_active = 1;			\
diff --git a/sys/dev/esp/ncr53c9x.c b/sys/dev/esp/ncr53c9x.c
index 3cb3bab..4868611 100644
--- a/sys/dev/esp/ncr53c9x.c
+++ b/sys/dev/esp/ncr53c9x.c
@@ -99,7 +99,7 @@
  * Based on aic6360 by Jarle Greipsland
  *
  * Acknowledgements: Many of the algorithms used in this driver are
- * inspired by the work of Julian Elischer (julian@tfs.com) and
+ * inspired by the work of Julian Elischer (julian@FreeBSD.org) and
  * Charles Hannum (mycroft@duality.gnu.ai.mit.edu).  Thanks a million!
  */
 
@@ -216,7 +216,7 @@ ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
 }
 
 /*
- * Attach this instance, and then all the sub-devices
+ * Attach this instance, and then all the sub-devices.
  */
 int
 ncr53c9x_attach(struct ncr53c9x_softc *sc)
@@ -770,7 +770,7 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
 	}
 
 	/*
-	 * Who am I. This is where we tell the target that we are
+	 * Who am I?  This is where we tell the target that we are
 	 * happy for it to disconnect etc.
 	 */
 
@@ -817,7 +817,7 @@ ncr53c9x_get_ecb(struct ncr53c9x_softc *sc)
 }
 
 /*
- * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
+ * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS:
  */
 
 /*
@@ -1043,7 +1043,7 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
 }
 
 /*
- * Used when interrupt driven I/O isn't allowed, e.g. during boot.
+ * Used when interrupt driven I/O is not allowed, e.g. during boot.
  */
 static void
 ncr53c9x_poll(struct cam_sim *sim)
@@ -1630,7 +1630,7 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
 
 gotit:
 	NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state));
-	/* we got complete message, flush the imess, */
+	/* We got a complete message, flush the imess, */
 	/* XXX nobody uses imlen below */
 	sc->sc_imlen = 0;
 	/*
@@ -1916,8 +1916,8 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
 	 * XXX - the NCR_ATN flag is not in sync with the actual ATN
 	 *	 condition on the SCSI bus. The 53c9x chip
 	 *	 automatically turns off ATN before sending the
-	 *	 message byte.  (see also the comment below in the
-	 *	 default case when picking out a message to send)
+	 *	 message byte.  (See also the comment below in the
+	 *	 default case when picking out a message to send.)
 	 */
 	if (sc->sc_flags & NCR_ATN) {
 		if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
@@ -2420,7 +2420,7 @@ again:
 			}
 			/*
 			 * The C90 only inhibits FIFO writes until reselection
-			 * is complete, instead of waiting until the interrupt
+			 * is complete instead of waiting until the interrupt
 			 * status register has been read.  So, if the reselect
 			 * happens while we were entering command bytes (for
 			 * another target) some of those bytes can appear in
@@ -2949,4 +2949,3 @@ ncr53c9x_watch(void *arg)
 	mtx_unlock(&sc->sc_lock);
 	callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
 }
-
diff --git a/sys/dev/esp/ncr53c9xreg.h b/sys/dev/esp/ncr53c9xreg.h
index a2d9668..b4ba1e8 100644
--- a/sys/dev/esp/ncr53c9xreg.h
+++ b/sys/dev/esp/ncr53c9xreg.h
@@ -42,7 +42,7 @@
 
 #define	NCR_FIFO	0x02		/* RW - FIFO data		*/
 
-#define	NCR_CMD		0x03		/* RW - Command (2 deep)	*/
+#define	 NCR_CMD	0x03		/* RW - Command (2 deep)	*/
 #define  NCRCMD_DMA	0x80		/*	DMA Bit			*/
 #define  NCRCMD_NOP	0x00		/*	No Operation		*/
 #define  NCRCMD_FLUSH	0x01		/*	Flush FIFO		*/
@@ -75,7 +75,7 @@
 #define  NCRCMD_SETATN	0x1a		/*	Set ATN			*/
 #define  NCRCMD_RSTATN	0x1b		/*	Reset ATN		*/
 
-#define	NCR_STAT	0x04		/* RO - Status			*/
+#define	 NCR_STAT	0x04		/* RO - Status			*/
 #define  NCRSTAT_INT	0x80		/*	Interrupt		*/
 #define  NCRSTAT_GE	0x40		/*	Gross Error		*/
 #define  NCRSTAT_PE	0x20		/*	Parity Error		*/
@@ -83,11 +83,11 @@
 #define  NCRSTAT_VGC	0x08		/*	Valid Group Code	*/
 #define  NCRSTAT_PHASE	0x07		/*	Phase bits		*/
 
-#define	NCR_SELID	0x04		/* WO - Select/Reselect Bus ID	*/
+#define	 NCR_SELID	0x04		/* WO - Select/Reselect Bus ID	*/
 #define  NCR_BUSID_HME		0x10 	/* XXX HME reselect ID 		*/
 #define  NCR_BUSID_HME32	0x40	/* XXX HME to select more than 16 */
 
-#define	NCR_INTR	0x05		/* RO - Interrupt		*/
+#define	 NCR_INTR	0x05		/* RO - Interrupt		*/
 #define  NCRINTR_SBR	0x80		/*	SCSI Bus Reset		*/
 #define  NCRINTR_ILL	0x40		/*	Illegal Command		*/
 #define  NCRINTR_DIS	0x20		/*	Disconnect		*/
@@ -97,16 +97,16 @@
 #define  NCRINTR_SELATN	0x02		/*	Select with ATN		*/
 #define  NCRINTR_SEL	0x01		/*	Selected		*/
 
-#define	NCR_TIMEOUT	0x05		/* WO - Select/Reselect Timeout */
+#define	 NCR_TIMEOUT	0x05		/* WO - Select/Reselect Timeout */
 
-#define	NCR_STEP	0x06		/* RO - Sequence Step		*/
+#define	 NCR_STEP	0x06		/* RO - Sequence Step		*/
 #define  NCRSTEP_MASK	0x07		/*	the last 3 bits		*/
 #define  NCRSTEP_DONE	0x04		/*	command went out	*/
 
-#define	NCR_SYNCTP	0x06		/* WO - Synch Transfer Period	*/
+#define	 NCR_SYNCTP	0x06		/* WO - Synch Transfer Period	*/
 					/*	Default 5 (53C9X)	*/
 
-#define	NCR_FFLAG	0x07		/* RO - FIFO Flags		*/
+#define	 NCR_FFLAG	0x07		/* RO - FIFO Flags		*/
 #define  NCRFIFO_SS	0xe0		/*	Sequence Step (Dup)	*/
 #define  NCRFIFO_FF	0x1f		/*	Bytes in FIFO		*/
 
@@ -114,7 +114,7 @@
 					/*	0 = ASYNC		*/
 					/*	1 - 15 = SYNC bytes	*/
 
-#define	NCR_CFG1	0x08		/* RW - Configuration #1	*/
+#define	 NCR_CFG1	0x08		/* RW - Configuration #1	*/
 #define  NCRCFG1_SLOW	0x80		/*	Slow Cable Mode		*/
 #define  NCRCFG1_SRR	0x40		/*	SCSI Reset Rep Int Dis	*/
 #define  NCRCFG1_PTEST	0x20		/*	Parity Test Mod		*/
@@ -122,7 +122,7 @@
 #define  NCRCFG1_CTEST	0x08		/*	Enable Chip Test	*/
 #define  NCRCFG1_BUSID	0x07		/*	Bus ID			*/
 
-#define	NCR_CCF		0x09		/* WO -	Clock Conversion Factor	*/
+#define	 NCR_CCF	0x09		/* WO -	Clock Conversion Factor	*/
 					/*	0 = 35.01 - 40MHz	*/
 					/*	NEVER SET TO 1		*/
 					/*	2 = 10MHz		*/
@@ -132,9 +132,9 @@
 					/*	6 = 25.01 - 30MHz	*/
 					/*	7 = 30.01 - 35MHz	*/
 
-#define	NCR_TEST	0x0a		/* WO - Test (Chip Test Only)	*/
+#define	 NCR_TEST	0x0a		/* WO - Test (Chip Test Only)	*/
 
-#define	NCR_CFG2	0x0b		/* RW - Configuration #2	*/
+#define	 NCR_CFG2	0x0b		/* RW - Configuration #2	*/
 #define	 NCRCFG2_RSVD	0xa0		/*	reserved		*/
 #define  NCRCFG2_FE	0x40		/* 	Features Enable		*/
 #define  NCRCFG2_DREQ	0x10		/* 	DREQ High Impedance	*/
@@ -147,7 +147,7 @@
 #define	 NCRCFG2_HME32  0x80		/*	HME 32 extended		*/
 
 /* Config #3 only on 53C9X */
-#define	NCR_CFG3	0x0c		/* RW - Configuration #3	*/
+#define	 NCR_CFG3	0x0c		/* RW - Configuration #3	*/
 #define	 NCRCFG3_RSVD	0xe0		/*	reserved		*/
 #define  NCRCFG3_IDM	0x10		/*	ID Message Res Check	*/
 #define  NCRCFG3_QTE	0x08		/*	Queue Tag Enable	*/
@@ -163,7 +163,7 @@
  */
 
 /* Config #3 different on ESP406/FAS408 */
-#define	NCR_ESPCFG3		0x0c	/* RW - Configuration #3	*/
+#define	 NCR_ESPCFG3		0x0c	/* RW - Configuration #3	*/
 #define  NCRESPCFG3_IDM		0x80	/*	ID Message Res Check	*/
 #define  NCRESPCFG3_QTE		0x40	/*	Queue Tag Enable	*/
 #define  NCRESPCFG3_CDB		0x20	/*	CDB 10-bytes OK		*/
@@ -174,7 +174,7 @@
 #define	 NCRESPCFG3_T8M		0x01	/*	Threshold 8 Mode	*/
 
 /* Config #3 also different on NCR53CF9x/FAS216 */
-#define	NCR_F9XCFG3		0x0c	/* RW - Configuration #3	*/
+#define	 NCR_F9XCFG3		0x0c	/* RW - Configuration #3	*/
 #define  NCRF9XCFG3_IDM		0x80	/*	ID Message Res Check	*/
 #define  NCRF9XCFG3_QTE		0x40	/*	Queue Tag Enable	*/
 #define  NCRF9XCFG3_CDB		0x20	/*	CDB 10-bytes OK		*/
@@ -195,7 +195,7 @@
 #define	 NCRFASCFG3_FASTCLK	0x01	/* 	fast clock mode */
 
 /* Config #4 only on ESP406/FAS408 */
-#define	NCR_CFG4	0x0d		/* RW - Configuration #4	*/
+#define	 NCR_CFG4	0x0d		/* RW - Configuration #4	*/
 #define	 NCRCFG4_CRS1	0x80		/*	Select register set #1	*/
 #define	 NCRCFG4_RSVD	0x7b		/*	reserved		*/
 #define	 NCRCFG4_ACTNEG	0x04		/*	Active negation		*/
@@ -207,7 +207,7 @@
    register 0x0d is set.  This bit is common to both register sets.
 */
 
-#define	NCR_JMP		0x00		/* RO - Jumper Sense Register	*/
+#define	 NCR_JMP	0x00		/* RO - Jumper Sense Register	*/
 #define  NCRJMP_RSVD	0xc0		/*	reserved		*/
 #define  NCRJMP_ROMSZ	0x20		/*	ROM Size 1=16K, 0=32K	*/
 #define	 NCRJMP_J4	0x10		/*	Jumper #4		*/
@@ -216,9 +216,9 @@
 #define	 NCRJMP_J1	0x02		/*	Jumper #1		*/
 #define	 NCRJMP_J0	0x01		/*	Jumper #0		*/
 
-#define	NCR_PIOFIFO	0x04		/* WO - PIO FIFO, 4 bytes deep	*/
+#define	 NCR_PIOFIFO	0x04		/* WO - PIO FIFO, 4 bytes deep	*/
 
-#define NCR_PSTAT	0x08		/* RW - PIO Status Register	*/
+#define  NCR_PSTAT	0x08		/* RW - PIO Status Register	*/
 #define  NCRPSTAT_PERR	0x80		/*	PIO Error		*/
 #define  NCRPSTAT_SIRQ	0x40		/*	Active High of SCSI IRQ */
 #define  NCRPSTAT_ATAI	0x20		/*	ATA IRQ			*/
@@ -228,7 +228,7 @@
 #define  NCRPSTAT_FFULL	0x02		/*	PIO FIFO Full		*/
 #define  NCRPSTAT_PIOM	0x01		/*	PIO/DMA Mode		*/
 
-#define NCR_PIOI	0x0b		/* RW - PIO Interrupt Enable	*/
+#define  NCR_PIOI	0x0b		/* RW - PIO Interrupt Enable	*/
 #define	 NCRPIOI_RSVD	0xe0		/*	reserved		*/
 #define	 NCRPIOI_EMPTY	0x10		/*	IRQ When Empty		*/
 #define	 NCRPIOI_13	0x08		/*	IRQ When 1/3		*/
@@ -236,7 +236,7 @@
 #define	 NCRPIOI_FULL	0x02		/*	IRQ When Full		*/
 #define	 NCRPIOI_FINV	0x01		/*	Flag Invert		*/
 
-#define	NCR_CFG5	0x0d		/* RW - Configuration #5	*/
+#define	 NCR_CFG5	0x0d		/* RW - Configuration #5	*/
 #define	 NCRCFG5_CRS1	0x80		/*	Select Register Set #1	*/
 #define	 NCRCFG5_SRAM	0x40		/*	SRAM Memory Map		*/
 #define  NCRCFG5_AADDR	0x20		/*	Auto Address		*/
@@ -246,10 +246,10 @@
 #define  NCRCFG5_INTP	0x02		/*	INT Polarity		*/
 #define  NCRCFG5_AINT	0x01		/*	ATA Interupt Enable	*/
 
-#define	NCR_SIGNTR	0x0e		/* RO - Signature		*/
+#define	 NCR_SIGNTR	0x0e		/* RO - Signature		*/
 
 /* Am53c974 Config #3 */
-#define	NCR_AMDCFG3		0x0c	/* RW - Configuration #3	*/
+#define	 NCR_AMDCFG3		0x0c	/* RW - Configuration #3	*/
 #define	 NCRAMDCFG3_IDM		0x80	/*	ID Message Res Check	*/
 #define	 NCRAMDCFG3_QTE		0x40	/*	Queue Tag Enable	*/
 #define	 NCRAMDCFG3_CDB		0x20	/*	CDB 10-bytes OK		*/
@@ -258,7 +258,7 @@
 #define	 NCRAMDCFG3_RSVD	0x07	/*	Reserved		*/
 
 /* Am53c974 Config #4 */
-#define	NCR_AMDCFG4		0x0d	/* RW - Configuration #4	*/
+#define	 NCR_AMDCFG4		0x0d	/* RW - Configuration #4	*/
 #define	 NCRAMDCFG4_GE		0xc0	/*	Glitch Eater		*/
 #define	 NCRAMDCFG4_GE12NS	0x00	/*	Signal window 12ns	*/
 #define	 NCRAMDCFG4_GE25NS	0x80	/*	Signal window 25ns	*/
@@ -272,19 +272,19 @@
 /*
  * FAS366
  */ 
-#define NCR_RCL		NCR_TCH	/* Recommand counter low */
-#define NCR_RCH		0xf	/* Recommand counter high */
-#define NCR_UID		NCR_RCL	/* fas366 part-uniq id */
+#define  NCR_RCL		NCR_TCH	/* Recommand counter low */
+#define  NCR_RCH		0xf	/* Recommand counter high */
+#define  NCR_UID		NCR_RCL	/* fas366 part-uniq id */
 
 
 /* status register #2 definitions (read	only) */
-#define NCR_STAT2	NCR_CCF
-#define	NCRFAS_STAT2_SEQCNT   0x01	   /* Sequence counter bit 7-3 enabled */
-#define	NCRFAS_STAT2_FLATCHED 0x02	   /* FIFO flags register latched */
-#define	NCRFAS_STAT2_CLATCHED 0x04	   /* Xfer cntr	& recommand ctr	latched */
-#define	NCRFAS_STAT2_CACTIVE  0x08	   /* Command register is active */
-#define	NCRFAS_STAT2_SCSI16   0x10	   /* SCSI interface is	wide */
-#define	NCRFAS_STAT2_ISHUTTLE 0x20	   /* FIFO Top register	contains 1 byte */
-#define	NCRFAS_STAT2_OSHUTTLE 0x40	   /* next byte	from FIFO is MSB */
-#define	NCRFAS_STAT2_EMPTY    0x80	   /* FIFO is empty */
+#define  NCR_STAT2	       NCR_CCF
+#define	 NCRFAS_STAT2_SEQCNT   0x01	   /* Sequence counter bit 7-3 enabled */
+#define	 NCRFAS_STAT2_FLATCHED 0x02	   /* FIFO flags register latched */
+#define	 NCRFAS_STAT2_CLATCHED 0x04	   /* Xfer cntr	& recommand ctr	latched */
+#define	 NCRFAS_STAT2_CACTIVE  0x08	   /* Command register is active */
+#define	 NCRFAS_STAT2_SCSI16   0x10	   /* SCSI interface is	wide */
+#define	 NCRFAS_STAT2_ISHUTTLE 0x20	   /* FIFO Top register	contains 1 byte */
+#define	 NCRFAS_STAT2_OSHUTTLE 0x40	   /* next byte	from FIFO is MSB */
+#define	 NCRFAS_STAT2_EMPTY    0x80	   /* FIFO is empty */
 
diff --git a/sys/dev/esp/ncr53c9xvar.h b/sys/dev/esp/ncr53c9xvar.h
index be7f148..7bf6b2d 100644
--- a/sys/dev/esp/ncr53c9xvar.h
+++ b/sys/dev/esp/ncr53c9xvar.h
@@ -85,8 +85,8 @@
 #define FREQTOCCF(freq)	(((freq + 4) / 5))
 
 /*
- * NCR 53c9x variants.  Note, these values are used as indexes into
- * a table; don't modify them unless you know what you're doing.
+ * NCR 53c9x variants.  Note these values are used as indexes into
+ * a table; do not modify them unless you know what you are doing.
  */
 #define	NCR_VARIANT_ESP100		0
 #define	NCR_VARIANT_ESP100A		1
@@ -171,9 +171,9 @@ struct ncr53c9x_linfo {
 	int64_t			lun;
 	LIST_ENTRY(ncr53c9x_linfo) link;
 	time_t			last_used;
-	unsigned char		used;	/* # slots in use */
-	unsigned char		avail;	/* where to start scanning */
-	unsigned char		busy;
+	u_char			used;	/* # slots in use */
+	u_char			avail;	/* where to start scanning */
+	u_char			busy;
 	struct ncr53c9x_ecb	*untagged;
 	struct ncr53c9x_ecb	*queued[NCR_TAG_DEPTH];
 };
@@ -361,7 +361,7 @@ struct ncr53c9x_softc {
 };
 
 /* values for sc_state */
-#define NCR_IDLE	1	/* waiting for something to do */
+#define NCR_IDLE	1	/* Waiting for something to do */
 #define NCR_SELECTING	2	/* SCSI command is arbiting  */
 #define NCR_RESELECTED	3	/* Has been reselected */
 #define NCR_IDENTIFIED	4	/* Has gotten IFY but not TAG */