diff options
Diffstat (limited to 'sys/dev/esp/ncr53c9xreg.h')
| -rw-r--r-- | sys/dev/esp/ncr53c9xreg.h | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/sys/dev/esp/ncr53c9xreg.h b/sys/dev/esp/ncr53c9xreg.h index a2d9668..b4ba1e8 100644 --- a/sys/dev/esp/ncr53c9xreg.h +++ b/sys/dev/esp/ncr53c9xreg.h @@ -42,7 +42,7 @@ #define NCR_FIFO 0x02 /* RW - FIFO data */ -#define NCR_CMD 0x03 /* RW - Command (2 deep) */ +#define NCR_CMD 0x03 /* RW - Command (2 deep) */ #define NCRCMD_DMA 0x80 /* DMA Bit */ #define NCRCMD_NOP 0x00 /* No Operation */ #define NCRCMD_FLUSH 0x01 /* Flush FIFO */ @@ -75,7 +75,7 @@ #define NCRCMD_SETATN 0x1a /* Set ATN */ #define NCRCMD_RSTATN 0x1b /* Reset ATN */ -#define NCR_STAT 0x04 /* RO - Status */ +#define NCR_STAT 0x04 /* RO - Status */ #define NCRSTAT_INT 0x80 /* Interrupt */ #define NCRSTAT_GE 0x40 /* Gross Error */ #define NCRSTAT_PE 0x20 /* Parity Error */ @@ -83,11 +83,11 @@ #define NCRSTAT_VGC 0x08 /* Valid Group Code */ #define NCRSTAT_PHASE 0x07 /* Phase bits */ -#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */ +#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */ #define NCR_BUSID_HME 0x10 /* XXX HME reselect ID */ #define NCR_BUSID_HME32 0x40 /* XXX HME to select more than 16 */ -#define NCR_INTR 0x05 /* RO - Interrupt */ +#define NCR_INTR 0x05 /* RO - Interrupt */ #define NCRINTR_SBR 0x80 /* SCSI Bus Reset */ #define NCRINTR_ILL 0x40 /* Illegal Command */ #define NCRINTR_DIS 0x20 /* Disconnect */ @@ -97,16 +97,16 @@ #define NCRINTR_SELATN 0x02 /* Select with ATN */ #define NCRINTR_SEL 0x01 /* Selected */ -#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */ +#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */ -#define NCR_STEP 0x06 /* RO - Sequence Step */ +#define NCR_STEP 0x06 /* RO - Sequence Step */ #define NCRSTEP_MASK 0x07 /* the last 3 bits */ #define NCRSTEP_DONE 0x04 /* command went out */ -#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */ +#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */ /* Default 5 (53C9X) */ -#define NCR_FFLAG 0x07 /* RO - FIFO Flags */ +#define NCR_FFLAG 0x07 /* RO - FIFO Flags */ #define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */ #define NCRFIFO_FF 0x1f /* Bytes in FIFO */ @@ -114,7 +114,7 @@ /* 0 = ASYNC */ /* 1 - 15 = SYNC bytes */ -#define NCR_CFG1 0x08 /* RW - Configuration #1 */ +#define NCR_CFG1 0x08 /* RW - Configuration #1 */ #define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */ #define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */ #define NCRCFG1_PTEST 0x20 /* Parity Test Mod */ @@ -122,7 +122,7 @@ #define NCRCFG1_CTEST 0x08 /* Enable Chip Test */ #define NCRCFG1_BUSID 0x07 /* Bus ID */ -#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */ +#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */ /* 0 = 35.01 - 40MHz */ /* NEVER SET TO 1 */ /* 2 = 10MHz */ @@ -132,9 +132,9 @@ /* 6 = 25.01 - 30MHz */ /* 7 = 30.01 - 35MHz */ -#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */ +#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */ -#define NCR_CFG2 0x0b /* RW - Configuration #2 */ +#define NCR_CFG2 0x0b /* RW - Configuration #2 */ #define NCRCFG2_RSVD 0xa0 /* reserved */ #define NCRCFG2_FE 0x40 /* Features Enable */ #define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */ @@ -147,7 +147,7 @@ #define NCRCFG2_HME32 0x80 /* HME 32 extended */ /* Config #3 only on 53C9X */ -#define NCR_CFG3 0x0c /* RW - Configuration #3 */ +#define NCR_CFG3 0x0c /* RW - Configuration #3 */ #define NCRCFG3_RSVD 0xe0 /* reserved */ #define NCRCFG3_IDM 0x10 /* ID Message Res Check */ #define NCRCFG3_QTE 0x08 /* Queue Tag Enable */ @@ -163,7 +163,7 @@ */ /* Config #3 different on ESP406/FAS408 */ -#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */ +#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */ #define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */ #define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */ #define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */ @@ -174,7 +174,7 @@ #define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */ /* Config #3 also different on NCR53CF9x/FAS216 */ -#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */ +#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */ #define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */ #define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */ #define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */ @@ -195,7 +195,7 @@ #define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */ /* Config #4 only on ESP406/FAS408 */ -#define NCR_CFG4 0x0d /* RW - Configuration #4 */ +#define NCR_CFG4 0x0d /* RW - Configuration #4 */ #define NCRCFG4_CRS1 0x80 /* Select register set #1 */ #define NCRCFG4_RSVD 0x7b /* reserved */ #define NCRCFG4_ACTNEG 0x04 /* Active negation */ @@ -207,7 +207,7 @@ register 0x0d is set. This bit is common to both register sets. */ -#define NCR_JMP 0x00 /* RO - Jumper Sense Register */ +#define NCR_JMP 0x00 /* RO - Jumper Sense Register */ #define NCRJMP_RSVD 0xc0 /* reserved */ #define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */ #define NCRJMP_J4 0x10 /* Jumper #4 */ @@ -216,9 +216,9 @@ #define NCRJMP_J1 0x02 /* Jumper #1 */ #define NCRJMP_J0 0x01 /* Jumper #0 */ -#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */ +#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */ -#define NCR_PSTAT 0x08 /* RW - PIO Status Register */ +#define NCR_PSTAT 0x08 /* RW - PIO Status Register */ #define NCRPSTAT_PERR 0x80 /* PIO Error */ #define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */ #define NCRPSTAT_ATAI 0x20 /* ATA IRQ */ @@ -228,7 +228,7 @@ #define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */ #define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */ -#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */ +#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */ #define NCRPIOI_RSVD 0xe0 /* reserved */ #define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */ #define NCRPIOI_13 0x08 /* IRQ When 1/3 */ @@ -236,7 +236,7 @@ #define NCRPIOI_FULL 0x02 /* IRQ When Full */ #define NCRPIOI_FINV 0x01 /* Flag Invert */ -#define NCR_CFG5 0x0d /* RW - Configuration #5 */ +#define NCR_CFG5 0x0d /* RW - Configuration #5 */ #define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */ #define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */ #define NCRCFG5_AADDR 0x20 /* Auto Address */ @@ -246,10 +246,10 @@ #define NCRCFG5_INTP 0x02 /* INT Polarity */ #define NCRCFG5_AINT 0x01 /* ATA Interupt Enable */ -#define NCR_SIGNTR 0x0e /* RO - Signature */ +#define NCR_SIGNTR 0x0e /* RO - Signature */ /* Am53c974 Config #3 */ -#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */ +#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */ #define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */ #define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */ #define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */ @@ -258,7 +258,7 @@ #define NCRAMDCFG3_RSVD 0x07 /* Reserved */ /* Am53c974 Config #4 */ -#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */ +#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */ #define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */ #define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */ #define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */ @@ -272,19 +272,19 @@ /* * FAS366 */ -#define NCR_RCL NCR_TCH /* Recommand counter low */ -#define NCR_RCH 0xf /* Recommand counter high */ -#define NCR_UID NCR_RCL /* fas366 part-uniq id */ +#define NCR_RCL NCR_TCH /* Recommand counter low */ +#define NCR_RCH 0xf /* Recommand counter high */ +#define NCR_UID NCR_RCL /* fas366 part-uniq id */ /* status register #2 definitions (read only) */ -#define NCR_STAT2 NCR_CCF -#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */ -#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */ -#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */ -#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */ -#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */ -#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */ -#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */ -#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */ +#define NCR_STAT2 NCR_CCF +#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */ +#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */ +#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */ +#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */ +#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */ +#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */ +#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */ +#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */ |
