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| author | scottl <scottl@FreeBSD.org> | 2008-08-02 13:04:26 +0000 |
|---|---|---|
| committer | scottl <scottl@FreeBSD.org> | 2008-08-02 13:04:26 +0000 |
| commit | 02392e305a759c070ed6d6dd7a87602b3006effa (patch) | |
| tree | f0ec10eaecba13372d823b4ddd207b94dfe5cb55 /sys/dev/ciss/cissvar.h | |
| parent | 3bbb49a345a9c362ea68b1c84998da2b606ff342 (diff) | |
| download | FreeBSD-src-02392e305a759c070ed6d6dd7a87602b3006effa.zip FreeBSD-src-02392e305a759c070ed6d6dd7a87602b3006effa.tar.gz | |
Correctly set the interrupt enable and disable bits. The previous
code interfered with Performant mode and legacy interrupts. Also
remove a register read operation on the Simplq code that was
effectively a time-wasting no-op.
Diffstat (limited to 'sys/dev/ciss/cissvar.h')
0 files changed, 0 insertions, 0 deletions
