diff options
| author | scottl <scottl@FreeBSD.org> | 2008-08-02 13:04:26 +0000 |
|---|---|---|
| committer | scottl <scottl@FreeBSD.org> | 2008-08-02 13:04:26 +0000 |
| commit | 02392e305a759c070ed6d6dd7a87602b3006effa (patch) | |
| tree | f0ec10eaecba13372d823b4ddd207b94dfe5cb55 /sys/dev/ciss | |
| parent | 3bbb49a345a9c362ea68b1c84998da2b606ff342 (diff) | |
| download | FreeBSD-src-02392e305a759c070ed6d6dd7a87602b3006effa.zip FreeBSD-src-02392e305a759c070ed6d6dd7a87602b3006effa.tar.gz | |
Correctly set the interrupt enable and disable bits. The previous
code interfered with Performant mode and legacy interrupts. Also
remove a register read operation on the Simplq code that was
effectively a time-wasting no-op.
Diffstat (limited to 'sys/dev/ciss')
| -rw-r--r-- | sys/dev/ciss/ciss.c | 4 | ||||
| -rw-r--r-- | sys/dev/ciss/cissreg.h | 22 |
2 files changed, 11 insertions, 15 deletions
diff --git a/sys/dev/ciss/ciss.c b/sys/dev/ciss/ciss.c index 58c590c..9073e7b 100644 --- a/sys/dev/ciss/ciss.c +++ b/sys/dev/ciss/ciss.c @@ -2028,10 +2028,6 @@ ciss_done(struct ciss_softc *sc, cr_qhead_t *qh) */ for (;;) { - /* see if the OPQ contains anything */ - if (!CISS_TL_SIMPLE_OPQ_INTERRUPT(sc)) - break; - tag = CISS_TL_SIMPLE_FETCH_CMD(sc); if (tag == CISS_TL_SIMPLE_OPQ_EMPTY) break; diff --git a/sys/dev/ciss/cissreg.h b/sys/dev/ciss/cissreg.h index 8909e9b..982df2f 100644 --- a/sys/dev/ciss/cissreg.h +++ b/sys/dev/ciss/cissreg.h @@ -736,17 +736,17 @@ struct ciss_bmic_flush_cache { #define CISS_MSI_COUNT 4 /* - * XXX documentation conflicts with the Linux driver as to whether setting or clearing - * bits masks interrupts + * XXX Here we effectively trust the BIOS to set the IMR correctly. But if + * we don't trust it, will we get into trouble with wrongly assuming what it + * should be? */ -#define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \ - CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ - CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask) -#define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \ - CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ - CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask) - -#define CISS_TL_SIMPLE_OPQ_INTERRUPT(sc) \ - (CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_ISR) & (sc)->ciss_interrupt_mask) +#define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \ + do { \ + (sc)->ciss_interrupt_mask = \ + CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR); \ + CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, ~0); \ + } while (0) +#define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \ + CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, (sc)->ciss_interrupt_mask) #endif /* _KERNEL */ |
