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author | raj <raj@FreeBSD.org> | 2009-01-08 13:20:28 +0000 |
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committer | raj <raj@FreeBSD.org> | 2009-01-08 13:20:28 +0000 |
commit | 8211555cceb46a5f12326f8b579ef71985c1909f (patch) | |
tree | 7f3438ebd8767dd6f323486c7a00d6050d1a380c /sys/arm/mv/discovery | |
parent | ca2e9cb3a95ecaff97ffcaba97157c04af4855c4 (diff) | |
download | FreeBSD-src-8211555cceb46a5f12326f8b579ef71985c1909f.zip FreeBSD-src-8211555cceb46a5f12326f8b579ef71985c1909f.tar.gz |
Adjust Marvell SOC support for A0 chip revision.
- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.
- Teach SOC ident routine about A0 (initial silicon version for general
audience)
Obtained from: Marvell, Semihalf
Diffstat (limited to 'sys/arm/mv/discovery')
-rw-r--r-- | sys/arm/mv/discovery/discovery.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/sys/arm/mv/discovery/discovery.c b/sys/arm/mv/discovery/discovery.c index c245fa9..5d41b92 100644 --- a/sys/arm/mv/discovery/discovery.c +++ b/sys/arm/mv/discovery/discovery.c @@ -226,3 +226,25 @@ const struct decode_win idma_win_tbl[] = { }; const struct decode_win *idma_wins = idma_win_tbl; int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); + +uint32_t +get_tclk(void) +{ + uint32_t sar; + + /* + * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. + * Current setting is read from Sample At Reset register. + */ + sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI); + sar = (sar & TCLK_MASK) >> TCLK_SHIFT; + + switch (sar) { + case 0: + return (TCLK_166MHZ); + case 1: + return (TCLK_200MHZ); + default: + panic("Unknown TCLK settings!"); + } +} |