diff options
author | raj <raj@FreeBSD.org> | 2009-01-08 13:20:28 +0000 |
---|---|---|
committer | raj <raj@FreeBSD.org> | 2009-01-08 13:20:28 +0000 |
commit | 8211555cceb46a5f12326f8b579ef71985c1909f (patch) | |
tree | 7f3438ebd8767dd6f323486c7a00d6050d1a380c /sys | |
parent | ca2e9cb3a95ecaff97ffcaba97157c04af4855c4 (diff) | |
download | FreeBSD-src-8211555cceb46a5f12326f8b579ef71985c1909f.zip FreeBSD-src-8211555cceb46a5f12326f8b579ef71985c1909f.tar.gz |
Adjust Marvell SOC support for A0 chip revision.
- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.
- Teach SOC ident routine about A0 (initial silicon version for general
audience)
Obtained from: Marvell, Semihalf
Diffstat (limited to 'sys')
-rw-r--r-- | sys/arm/mv/common.c | 15 | ||||
-rw-r--r-- | sys/arm/mv/discovery/discovery.c | 22 | ||||
-rw-r--r-- | sys/arm/mv/kirkwood/kirkwood.c | 18 | ||||
-rw-r--r-- | sys/arm/mv/mvreg.h | 32 | ||||
-rw-r--r-- | sys/arm/mv/orion/orion.c | 21 |
5 files changed, 87 insertions, 21 deletions
diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c index 5c8d003..6e03493 100644 --- a/sys/arm/mv/common.c +++ b/sys/arm/mv/common.c @@ -104,17 +104,6 @@ soc_power_ctrl_get(uint32_t mask) return (mask); } -uint32_t -get_tclk(void) -{ - -#if defined(SOC_MV_DISCOVERY) - return (TCLK_200MHZ); -#else - return (TCLK_166MHZ); -#endif -} - void soc_id(uint32_t *dev, uint32_t *rev) { @@ -165,6 +154,10 @@ soc_identify(void) break; case MV_DEV_88F6281: dev = "Marvell 88F6281"; + if (r == 0) + rev = "Z0"; + else if (r == 2) + rev = "A0"; break; case MV_DEV_MV78100: dev = "Marvell MV78100"; diff --git a/sys/arm/mv/discovery/discovery.c b/sys/arm/mv/discovery/discovery.c index c245fa9..5d41b92 100644 --- a/sys/arm/mv/discovery/discovery.c +++ b/sys/arm/mv/discovery/discovery.c @@ -226,3 +226,25 @@ const struct decode_win idma_win_tbl[] = { }; const struct decode_win *idma_wins = idma_win_tbl; int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); + +uint32_t +get_tclk(void) +{ + uint32_t sar; + + /* + * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. + * Current setting is read from Sample At Reset register. + */ + sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI); + sar = (sar & TCLK_MASK) >> TCLK_SHIFT; + + switch (sar) { + case 0: + return (TCLK_166MHZ); + case 1: + return (TCLK_200MHZ); + default: + panic("Unknown TCLK settings!"); + } +} diff --git a/sys/arm/mv/kirkwood/kirkwood.c b/sys/arm/mv/kirkwood/kirkwood.c index 0ba34aa..a8695f3 100644 --- a/sys/arm/mv/kirkwood/kirkwood.c +++ b/sys/arm/mv/kirkwood/kirkwood.c @@ -150,3 +150,21 @@ const struct decode_win cpu_win_tbl[] = { }; const struct decode_win *cpu_wins = cpu_win_tbl; int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); + +uint32_t +get_tclk(void) +{ + uint32_t dev, rev; + + /* + * On Kirkwood TCLK is not configurable and depends on silicon + * revision: + * - A0 has TCLK hardcoded to 200 MHz. + * - Z0 and others have TCLK hardcoded to 166 MHz. + */ + soc_id(&dev, &rev); + if (dev == MV_DEV_88F6281 && rev == 2) + return (TCLK_200MHZ); + + return (TCLK_166MHZ); +} diff --git a/sys/arm/mv/mvreg.h b/sys/arm/mv/mvreg.h index 9b86c07..37108f0 100644 --- a/sys/arm/mv/mvreg.h +++ b/sys/arm/mv/mvreg.h @@ -405,15 +405,29 @@ /* * MPP */ +#if defined(SOC_MV_ORION) #define MPP_CONTROL0 0x00 #define MPP_CONTROL1 0x04 #define MPP_CONTROL2 0x50 -#define DEVICE_MULTIPLEX 0x08 +#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) +#define MPP_CONTROL0 0x00 +#define MPP_CONTROL1 0x04 +#define MPP_CONTROL2 0x08 +#define MPP_CONTROL3 0x0C +#define MPP_CONTROL4 0x10 +#define MPP_CONTROL5 0x14 +#define MPP_CONTROL6 0x18 +#else +#error SOC_MV_XX not defined +#endif #if defined(SOC_MV_ORION) #define SAMPLE_AT_RESET 0x10 -#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) +#elif defined(SOC_MV_KIRKWOOD) #define SAMPLE_AT_RESET 0x30 +#elif defined(SOC_MV_DISCOVERY) +#define SAMPLE_AT_RESET_LO 0x30 +#define SAMPLE_AT_RESET_HI 0x34 #else #error SOC_MV_XX not defined #endif @@ -421,14 +435,12 @@ /* * Clocks */ -#ifdef SOC_MV_ORION -#define TCLK_MASK 0x300 -#define TCLK_SHIFT 0x8 -#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) -#define TCLK_MASK 0x30000 -#define TCLK_SHIFT 0x10 -#else -#error SOC_MV_XX not defined +#if defined(SOC_MV_ORION) +#define TCLK_MASK 0x00000300 +#define TCLK_SHIFT 0x08 +#elif defined(SOC_MV_DISCOVERY) +#define TCLK_MASK 0x00000180 +#define TCLK_SHIFT 0x07 #endif #define TCLK_100MHZ 100000000 diff --git a/sys/arm/mv/orion/orion.c b/sys/arm/mv/orion/orion.c index 5ee3bac..387e081 100644 --- a/sys/arm/mv/orion/orion.c +++ b/sys/arm/mv/orion/orion.c @@ -167,3 +167,24 @@ const struct decode_win idma_win_tbl[] = { }; const struct decode_win *idma_wins = idma_win_tbl; int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); + +uint32_t +get_tclk(void) +{ + uint32_t sar; + + /* + * On Orion TCLK is can be configured to 150 MHz or 166 MHz. + * Current setting is read from Sample At Reset register. + */ + sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET); + sar = (sar & TCLK_MASK) >> TCLK_SHIFT; + switch (sar) { + case 1: + return (TCLK_150MHZ); + case 2: + return (TCLK_166MHZ); + default: + panic("Unknown TCLK settings!"); + } +} |