Adjust Marvell SOC support for A0 chip revision.

- Clean up TCLK handling so that it's dynamically recognized depending on
  registers settings or chip version/revision. Update registers definitions.

- Teach SOC ident routine about A0 (initial silicon version for general
  audience)

Obtained from:	Marvell, Semihalf

1 files changed, 4 insertions, 11 deletions

diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c
index 5c8d003..6e03493 100644
--- a/sys/arm/mv/common.c
+++ b/sys/arm/mv/common.c
@@ -104,17 +104,6 @@ soc_power_ctrl_get(uint32_t mask)
 	return (mask);
 }
 
-uint32_t
-get_tclk(void)
-{
-
-#if defined(SOC_MV_DISCOVERY)
-	return (TCLK_200MHZ);
-#else
-	return (TCLK_166MHZ);
-#endif
-}
-
 void
 soc_id(uint32_t *dev, uint32_t *rev)
 {
@@ -165,6 +154,10 @@ soc_identify(void)
 		break;
 	case MV_DEV_88F6281:
 		dev = "Marvell 88F6281";
+		if (r == 0)
+			rev = "Z0";
+		else if (r == 2)
+			rev = "A0";
 		break;
 	case MV_DEV_MV78100:
 		dev = "Marvell MV78100";