diff options
| author | peter <peter@FreeBSD.org> | 2001-07-12 06:32:51 +0000 |
|---|---|---|
| committer | peter <peter@FreeBSD.org> | 2001-07-12 06:32:51 +0000 |
| commit | e00129231d89ad2ab6ec8862931dd864ff079d0c (patch) | |
| tree | acb374c639798d8213f972fae7e8609dec013b5f /sys/amd64/amd64/initcpu.c | |
| parent | b5164c6585fabc3c848ff92ada3f6ffb64a9e8f2 (diff) | |
| download | FreeBSD-src-e00129231d89ad2ab6ec8862931dd864ff079d0c.zip FreeBSD-src-e00129231d89ad2ab6ec8862931dd864ff079d0c.tar.gz | |
Activate SSE/SIMD. This is the extra context switching support that
we are required to do if we let user processes use the extra 128 bit
registers etc.
This is the base part of the diff I got from:
http://www.issei.org/issei/FreeBSD/sse.html
I believe this is by: Mr. SUZUKI Issei <issei@issei.org>
SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp>
Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see
http://kobe1995.net/~kaz/FreeBSD/SSE.en.html
I have fixed a couple of style(9) deviations. I have some followup
commits to fix a couple of non-style things.
Diffstat (limited to 'sys/amd64/amd64/initcpu.c')
| -rw-r--r-- | sys/amd64/amd64/initcpu.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 8b39b44..7fb56fa 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -34,6 +34,7 @@ #include <sys/param.h> #include <sys/kernel.h> #include <sys/systm.h> +#include <sys/sysctl.h> #include <machine/cputypes.h> #include <machine/md_var.h> @@ -61,8 +62,14 @@ static void init_6x86(void); static void init_6x86MX(void); static void init_ppro(void); static void init_mendocino(void); +void enable_sse(); #endif +int hw_instruction_sse = 0; +SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, + &hw_instruction_sse, 0, + "SIMD/MMX2 instructions available in CPU"); + #ifdef I486_CPU /* * IBM Blue Lightning @@ -501,6 +508,20 @@ init_mendocino(void) #endif /* CPU_PPRO2CELERON */ } +/* + * Initialize CR4 (Control register 4) to enable SSE instructions. + */ +void +enable_sse(void) +{ +#if defined(CPU_ENABLE_SSE) + if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { + load_cr4(rcr4() | CR4_FXSR | CR4_XMM); + cpu_fxsr = hw_instruction_sse = 1; + } +#endif +} + #endif /* I686_CPU */ void @@ -544,6 +565,7 @@ initializecpu(void) init_mendocino(); break; } + enable_sse(); } break; #endif |
