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-rw-r--r--cad/iverilog/Makefile6
-rw-r--r--cad/iverilog/distinfo4
-rw-r--r--cad/iverilog/pkg-plist1
3 files changed, 6 insertions, 5 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index c7e3001..40d7f16 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,10 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20040606
+PORTVERSION= 0.8
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20040606
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
+DISTNAME= verilog-$(PORTVERSION)
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index c8740fa..9aefb94 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,2 +1,2 @@
-MD5 (verilog-20040606.tar.gz) = 92704dec05a832dc9bf1cb3ba399176a
-SIZE (verilog-20040606.tar.gz) = 1361219
+MD5 (verilog-0.8.tar.gz) = 12a20a7f63183e767a9d7d077eb0556c
+SIZE (verilog-0.8.tar.gz) = 1371542
diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist
index 00d41c3..0542de33 100644
--- a/cad/iverilog/pkg-plist
+++ b/cad/iverilog/pkg-plist
@@ -15,6 +15,7 @@ lib/ivl/ivlpp
lib/ivl/null-s.conf
lib/ivl/null.conf
lib/ivl/null.tgt
+lib/ivl/system.sft
lib/ivl/system.vpi
lib/ivl/vvp-s.conf
lib/ivl/vvp.conf
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