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-rw-r--r--cad/iverilog/Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index c7e3001..40d7f16 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,10 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20040606
+PORTVERSION= 0.8
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20040606
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
+DISTNAME= verilog-$(PORTVERSION)
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
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