blob: 67f42a7178d55bc776bbd418a0089722b13ed9ee (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
library = s3estarter
top = top_tb
verilogfiles = ../rtl_tb/ddr.v
software_dir = ../software/test
#software_dir = ../software/ethernet_speed
# http://sourceforge.net/projects/vmk/
VMK = vmk
# generate list of used libs
library_list = $(shell cut vhdl_files.txt --field 1 --delimiter=' ' | sort --unique)
all: compile simulate
software:
test ! -d $(software_dir) || make --directory $(software_dir) | ccze -A
compile: Makefile.msim
export ANAFLAGS="-quiet -2008"; \
make -f Makefile.msim | ccze -A
simulate:
export top=$(top); \
vsim -quiet -gui $(library).$(top) -do run.do -l transcript.log
clean:
@# sim stuff
rm -f transcript.log
rm -f *.wlf
rm -f wlf*
@# compile stuff
-make -f Makefile.msim clean
rm -rf $(library_list)
rm -f Makefile.msim
rm -f .stamp
# generate Makefile.msim with vmk
Makefile.msim: software vhdl_files.txt $(library_list)
$(VMK) -t modelsim -O -w $(library) -F vhdl_files.txt
$(library_list):
vlib $@
|
