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authorBert Lange <b.lange@hzdr.de>2015-04-15 13:36:55 +0200
committerBert Lange <b.lange@hzdr.de>2015-04-15 13:36:55 +0200
commita1c964908b51599bf624bd2d253419c7e629f195 (patch)
tree06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
parentbbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff)
parent8679e4f91dcae05aef40f96629f33f0f4161f14a (diff)
downloadzpu-a1c964908b51599bf624bd2d253419c7e629f195.zip
zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java')
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java126
1 files changed, 126 insertions, 0 deletions
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
new file mode 100644
index 0000000..663e68f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -0,0 +1,126 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Phi extends Simulator
+{
+ @Override
+ protected long getSampleOffset()
+ {
+
+ return super.getSampleOffset()-(0x5e7b2-0x0005E7C0);
+ }
+
+
+ public static void main(String[] args)
+ {
+ new SimApp(new SimFactory()
+ {
+ public Simulator create()
+ {
+ return new Phi();
+ }
+ }).run(args);
+ }
+
+
+ protected int getIO()
+ {
+ return 0x08000000;
+ }
+
+
+
+ protected int ioRead(int addr) throws CPUException
+ {
+ switch (addr)
+ {
+
+ case 0x080a0020:
+ return interrupt?0:1; // interrupt mask
+
+
+
+ /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+ case 0x080a000c:
+ return 0x100; // buffer ready.
+
+ case 0x080a0014:
+ case 0x080a0018:
+ return readSampledTimer(addr, 0x080a0014);
+
+ case 0x080a0030:
+ return timerPending?1:0;
+ case 0x080a0038:
+ return (int)(timerInterval-1-((cycles-lastTimer)%timerInterval));
+
+
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+
+
+ protected void ioWrite(int addr, int val) throws MemoryAccessException
+ {
+ switch (addr)
+ {
+ case 0x080a0020:
+ interrupt=(val&1)==0;
+ return;
+ case 0x080a002c:
+ timer=(val&0x1)!=0;
+ break;
+ case 0x080a0030:
+ if ((val&0x1)!=0)
+ {
+ timerPending=false;
+ }
+ if ((val&0x2)!=0)
+ {
+ lastTimer=cycles;
+ }
+ break;
+ case 0x080a0034:
+ timerInterval=val;
+ return;
+
+ case 0x080a0014:
+ writeTimerSampleReg(val);
+ case 0x080a000c:
+ syscall.writeUART(val);
+ break;
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+ public Phi() throws CPUException
+ {
+ }
+
+ protected boolean emulateConfig()
+ {
+ return true;
+ }
+
+ protected int getStartStack()
+ {
+ return getRAMSIZE()-8;
+ }
+
+ protected int getRAMSIZE()
+ {
+ return 2*1024*1024;
+ }
+
+
+ protected int getIOSIZE()
+ {
+ return 0x100000;
+ }
+
+}
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