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author | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
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committer | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
commit | a1c964908b51599bf624bd2d253419c7e629f195 (patch) | |
tree | 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java | |
parent | bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff) | |
parent | 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff) | |
download | zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz |
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java')
-rw-r--r-- | zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java new file mode 100644 index 0000000..8d8667c --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java @@ -0,0 +1,109 @@ + +package com.zylin.zpu.simulator; + +import com.zylin.zpu.simulator.exceptions.CPUException; +import com.zylin.zpu.simulator.exceptions.MemoryAccessException; + +public class Abel extends Simulator +{ + + protected int getIO() + { + return 0x8000; + } + + + + protected int ioRead(int addr) throws CPUException + { + switch (addr) + { + case 0xc000: + return syscall.readUART(); + + /* FIFO empty? bit 0, FIFO full bit 1(never the case) */ + case 0xc004: + return syscall.readFIFO(); + + case 0x9000: + case 0x9004: + case 0x9008: + case 0x900c: + + case 0x9010: + case 0x9014: + case 0x9018: + case 0x901c: + return readSampledTimer(addr, 0x9000); + + case 0x8800: + return readMHz(); + + default: + throw new MemoryAccessException(); + } + } + + /* + ; Read/write are on different addresses + ; The registers are 8 bits and mapped to bit[7:0] + ; + ; 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + ; Read : Reads from UART RX FIFO (4 byte FIFO) + ; 0xC004 Read : UART status register + ; Bit 0 = RX FIFO empty + ; Bit 1 = TX FIFO full + ; 0xA000 Write: 8 LED's + */ + + /* + 0x9000 Write: bit 0: 1= reset counter + 0= counter running + bit 1: 1= sample counter (when set to 1) + 0=not used + Read : counter bit[7:0] + 0x9004 Read: counter bit [15:8] + 0x9008 Read: counter bit [23:16] + 0x900C Read: counter bit [31:24] + 0x9010 Read: counter bit [39:32] + 0x9014 Read: counter bit [47:40] + 0x9018 Read: counter bit [55:48] + 0x901C Read: counter bit [63:56] + + 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + */ + + protected void ioWrite(int addr, int val) throws MemoryAccessException + { + switch (addr) + { + case 0x9000: + writeTimerSampleReg(val); + case 0xc000: + syscall.writeUART(val); + break; + default: + throw new MemoryAccessException(); + } + } + + Abel() throws CPUException + { + } + + protected boolean emulateConfig() + { + return true; + } + + protected int getStartStack() + { + return getRAMSIZE()-8; + } + + protected int getRAMSIZE() + { + return 32768; + } + +} |